2 * linux/arch/ia64/kernel/irq.c
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
17 #include <linux/config.h>
18 #include <linux/module.h>
20 #include <linux/jiffies.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/slab.h>
27 #include <linux/ptrace.h>
28 #include <linux/random.h> /* for rand_initialize_irq() */
29 #include <linux/signal.h>
30 #include <linux/smp.h>
31 #include <linux/smp_lock.h>
32 #include <linux/threads.h>
34 #include <asm/bitops.h>
35 #include <asm/delay.h>
36 #include <asm/intrinsics.h>
38 #include <asm/hw_irq.h>
39 #include <asm/machvec.h>
40 #include <asm/pgtable.h>
41 #include <asm/system.h>
44 # include <asm/perfmon.h>
49 /* default base addr of IPI table */
50 void __iomem *ipi_base_addr = ((void __iomem *)
51 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
54 * Legacy IRQ to IA-64 vector translation table.
56 __u8 isa_irq_to_vector_map[16] = {
57 /* 8259 IRQ translation, first 16 entries */
58 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
59 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
61 EXPORT_SYMBOL(isa_irq_to_vector_map);
66 preempt_count() += HARDIRQ_OFFSET;
72 preempt_count() -= IRQ_EXIT_OFFSET;
73 if (!in_interrupt() && local_softirq_pending())
75 preempt_enable_no_resched();
79 assign_irq_vector (int irq)
81 static int next_vector = IA64_FIRST_DEVICE_VECTOR;
83 if (next_vector > IA64_LAST_DEVICE_VECTOR)
84 /* XXX could look for sharable vectors instead of panic'ing... */
85 panic("assign_irq_vector: out of interrupt vectors!");
89 extern unsigned int do_IRQ(unsigned long irq, struct pt_regs *regs);
92 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
94 # define IS_RESCHEDULE(vec) (0)
97 * That's where the IVT branches when we get an external
98 * interrupt. This branches to the correct hardware IRQ handler via
102 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
104 unsigned long saved_tpr;
108 unsigned long bsp, sp;
111 * Note: if the interrupt happened while executing in
112 * the context switch routine (ia64_switch_to), we may
113 * get a spurious stack overflow here. This is
114 * because the register and the memory stack are not
115 * switched atomically.
117 bsp = ia64_getreg(_IA64_REG_AR_BSP);
118 sp = ia64_getreg(_IA64_REG_AR_SP);
120 if ((sp - bsp) < 1024) {
121 static unsigned char count;
122 static long last_time;
124 if (jiffies - last_time > 5*HZ)
128 printk("ia64_handle_irq: DANGER: less than "
129 "1KB of free stack space!!\n"
130 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
134 #endif /* IRQ_DEBUG */
137 * Always set TPR to limit maximum interrupt nesting depth to
138 * 16 (without this, it would be ~240, which could easily lead
139 * to kernel stack overflows).
142 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
144 while (vector != IA64_SPURIOUS_INT_VECTOR) {
145 if (!IS_RESCHEDULE(vector)) {
146 ia64_setreg(_IA64_REG_CR_TPR, vector);
149 do_IRQ(local_vector_to_irq(vector), regs);
152 * Disable interrupts and send EOI:
155 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
158 vector = ia64_get_ivr();
161 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
162 * handler needs to be able to wait for further keyboard interrupts, which can't
163 * come through until ia64_eoi() has been done.
168 #ifdef CONFIG_HOTPLUG_CPU
170 * This function emulates a interrupt processing when a cpu is about to be
173 void ia64_process_pending_intr(void)
176 unsigned long saved_tpr;
177 extern unsigned int vectors_in_migration[NR_IRQS];
179 vector = ia64_get_ivr();
182 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
186 * Perform normal interrupt style processing
188 while (vector != IA64_SPURIOUS_INT_VECTOR) {
189 if (!IS_RESCHEDULE(vector)) {
190 ia64_setreg(_IA64_REG_CR_TPR, vector);
194 * Now try calling normal ia64_handle_irq as it would have got called
195 * from a real intr handler. Try passing null for pt_regs, hopefully
196 * it will work. I hope it works!.
197 * Probably could shared code.
199 vectors_in_migration[local_vector_to_irq(vector)]=0;
200 do_IRQ(local_vector_to_irq(vector), NULL);
203 * Disable interrupts and send EOI
206 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
209 vector = ia64_get_ivr();
217 extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
219 static struct irqaction ipi_irqaction = {
220 .handler = handle_IPI,
221 .flags = SA_INTERRUPT,
227 register_percpu_irq (ia64_vector vec, struct irqaction *action)
232 for (irq = 0; irq < NR_IRQS; ++irq)
233 if (irq_to_vector(irq) == vec) {
234 desc = irq_descp(irq);
235 desc->status |= IRQ_PER_CPU;
236 desc->handler = &irq_type_ia64_lsapic;
238 setup_irq(irq, action);
245 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
247 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
249 #ifdef CONFIG_PERFMON
256 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
258 void __iomem *ipi_addr;
259 unsigned long ipi_data;
260 unsigned long phys_cpu_id;
263 phys_cpu_id = cpu_physical_id(cpu);
265 phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
269 * cpu number is in 8bit ID and 8bit EID
272 ipi_data = (delivery_mode << 8) | (vector & 0xff);
273 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
275 writeq(ipi_data, ipi_addr);