2 * linux/arch/ia64/kernel/irq.c
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
17 #include <linux/config.h>
18 #include <linux/module.h>
20 #include <linux/jiffies.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/slab.h>
27 #include <linux/ptrace.h>
28 #include <linux/random.h> /* for rand_initialize_irq() */
29 #include <linux/signal.h>
30 #include <linux/smp.h>
31 #include <linux/smp_lock.h>
32 #include <linux/threads.h>
34 #include <asm/bitops.h>
35 #include <asm/delay.h>
36 #include <asm/intrinsics.h>
38 #include <asm/hw_irq.h>
39 #include <asm/machvec.h>
40 #include <asm/pgtable.h>
41 #include <asm/system.h>
44 # include <asm/perfmon.h>
49 /* default base addr of IPI table */
50 unsigned long ipi_base_addr = (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR);
53 * Legacy IRQ to IA-64 vector translation table.
55 __u8 isa_irq_to_vector_map[16] = {
56 /* 8259 IRQ translation, first 16 entries */
57 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
58 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
60 EXPORT_SYMBOL(isa_irq_to_vector_map);
65 preempt_count() += HARDIRQ_OFFSET;
71 preempt_count() -= IRQ_EXIT_OFFSET;
72 if (!in_interrupt() && local_softirq_pending())
74 preempt_enable_no_resched();
78 assign_irq_vector (int irq)
80 static int next_vector = IA64_FIRST_DEVICE_VECTOR;
82 if (next_vector > IA64_LAST_DEVICE_VECTOR)
83 /* XXX could look for sharable vectors instead of panic'ing... */
84 panic("assign_irq_vector: out of interrupt vectors!");
88 extern unsigned int do_IRQ(unsigned long irq, struct pt_regs *regs);
91 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
93 # define IS_RESCHEDULE(vec) (0)
96 * That's where the IVT branches when we get an external
97 * interrupt. This branches to the correct hardware IRQ handler via
101 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
103 unsigned long saved_tpr;
107 unsigned long bsp, sp;
110 * Note: if the interrupt happened while executing in
111 * the context switch routine (ia64_switch_to), we may
112 * get a spurious stack overflow here. This is
113 * because the register and the memory stack are not
114 * switched atomically.
116 bsp = ia64_getreg(_IA64_REG_AR_BSP);
117 sp = ia64_getreg(_IA64_REG_AR_SP);
119 if ((sp - bsp) < 1024) {
120 static unsigned char count;
121 static long last_time;
123 if (jiffies - last_time > 5*HZ)
127 printk("ia64_handle_irq: DANGER: less than "
128 "1KB of free stack space!!\n"
129 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
133 #endif /* IRQ_DEBUG */
136 * Always set TPR to limit maximum interrupt nesting depth to
137 * 16 (without this, it would be ~240, which could easily lead
138 * to kernel stack overflows).
141 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
143 while (vector != IA64_SPURIOUS_INT_VECTOR) {
144 if (!IS_RESCHEDULE(vector)) {
145 ia64_setreg(_IA64_REG_CR_TPR, vector);
148 do_IRQ(local_vector_to_irq(vector), regs);
151 * Disable interrupts and send EOI:
154 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
157 vector = ia64_get_ivr();
160 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
161 * handler needs to be able to wait for further keyboard interrupts, which can't
162 * come through until ia64_eoi() has been done.
167 #ifdef CONFIG_HOTPLUG_CPU
169 * This function emulates a interrupt processing when a cpu is about to be
172 void ia64_process_pending_intr(void)
175 unsigned long saved_tpr;
176 extern unsigned int vectors_in_migration[NR_IRQS];
178 vector = ia64_get_ivr();
181 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
185 * Perform normal interrupt style processing
187 while (vector != IA64_SPURIOUS_INT_VECTOR) {
188 if (!IS_RESCHEDULE(vector)) {
189 ia64_setreg(_IA64_REG_CR_TPR, vector);
193 * Now try calling normal ia64_handle_irq as it would have got called
194 * from a real intr handler. Try passing null for pt_regs, hopefully
195 * it will work. I hope it works!.
196 * Probably could shared code.
198 vectors_in_migration[local_vector_to_irq(vector)]=0;
199 do_IRQ(local_vector_to_irq(vector), NULL);
202 * Disable interrupts and send EOI
205 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
208 vector = ia64_get_ivr();
216 extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
218 static struct irqaction ipi_irqaction = {
219 .handler = handle_IPI,
220 .flags = SA_INTERRUPT,
226 register_percpu_irq (ia64_vector vec, struct irqaction *action)
231 for (irq = 0; irq < NR_IRQS; ++irq)
232 if (irq_to_vector(irq) == vec) {
233 desc = irq_descp(irq);
234 desc->status |= IRQ_PER_CPU;
235 desc->handler = &irq_type_ia64_lsapic;
237 setup_irq(irq, action);
244 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
246 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
248 #ifdef CONFIG_PERFMON
255 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
257 unsigned long ipi_addr;
258 unsigned long ipi_data;
259 unsigned long phys_cpu_id;
262 phys_cpu_id = cpu_physical_id(cpu);
264 phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
268 * cpu number is in 8bit ID and 8bit EID
271 ipi_data = (delivery_mode << 8) | (vector & 0xff);
272 ipi_addr = ipi_base_addr | (phys_cpu_id << 4) | ((redirect & 1) << 3);
274 writeq(ipi_data, ipi_addr);