3 * Purpose: Generic MCA handling layer
5 * Updated for latest kernel
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Dell Inc.
10 * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
12 * Copyright (C) 2002 Intel
13 * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
15 * Copyright (C) 2001 Intel
16 * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
18 * Copyright (C) 2000 Intel
19 * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
21 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22 * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
24 * 03/04/15 D. Mosberger Added INIT backtrace support.
25 * 02/03/25 M. Domsch GUID cleanups
27 * 02/01/04 J. Hall Aligned MCA stack to 16 bytes, added platform vs. CPU
28 * error flag, set SAL default return values, changed
29 * error record structure to linked list, added init call
30 * to sal_get_state_info_size().
32 * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected
33 * platform errors, completed code for logging of
34 * corrected & uncorrected machine check errors, and
35 * updated for conformance with Nov. 2000 revision of the
37 * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38 * added min save state dump, added INIT handler.
40 * 2003-12-08 Keith Owens <kaos@sgi.com>
41 * smp_call_function() must not be called from interrupt context (can
42 * deadlock on tasklist_lock). Use keventd to call smp_call_function().
44 * 2004-02-01 Keith Owens <kaos@sgi.com>
45 * Avoid deadlock when using printk() for MCA and INIT records.
46 * Delete all record printing code, moved to salinfo_decode in user space.
47 * Mark variables and functions static where possible.
48 * Delete dead variables and functions.
49 * Reorder to remove the need for forward declarations and to consolidate
52 #include <linux/config.h>
53 #include <linux/types.h>
54 #include <linux/init.h>
55 #include <linux/sched.h>
56 #include <linux/interrupt.h>
57 #include <linux/irq.h>
58 #include <linux/kallsyms.h>
59 #include <linux/smp_lock.h>
60 #include <linux/bootmem.h>
61 #include <linux/acpi.h>
62 #include <linux/timer.h>
63 #include <linux/module.h>
64 #include <linux/kernel.h>
65 #include <linux/smp.h>
66 #include <linux/workqueue.h>
68 #include <asm/delay.h>
69 #include <asm/machvec.h>
71 #include <asm/ptrace.h>
72 #include <asm/system.h>
77 #include <asm/hw_irq.h>
79 #if defined(IA64_MCA_DEBUG_INFO)
80 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
82 # define IA64_MCA_DEBUG(fmt...)
85 typedef struct ia64_fptr {
90 /* Used by mca_asm.S */
91 ia64_mca_sal_to_os_state_t ia64_sal_to_os_handoff_state;
92 ia64_mca_os_to_sal_state_t ia64_os_to_sal_handoff_state;
93 u64 ia64_mca_proc_state_dump[512];
94 u64 ia64_mca_stack[1024] __attribute__((aligned(16)));
95 u64 ia64_mca_stackframe[32];
96 u64 ia64_mca_bspstore[1024];
97 u64 ia64_init_stack[KERNEL_STACK_SIZE/8] __attribute__((aligned(16)));
98 u64 ia64_mca_serialize;
101 extern void ia64_monarch_init_handler (void);
102 extern void ia64_slave_init_handler (void);
104 static ia64_mc_info_t ia64_mc_info;
106 struct ia64_mca_tlb_info ia64_mca_tlb_list[NR_CPUS];
108 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
109 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
110 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
111 #define CMC_HISTORY_LENGTH 5
113 static struct timer_list cpe_poll_timer;
114 static struct timer_list cmc_poll_timer;
116 * This variable tells whether we are currently in polling mode.
117 * Start with this in the wrong state so we won't play w/ timers
118 * before the system is ready.
120 static int cmc_polling_enabled = 1;
123 * Clearing this variable prevents CPE polling from getting activated
124 * in mca_late_init. Use it if your system doesn't provide a CPEI,
125 * but encounters problems retrieving CPE logs. This should only be
126 * necessary for debugging.
128 static int cpe_poll_enabled = 1;
130 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
133 * IA64_MCA log support
135 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
136 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
138 typedef struct ia64_state_log_s
142 unsigned long isl_count;
143 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
146 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
148 #define IA64_LOG_ALLOCATE(it, size) \
149 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
150 (ia64_err_rec_t *)alloc_bootmem(size); \
151 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
152 (ia64_err_rec_t *)alloc_bootmem(size);}
153 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
154 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
155 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
156 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
157 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
158 #define IA64_LOG_INDEX_INC(it) \
159 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
160 ia64_state_log[it].isl_count++;}
161 #define IA64_LOG_INDEX_DEC(it) \
162 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
163 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
164 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
165 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
169 * Reset the OS ia64 log buffer
170 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
174 ia64_log_init(int sal_info_type)
178 IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
179 IA64_LOG_LOCK_INIT(sal_info_type);
181 // SAL will tell us the maximum size of any error record of this type
182 max_size = ia64_sal_get_state_info_size(sal_info_type);
184 /* alloc_bootmem() doesn't like zero-sized allocations! */
187 // set up OS data structures to hold error info
188 IA64_LOG_ALLOCATE(sal_info_type, max_size);
189 memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
190 memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
196 * Get the current MCA log from SAL and copy it into the OS log buffer.
198 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
199 * irq_safe whether you can use printk at this point
200 * Outputs : size (total record length)
201 * *buffer (ptr to error record)
205 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
207 sal_log_record_header_t *log_buffer;
211 IA64_LOG_LOCK(sal_info_type);
213 /* Get the process state information */
214 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
216 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
219 IA64_LOG_INDEX_INC(sal_info_type);
220 IA64_LOG_UNLOCK(sal_info_type);
222 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
223 "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
225 *buffer = (u8 *) log_buffer;
228 IA64_LOG_UNLOCK(sal_info_type);
234 * ia64_mca_log_sal_error_record
236 * This function retrieves a specified error record type from SAL
237 * and wakes up any processes waiting for error records.
239 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE/INIT)
242 ia64_mca_log_sal_error_record(int sal_info_type)
246 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA && sal_info_type != SAL_INFO_TYPE_INIT;
247 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
249 size = ia64_log_get(sal_info_type, &buffer, irq_safe);
253 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
256 printk(KERN_INFO "CPU %d: SAL log contains %s error record\n",
258 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
260 /* Clear logs from corrected errors in case there's no user-level logger */
261 if (sal_info_type == SAL_INFO_TYPE_CPE || sal_info_type == SAL_INFO_TYPE_CMC)
262 ia64_sal_clear_state_info(sal_info_type);
266 * platform dependent error handling
268 #ifndef PLATFORM_MCA_HANDLERS
271 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
273 IA64_MCA_DEBUG("%s: received interrupt. CPU:%d vector = %#x\n",
274 __FUNCTION__, smp_processor_id(), cpe_irq);
276 /* SAL spec states this should run w/ interrupts enabled */
279 /* Get the CMC error record and log it */
280 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
285 show_min_state (pal_min_state_area_t *minstate)
287 u64 iip = minstate->pmsa_iip + ((struct ia64_psr *)(&minstate->pmsa_ipsr))->ri;
288 u64 xip = minstate->pmsa_xip + ((struct ia64_psr *)(&minstate->pmsa_xpsr))->ri;
290 printk("NaT bits\t%016lx\n", minstate->pmsa_nat_bits);
291 printk("pr\t\t%016lx\n", minstate->pmsa_pr);
292 printk("b0\t\t%016lx ", minstate->pmsa_br0); print_symbol("%s\n", minstate->pmsa_br0);
293 printk("ar.rsc\t\t%016lx\n", minstate->pmsa_rsc);
294 printk("cr.iip\t\t%016lx ", iip); print_symbol("%s\n", iip);
295 printk("cr.ipsr\t\t%016lx\n", minstate->pmsa_ipsr);
296 printk("cr.ifs\t\t%016lx\n", minstate->pmsa_ifs);
297 printk("xip\t\t%016lx ", xip); print_symbol("%s\n", xip);
298 printk("xpsr\t\t%016lx\n", minstate->pmsa_xpsr);
299 printk("xfs\t\t%016lx\n", minstate->pmsa_xfs);
300 printk("b1\t\t%016lx ", minstate->pmsa_br1);
301 print_symbol("%s\n", minstate->pmsa_br1);
303 printk("\nstatic registers r0-r15:\n");
304 printk(" r0- 3 %016lx %016lx %016lx %016lx\n",
305 0UL, minstate->pmsa_gr[0], minstate->pmsa_gr[1], minstate->pmsa_gr[2]);
306 printk(" r4- 7 %016lx %016lx %016lx %016lx\n",
307 minstate->pmsa_gr[3], minstate->pmsa_gr[4],
308 minstate->pmsa_gr[5], minstate->pmsa_gr[6]);
309 printk(" r8-11 %016lx %016lx %016lx %016lx\n",
310 minstate->pmsa_gr[7], minstate->pmsa_gr[8],
311 minstate->pmsa_gr[9], minstate->pmsa_gr[10]);
312 printk("r12-15 %016lx %016lx %016lx %016lx\n",
313 minstate->pmsa_gr[11], minstate->pmsa_gr[12],
314 minstate->pmsa_gr[13], minstate->pmsa_gr[14]);
316 printk("\nbank 0:\n");
317 printk("r16-19 %016lx %016lx %016lx %016lx\n",
318 minstate->pmsa_bank0_gr[0], minstate->pmsa_bank0_gr[1],
319 minstate->pmsa_bank0_gr[2], minstate->pmsa_bank0_gr[3]);
320 printk("r20-23 %016lx %016lx %016lx %016lx\n",
321 minstate->pmsa_bank0_gr[4], minstate->pmsa_bank0_gr[5],
322 minstate->pmsa_bank0_gr[6], minstate->pmsa_bank0_gr[7]);
323 printk("r24-27 %016lx %016lx %016lx %016lx\n",
324 minstate->pmsa_bank0_gr[8], minstate->pmsa_bank0_gr[9],
325 minstate->pmsa_bank0_gr[10], minstate->pmsa_bank0_gr[11]);
326 printk("r28-31 %016lx %016lx %016lx %016lx\n",
327 minstate->pmsa_bank0_gr[12], minstate->pmsa_bank0_gr[13],
328 minstate->pmsa_bank0_gr[14], minstate->pmsa_bank0_gr[15]);
330 printk("\nbank 1:\n");
331 printk("r16-19 %016lx %016lx %016lx %016lx\n",
332 minstate->pmsa_bank1_gr[0], minstate->pmsa_bank1_gr[1],
333 minstate->pmsa_bank1_gr[2], minstate->pmsa_bank1_gr[3]);
334 printk("r20-23 %016lx %016lx %016lx %016lx\n",
335 minstate->pmsa_bank1_gr[4], minstate->pmsa_bank1_gr[5],
336 minstate->pmsa_bank1_gr[6], minstate->pmsa_bank1_gr[7]);
337 printk("r24-27 %016lx %016lx %016lx %016lx\n",
338 minstate->pmsa_bank1_gr[8], minstate->pmsa_bank1_gr[9],
339 minstate->pmsa_bank1_gr[10], minstate->pmsa_bank1_gr[11]);
340 printk("r28-31 %016lx %016lx %016lx %016lx\n",
341 minstate->pmsa_bank1_gr[12], minstate->pmsa_bank1_gr[13],
342 minstate->pmsa_bank1_gr[14], minstate->pmsa_bank1_gr[15]);
346 fetch_min_state (pal_min_state_area_t *ms, struct pt_regs *pt, struct switch_stack *sw)
348 u64 *dst_banked, *src_banked, bit, shift, nat_bits;
352 * First, update the pt-regs and switch-stack structures with the contents stored
353 * in the min-state area:
355 if (((struct ia64_psr *) &ms->pmsa_ipsr)->ic == 0) {
356 pt->cr_ipsr = ms->pmsa_xpsr;
357 pt->cr_iip = ms->pmsa_xip;
358 pt->cr_ifs = ms->pmsa_xfs;
360 pt->cr_ipsr = ms->pmsa_ipsr;
361 pt->cr_iip = ms->pmsa_iip;
362 pt->cr_ifs = ms->pmsa_ifs;
364 pt->ar_rsc = ms->pmsa_rsc;
365 pt->pr = ms->pmsa_pr;
366 pt->r1 = ms->pmsa_gr[0];
367 pt->r2 = ms->pmsa_gr[1];
368 pt->r3 = ms->pmsa_gr[2];
369 sw->r4 = ms->pmsa_gr[3];
370 sw->r5 = ms->pmsa_gr[4];
371 sw->r6 = ms->pmsa_gr[5];
372 sw->r7 = ms->pmsa_gr[6];
373 pt->r8 = ms->pmsa_gr[7];
374 pt->r9 = ms->pmsa_gr[8];
375 pt->r10 = ms->pmsa_gr[9];
376 pt->r11 = ms->pmsa_gr[10];
377 pt->r12 = ms->pmsa_gr[11];
378 pt->r13 = ms->pmsa_gr[12];
379 pt->r14 = ms->pmsa_gr[13];
380 pt->r15 = ms->pmsa_gr[14];
381 dst_banked = &pt->r16; /* r16-r31 are contiguous in struct pt_regs */
382 src_banked = ms->pmsa_bank1_gr;
383 for (i = 0; i < 16; ++i)
384 dst_banked[i] = src_banked[i];
385 pt->b0 = ms->pmsa_br0;
386 sw->b1 = ms->pmsa_br1;
388 /* construct the NaT bits for the pt-regs structure: */
389 # define PUT_NAT_BIT(dst, addr) \
391 bit = nat_bits & 1; nat_bits >>= 1; \
392 shift = ((unsigned long) addr >> 3) & 0x3f; \
393 dst = ((dst) & ~(1UL << shift)) | (bit << shift); \
396 /* Rotate the saved NaT bits such that bit 0 corresponds to pmsa_gr[0]: */
397 shift = ((unsigned long) &ms->pmsa_gr[0] >> 3) & 0x3f;
398 nat_bits = (ms->pmsa_nat_bits >> shift) | (ms->pmsa_nat_bits << (64 - shift));
400 PUT_NAT_BIT(sw->caller_unat, &pt->r1);
401 PUT_NAT_BIT(sw->caller_unat, &pt->r2);
402 PUT_NAT_BIT(sw->caller_unat, &pt->r3);
403 PUT_NAT_BIT(sw->ar_unat, &sw->r4);
404 PUT_NAT_BIT(sw->ar_unat, &sw->r5);
405 PUT_NAT_BIT(sw->ar_unat, &sw->r6);
406 PUT_NAT_BIT(sw->ar_unat, &sw->r7);
407 PUT_NAT_BIT(sw->caller_unat, &pt->r8); PUT_NAT_BIT(sw->caller_unat, &pt->r9);
408 PUT_NAT_BIT(sw->caller_unat, &pt->r10); PUT_NAT_BIT(sw->caller_unat, &pt->r11);
409 PUT_NAT_BIT(sw->caller_unat, &pt->r12); PUT_NAT_BIT(sw->caller_unat, &pt->r13);
410 PUT_NAT_BIT(sw->caller_unat, &pt->r14); PUT_NAT_BIT(sw->caller_unat, &pt->r15);
411 nat_bits >>= 16; /* skip over bank0 NaT bits */
412 PUT_NAT_BIT(sw->caller_unat, &pt->r16); PUT_NAT_BIT(sw->caller_unat, &pt->r17);
413 PUT_NAT_BIT(sw->caller_unat, &pt->r18); PUT_NAT_BIT(sw->caller_unat, &pt->r19);
414 PUT_NAT_BIT(sw->caller_unat, &pt->r20); PUT_NAT_BIT(sw->caller_unat, &pt->r21);
415 PUT_NAT_BIT(sw->caller_unat, &pt->r22); PUT_NAT_BIT(sw->caller_unat, &pt->r23);
416 PUT_NAT_BIT(sw->caller_unat, &pt->r24); PUT_NAT_BIT(sw->caller_unat, &pt->r25);
417 PUT_NAT_BIT(sw->caller_unat, &pt->r26); PUT_NAT_BIT(sw->caller_unat, &pt->r27);
418 PUT_NAT_BIT(sw->caller_unat, &pt->r28); PUT_NAT_BIT(sw->caller_unat, &pt->r29);
419 PUT_NAT_BIT(sw->caller_unat, &pt->r30); PUT_NAT_BIT(sw->caller_unat, &pt->r31);
423 init_handler_platform (pal_min_state_area_t *ms,
424 struct pt_regs *pt, struct switch_stack *sw)
426 struct unw_frame_info info;
428 /* if a kernel debugger is available call it here else just dump the registers */
431 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
432 * generated via the BMC's command-line interface, but since the console is on the
433 * same serial line, the user will need some time to switch out of the BMC before
436 printk("Delaying for 5 seconds...\n");
440 printk("Backtrace of current task (pid %d, %s)\n", current->pid, current->comm);
441 fetch_min_state(ms, pt, sw);
442 unw_init_from_interruption(&info, current, pt, sw);
443 ia64_do_show_stack(&info, NULL);
446 /* read_trylock() would be handy... */
447 if (!tasklist_lock.write_lock)
448 read_lock(&tasklist_lock);
451 struct task_struct *g, *t;
452 do_each_thread (g, t) {
456 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
458 } while_each_thread (g, t);
461 if (!tasklist_lock.write_lock)
462 read_unlock(&tasklist_lock);
465 printk("\nINIT dump complete. Please reboot now.\n");
466 while (1); /* hang city if no debugger */
471 * ia64_mca_register_cpev
473 * Register the corrected platform error vector with SAL.
476 * cpev Corrected Platform Error Vector number
482 ia64_mca_register_cpev (int cpev)
484 /* Register the CPE interrupt vector with SAL */
485 struct ia64_sal_retval isrv;
487 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
489 printk(KERN_ERR "Failed to register Corrected Platform "
490 "Error interrupt vector with SAL (status %ld)\n", isrv.status);
494 IA64_MCA_DEBUG("%s: corrected platform error "
495 "vector %#x setup and enabled\n", __FUNCTION__, cpev);
497 #endif /* CONFIG_ACPI */
499 #endif /* PLATFORM_MCA_HANDLERS */
502 * ia64_mca_cmc_vector_setup
504 * Setup the corrected machine check vector register in the processor and
505 * unmask interrupt. This function is invoked on a per-processor basis.
514 ia64_mca_cmc_vector_setup (void)
518 cmcv.cmcv_regval = 0;
519 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
520 cmcv.cmcv_vector = IA64_CMC_VECTOR;
521 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
523 IA64_MCA_DEBUG("%s: CPU %d corrected "
524 "machine check vector %#x setup and enabled.\n",
525 __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
527 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
528 __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
532 * ia64_mca_cmc_vector_disable
534 * Mask the corrected machine check vector register in the processor.
535 * This function is invoked on a per-processor basis.
544 ia64_mca_cmc_vector_disable (void *dummy)
548 cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV);
550 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
551 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval)
553 IA64_MCA_DEBUG("%s: CPU %d corrected "
554 "machine check vector %#x disabled.\n",
555 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
559 * ia64_mca_cmc_vector_enable
561 * Unmask the corrected machine check vector register in the processor.
562 * This function is invoked on a per-processor basis.
571 ia64_mca_cmc_vector_enable (void *dummy)
575 cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV);
577 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
578 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval)
580 IA64_MCA_DEBUG("%s: CPU %d corrected "
581 "machine check vector %#x enabled.\n",
582 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
586 * ia64_mca_cmc_vector_disable_keventd
588 * Called via keventd (smp_call_function() is not safe in interrupt context) to
589 * disable the cmc interrupt vector.
592 ia64_mca_cmc_vector_disable_keventd(void *unused)
594 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
598 * ia64_mca_cmc_vector_enable_keventd
600 * Called via keventd (smp_call_function() is not safe in interrupt context) to
601 * enable the cmc interrupt vector.
604 ia64_mca_cmc_vector_enable_keventd(void *unused)
606 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
610 * ia64_mca_wakeup_ipi_wait
612 * Wait for the inter-cpu interrupt to be sent by the
613 * monarch processor once it is done with handling the
620 ia64_mca_wakeup_ipi_wait(void)
622 int irr_num = (IA64_MCA_WAKEUP_VECTOR >> 6);
623 int irr_bit = (IA64_MCA_WAKEUP_VECTOR & 0x3f);
629 irr = ia64_getreg(_IA64_REG_CR_IRR0);
632 irr = ia64_getreg(_IA64_REG_CR_IRR1);
635 irr = ia64_getreg(_IA64_REG_CR_IRR2);
638 irr = ia64_getreg(_IA64_REG_CR_IRR3);
641 } while (!(irr & (1UL << irr_bit))) ;
647 * Send an inter-cpu interrupt to wake-up a particular cpu
648 * and mark that cpu to be out of rendez.
654 ia64_mca_wakeup(int cpu)
656 platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
657 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
662 * ia64_mca_wakeup_all
664 * Wakeup all the cpus which have rendez'ed previously.
670 ia64_mca_wakeup_all(void)
674 /* Clear the Rendez checkin flag for all cpus */
675 for(cpu = 0; cpu < NR_CPUS; cpu++) {
676 if (!cpu_online(cpu))
678 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
679 ia64_mca_wakeup(cpu);
685 * ia64_mca_rendez_interrupt_handler
687 * This is handler used to put slave processors into spinloop
688 * while the monarch processor does the mca handling and later
689 * wake each slave up once the monarch is done.
695 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *ptregs)
698 int cpu = smp_processor_id();
700 /* Mask all interrupts */
701 local_irq_save(flags);
703 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
704 /* Register with the SAL monarch that the slave has
707 ia64_sal_mc_rendez();
709 /* Wait for the wakeup IPI from the monarch
710 * This waiting is done by polling on the wakeup-interrupt
711 * vector bit in the processor's IRRs
713 ia64_mca_wakeup_ipi_wait();
715 /* Enable all interrupts */
716 local_irq_restore(flags);
721 * ia64_mca_wakeup_int_handler
723 * The interrupt handler for processing the inter-cpu interrupt to the
724 * slave cpu which was spinning in the rendez loop.
725 * Since this spinning is done by turning off the interrupts and
726 * polling on the wakeup-interrupt bit in the IRR, there is
727 * nothing useful to be done in the handler.
729 * Inputs : wakeup_irq (Wakeup-interrupt bit)
730 * arg (Interrupt handler specific argument)
731 * ptregs (Exception frame at the time of the interrupt)
736 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
742 * ia64_return_to_sal_check
744 * This is function called before going back from the OS_MCA handler
745 * to the OS_MCA dispatch code which finally takes the control back
747 * The main purpose of this routine is to setup the OS_MCA to SAL
748 * return state which can be used by the OS_MCA dispatch code
749 * just before going back to SAL.
756 ia64_return_to_sal_check(int recover)
759 /* Copy over some relevant stuff from the sal_to_os_mca_handoff
760 * so that it can be used at the time of os_mca_to_sal_handoff
762 ia64_os_to_sal_handoff_state.imots_sal_gp =
763 ia64_sal_to_os_handoff_state.imsto_sal_gp;
765 ia64_os_to_sal_handoff_state.imots_sal_check_ra =
766 ia64_sal_to_os_handoff_state.imsto_sal_check_ra;
769 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_CORRECTED;
771 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT;
773 /* Default = tell SAL to return to same context */
774 ia64_os_to_sal_handoff_state.imots_context = IA64_MCA_SAME_CONTEXT;
776 ia64_os_to_sal_handoff_state.imots_new_min_state =
777 (u64 *)ia64_sal_to_os_handoff_state.pal_min_state;
782 * ia64_mca_ucmc_handler
784 * This is uncorrectable machine check handler called from OS_MCA
785 * dispatch code which is in turn called from SAL_CHECK().
786 * This is the place where the core of OS MCA handling is done.
787 * Right now the logs are extracted and displayed in a well-defined
788 * format. This handler code is supposed to be run only on the
789 * monarch processor. Once the monarch is done with MCA handling
790 * further MCA logging is enabled by clearing logs.
791 * Monarch also has the duty of sending wakeup-IPIs to pull the
792 * slave processors out of rendezvous spinloop.
798 ia64_mca_ucmc_handler(void)
800 pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
801 &ia64_sal_to_os_handoff_state.proc_state_param;
802 int recover = psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc);
804 /* Get the MCA error record and log it */
805 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
808 * Wakeup all the processors which are spinning in the rendezvous
811 ia64_mca_wakeup_all();
814 ia64_return_to_sal_check(recover);
817 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
818 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
821 * ia64_mca_cmc_int_handler
823 * This is corrected machine check interrupt handler.
824 * Right now the logs are extracted and displayed in a well-defined
829 * client data arg ptr
830 * saved registers ptr
836 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
838 static unsigned long cmc_history[CMC_HISTORY_LENGTH];
840 static spinlock_t cmc_history_lock = SPIN_LOCK_UNLOCKED;
842 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
843 __FUNCTION__, cmc_irq, smp_processor_id());
845 /* SAL spec states this should run w/ interrupts enabled */
848 /* Get the CMC error record and log it */
849 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
851 spin_lock(&cmc_history_lock);
852 if (!cmc_polling_enabled) {
853 int i, count = 1; /* we know 1 happened now */
854 unsigned long now = jiffies;
856 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
857 if (now - cmc_history[i] <= HZ)
861 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
862 if (count >= CMC_HISTORY_LENGTH) {
864 cmc_polling_enabled = 1;
865 spin_unlock(&cmc_history_lock);
866 schedule_work(&cmc_disable_work);
869 * Corrected errors will still be corrected, but
870 * make sure there's a log somewhere that indicates
871 * something is generating more than we can handle.
873 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
875 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
877 /* lock already released, get out now */
880 cmc_history[index++] = now;
881 if (index == CMC_HISTORY_LENGTH)
885 spin_unlock(&cmc_history_lock);
890 * ia64_mca_cmc_int_caller
892 * Triggered by sw interrupt from CMC polling routine. Calls
893 * real interrupt handler and either triggers a sw interrupt
894 * on the next cpu or does cleanup at the end.
898 * client data arg ptr
899 * saved registers ptr
904 ia64_mca_cmc_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
906 static int start_count = -1;
909 cpuid = smp_processor_id();
911 /* If first cpu, update count */
912 if (start_count == -1)
913 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
915 ia64_mca_cmc_int_handler(cpe_irq, arg, ptregs);
917 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
919 if (cpuid < NR_CPUS) {
920 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
922 /* If no log record, switch out of polling mode */
923 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
925 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
926 schedule_work(&cmc_enable_work);
927 cmc_polling_enabled = 0;
931 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
943 * Poll for Corrected Machine Checks (CMCs)
945 * Inputs : dummy(unused)
950 ia64_mca_cmc_poll (unsigned long dummy)
952 /* Trigger a CMC interrupt cascade */
953 platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
957 * ia64_mca_cpe_int_caller
959 * Triggered by sw interrupt from CPE polling routine. Calls
960 * real interrupt handler and either triggers a sw interrupt
961 * on the next cpu or does cleanup at the end.
965 * client data arg ptr
966 * saved registers ptr
971 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
973 static int start_count = -1;
974 static int poll_time = MAX_CPE_POLL_INTERVAL;
977 cpuid = smp_processor_id();
979 /* If first cpu, update count */
980 if (start_count == -1)
981 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
983 ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
985 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
987 if (cpuid < NR_CPUS) {
988 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
991 * If a log was recorded, increase our polling frequency,
992 * otherwise, backoff.
994 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
995 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
997 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1000 mod_timer(&cpe_poll_timer, jiffies + poll_time);
1009 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1010 * on first cpu, from there it will trickle through all the cpus.
1012 * Inputs : dummy(unused)
1017 ia64_mca_cpe_poll (unsigned long dummy)
1019 /* Trigger a CPE interrupt cascade */
1020 platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1024 * C portion of the OS INIT handler
1026 * Called from ia64_monarch_init_handler
1028 * Inputs: pointer to pt_regs where processor info was saved.
1031 * 0 if SAL must warm boot the System
1032 * 1 if SAL must return to interrupted context using PAL_MC_RESUME
1036 ia64_init_handler (struct pt_regs *pt, struct switch_stack *sw)
1038 pal_min_state_area_t *ms;
1040 oops_in_progress = 1; /* avoid deadlock in printk, but it makes recovery dodgy */
1042 printk(KERN_INFO "Entered OS INIT handler. PSP=%lx\n",
1043 ia64_sal_to_os_handoff_state.proc_state_param);
1046 * Address of minstate area provided by PAL is physical,
1047 * uncacheable (bit 63 set). Convert to Linux virtual
1048 * address in region 6.
1050 ms = (pal_min_state_area_t *)(ia64_sal_to_os_handoff_state.pal_min_state | (6ul<<61));
1052 init_handler_platform(ms, pt, sw); /* call platform specific routines */
1056 ia64_mca_disable_cpe_polling(char *str)
1058 cpe_poll_enabled = 0;
1062 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1064 static struct irqaction cmci_irqaction = {
1065 .handler = ia64_mca_cmc_int_handler,
1066 .flags = SA_INTERRUPT,
1070 static struct irqaction cmcp_irqaction = {
1071 .handler = ia64_mca_cmc_int_caller,
1072 .flags = SA_INTERRUPT,
1076 static struct irqaction mca_rdzv_irqaction = {
1077 .handler = ia64_mca_rendez_int_handler,
1078 .flags = SA_INTERRUPT,
1082 static struct irqaction mca_wkup_irqaction = {
1083 .handler = ia64_mca_wakeup_int_handler,
1084 .flags = SA_INTERRUPT,
1089 static struct irqaction mca_cpe_irqaction = {
1090 .handler = ia64_mca_cpe_int_handler,
1091 .flags = SA_INTERRUPT,
1095 static struct irqaction mca_cpep_irqaction = {
1096 .handler = ia64_mca_cpe_int_caller,
1097 .flags = SA_INTERRUPT,
1100 #endif /* CONFIG_ACPI */
1105 * Do all the system level mca specific initialization.
1107 * 1. Register spinloop and wakeup request interrupt vectors
1109 * 2. Register OS_MCA handler entry point
1111 * 3. Register OS_INIT handler entry point
1113 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1115 * Note that this initialization is done very early before some kernel
1116 * services are available.
1125 ia64_fptr_t *mon_init_ptr = (ia64_fptr_t *)ia64_monarch_init_handler;
1126 ia64_fptr_t *slave_init_ptr = (ia64_fptr_t *)ia64_slave_init_handler;
1127 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1130 struct ia64_sal_retval isrv;
1131 u64 timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1133 IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1135 /* Clear the Rendez checkin flag for all cpus */
1136 for(i = 0 ; i < NR_CPUS; i++)
1137 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1140 * Register the rendezvous spinloop and wakeup mechanism with SAL
1143 /* Register the rendezvous interrupt vector with SAL */
1145 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1146 SAL_MC_PARAM_MECHANISM_INT,
1147 IA64_MCA_RENDEZ_VECTOR,
1149 SAL_MC_PARAM_RZ_ALWAYS);
1154 printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1155 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1159 printk(KERN_ERR "Failed to register rendezvous interrupt "
1160 "with SAL (status %ld)\n", rc);
1164 /* Register the wakeup interrupt vector with SAL */
1165 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1166 SAL_MC_PARAM_MECHANISM_INT,
1167 IA64_MCA_WAKEUP_VECTOR,
1171 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1172 "(status %ld)\n", rc);
1176 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1178 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp);
1180 * XXX - disable SAL checksum by setting size to 0; should be
1181 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1183 ia64_mc_info.imi_mca_handler_size = 0;
1185 /* Register the os mca handler with SAL */
1186 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1187 ia64_mc_info.imi_mca_handler,
1188 ia64_tpa(mca_hldlr_ptr->gp),
1189 ia64_mc_info.imi_mca_handler_size,
1192 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1193 "(status %ld)\n", rc);
1197 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1198 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1201 * XXX - disable SAL checksum by setting size to 0, should be
1202 * size of the actual init handler in mca_asm.S.
1204 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(mon_init_ptr->fp);
1205 ia64_mc_info.imi_monarch_init_handler_size = 0;
1206 ia64_mc_info.imi_slave_init_handler = ia64_tpa(slave_init_ptr->fp);
1207 ia64_mc_info.imi_slave_init_handler_size = 0;
1209 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1210 ia64_mc_info.imi_monarch_init_handler);
1212 /* Register the os init handler with SAL */
1213 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1214 ia64_mc_info.imi_monarch_init_handler,
1215 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1216 ia64_mc_info.imi_monarch_init_handler_size,
1217 ia64_mc_info.imi_slave_init_handler,
1218 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1219 ia64_mc_info.imi_slave_init_handler_size)))
1221 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1222 "(status %ld)\n", rc);
1226 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1229 * Configure the CMCI/P vector and handler. Interrupts for CMC are
1230 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1232 register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1233 register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1234 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP & enable */
1236 /* Setup the MCA rendezvous interrupt vector */
1237 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1239 /* Setup the MCA wakeup interrupt vector */
1240 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1243 /* Setup the CPE interrupt vector */
1247 int cpev = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1250 for (irq = 0; irq < NR_IRQS; ++irq)
1251 if (irq_to_vector(irq) == cpev) {
1252 desc = irq_descp(irq);
1253 desc->status |= IRQ_PER_CPU;
1254 setup_irq(irq, &mca_cpe_irqaction);
1256 ia64_mca_register_cpev(cpev);
1261 /* Initialize the areas set aside by the OS to buffer the
1262 * platform/processor error states for MCA/INIT/CMC
1265 ia64_log_init(SAL_INFO_TYPE_MCA);
1266 ia64_log_init(SAL_INFO_TYPE_INIT);
1267 ia64_log_init(SAL_INFO_TYPE_CMC);
1268 ia64_log_init(SAL_INFO_TYPE_CPE);
1270 printk(KERN_INFO "MCA related initialization done\n");
1274 * ia64_mca_late_init
1276 * Opportunity to setup things that require initialization later
1277 * than ia64_mca_init. Setup a timer to poll for CPEs if the
1278 * platform doesn't support an interrupt driven mechanism.
1284 ia64_mca_late_init(void)
1286 init_timer(&cmc_poll_timer);
1287 cmc_poll_timer.function = ia64_mca_cmc_poll;
1289 /* Reset to the correct state */
1290 cmc_polling_enabled = 0;
1292 init_timer(&cpe_poll_timer);
1293 cpe_poll_timer.function = ia64_mca_cpe_poll;
1296 /* If platform doesn't support CPEI, get the timer going. */
1297 if (acpi_request_vector(ACPI_INTERRUPT_CPEI) < 0 && cpe_poll_enabled) {
1298 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1299 ia64_mca_cpe_poll(0UL);
1306 device_initcall(ia64_mca_late_init);