2 * Kernel support for the ptrace() and syscall tracing interfaces.
4 * Copyright (C) 1999-2005 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Copyright (C) 2006 Intel Co
7 * 2006-08-12 - IA64 Native Utrace implementation support added by
8 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
10 * Derived from the x86 and Alpha versions.
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
16 #include <linux/errno.h>
17 #include <linux/ptrace.h>
18 #include <linux/tracehook.h>
19 #include <linux/smp_lock.h>
20 #include <linux/user.h>
21 #include <linux/security.h>
22 #include <linux/audit.h>
23 #include <linux/signal.h>
24 #include <linux/module.h>
26 #include <asm/tracehook.h>
27 #include <asm/pgtable.h>
28 #include <asm/processor.h>
29 #include <asm/ptrace_offsets.h>
31 #include <asm/system.h>
32 #include <asm/uaccess.h>
34 #include <asm/unwind.h>
36 #include <asm/perfmon.h>
42 * Bits in the PSR that we allow ptrace() to change:
43 * be, up, ac, mfl, mfh (the user mask; five bits total)
44 * db (debug breakpoint fault; one bit)
45 * id (instruction debug fault disable; one bit)
46 * dd (data debug fault disable; one bit)
47 * ri (restart instruction; two bits)
48 * is (instruction set; one bit)
50 #define IPSR_MASK (IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS \
51 | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
53 #define MASK(nbits) ((1UL << (nbits)) - 1) /* mask with NBITS bits set */
54 #define PFM_MASK MASK(38)
56 #define PTRACE_DEBUG 0
59 # define dprintk(format...) printk(format)
62 # define dprintk(format...)
65 /* Return TRUE if PT was created due to kernel-entry via a system-call. */
68 in_syscall (struct pt_regs *pt)
70 return (long) pt->cr_ifs >= 0;
74 * Collect the NaT bits for r1-r31 from scratch_unat and return a NaT
75 * bitset where bit i is set iff the NaT bit of register i is set.
78 ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat)
80 # define GET_BITS(first, last, unat) \
82 unsigned long bit = ia64_unat_pos(&pt->r##first); \
83 unsigned long nbits = (last - first + 1); \
84 unsigned long mask = MASK(nbits) << first; \
87 dist = 64 + bit - first; \
90 ia64_rotr(unat, dist) & mask; \
95 * Registers that are stored consecutively in struct pt_regs
96 * can be handled in parallel. If the register order in
97 * struct_pt_regs changes, this code MUST be updated.
99 val = GET_BITS( 1, 1, scratch_unat);
100 val |= GET_BITS( 2, 3, scratch_unat);
101 val |= GET_BITS(12, 13, scratch_unat);
102 val |= GET_BITS(14, 14, scratch_unat);
103 val |= GET_BITS(15, 15, scratch_unat);
104 val |= GET_BITS( 8, 11, scratch_unat);
105 val |= GET_BITS(16, 31, scratch_unat);
112 * Set the NaT bits for the scratch registers according to NAT and
113 * return the resulting unat (assuming the scratch registers are
117 ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat)
119 # define PUT_BITS(first, last, nat) \
121 unsigned long bit = ia64_unat_pos(&pt->r##first); \
122 unsigned long nbits = (last - first + 1); \
123 unsigned long mask = MASK(nbits) << first; \
126 dist = 64 + bit - first; \
128 dist = bit - first; \
129 ia64_rotl(nat & mask, dist); \
131 unsigned long scratch_unat;
134 * Registers that are stored consecutively in struct pt_regs
135 * can be handled in parallel. If the register order in
136 * struct_pt_regs changes, this code MUST be updated.
138 scratch_unat = PUT_BITS( 1, 1, nat);
139 scratch_unat |= PUT_BITS( 2, 3, nat);
140 scratch_unat |= PUT_BITS(12, 13, nat);
141 scratch_unat |= PUT_BITS(14, 14, nat);
142 scratch_unat |= PUT_BITS(15, 15, nat);
143 scratch_unat |= PUT_BITS( 8, 11, nat);
144 scratch_unat |= PUT_BITS(16, 31, nat);
151 #define IA64_MLX_TEMPLATE 0x2
152 #define IA64_MOVL_OPCODE 6
155 ia64_increment_ip (struct pt_regs *regs)
157 unsigned long w0, ri = ia64_psr(regs)->ri + 1;
162 } else if (ri == 2) {
163 get_user(w0, (char __user *) regs->cr_iip + 0);
164 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
166 * rfi'ing to slot 2 of an MLX bundle causes
167 * an illegal operation fault. We don't want
174 ia64_psr(regs)->ri = ri;
178 ia64_decrement_ip (struct pt_regs *regs)
180 unsigned long w0, ri = ia64_psr(regs)->ri - 1;
182 if (ia64_psr(regs)->ri == 0) {
185 get_user(w0, (char __user *) regs->cr_iip + 0);
186 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
188 * rfi'ing to slot 2 of an MLX bundle causes
189 * an illegal operation fault. We don't want
195 ia64_psr(regs)->ri = ri;
199 * This routine is used to read an rnat bits that are stored on the
200 * kernel backing store. Since, in general, the alignment of the user
201 * and kernel are different, this is not completely trivial. In
202 * essence, we need to construct the user RNAT based on up to two
203 * kernel RNAT values and/or the RNAT value saved in the child's
208 * +--------+ <-- lowest address
215 * | slot01 | > child_regs->ar_rnat
217 * | slot02 | / kernel rbs
218 * +--------+ +--------+
219 * <- child_regs->ar_bspstore | slot61 | <-- krbs
220 * +- - - - + +--------+
222 * +- - - - + +--------+
224 * +- - - - + +--------+
226 * +- - - - + +--------+
231 * | slot01 | > child_stack->ar_rnat
235 * <--- child_stack->ar_bspstore
237 * The way to think of this code is as follows: bit 0 in the user rnat
238 * corresponds to some bit N (0 <= N <= 62) in one of the kernel rnat
239 * value. The kernel rnat value holding this bit is stored in
240 * variable rnat0. rnat1 is loaded with the kernel rnat value that
241 * form the upper bits of the user rnat value.
245 * o when reading the rnat "below" the first rnat slot on the kernel
246 * backing store, rnat0/rnat1 are set to 0 and the low order bits are
247 * merged in from pt->ar_rnat.
249 * o when reading the rnat "above" the last rnat slot on the kernel
250 * backing store, rnat0/rnat1 gets its value from sw->ar_rnat.
253 get_rnat (struct task_struct *task, struct switch_stack *sw,
254 unsigned long *krbs, unsigned long *urnat_addr,
255 unsigned long *urbs_end)
257 unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr;
258 unsigned long umask = 0, mask, m;
259 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
260 long num_regs, nbits;
263 pt = task_pt_regs(task);
264 kbsp = (unsigned long *) sw->ar_bspstore;
265 ubspstore = (unsigned long *) pt->ar_bspstore;
267 if (urbs_end < urnat_addr)
268 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_end);
273 * First, figure out which bit number slot 0 in user-land maps
274 * to in the kernel rnat. Do this by figuring out how many
275 * register slots we're beyond the user's backingstore and
276 * then computing the equivalent address in kernel space.
278 num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
279 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
280 shift = ia64_rse_slot_num(slot0_kaddr);
281 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
282 rnat0_kaddr = rnat1_kaddr - 64;
284 if (ubspstore + 63 > urnat_addr) {
285 /* some bits need to be merged in from pt->ar_rnat */
286 umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
287 urnat = (pt->ar_rnat & umask);
294 if (rnat0_kaddr >= kbsp)
296 else if (rnat0_kaddr > krbs)
297 rnat0 = *rnat0_kaddr;
298 urnat |= (rnat0 & m) >> shift;
300 m = mask >> (63 - shift);
301 if (rnat1_kaddr >= kbsp)
303 else if (rnat1_kaddr > krbs)
304 rnat1 = *rnat1_kaddr;
305 urnat |= (rnat1 & m) << (63 - shift);
310 * The reverse of get_rnat.
313 put_rnat (struct task_struct *task, struct switch_stack *sw,
314 unsigned long *krbs, unsigned long *urnat_addr, unsigned long urnat,
315 unsigned long *urbs_end)
317 unsigned long rnat0 = 0, rnat1 = 0, *slot0_kaddr, umask = 0, mask, m;
318 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
319 long num_regs, nbits;
321 unsigned long cfm, *urbs_kargs;
323 pt = task_pt_regs(task);
324 kbsp = (unsigned long *) sw->ar_bspstore;
325 ubspstore = (unsigned long *) pt->ar_bspstore;
327 urbs_kargs = urbs_end;
328 if (in_syscall(pt)) {
330 * If entered via syscall, don't allow user to set rnat bits
334 urbs_kargs = ia64_rse_skip_regs(urbs_end, -(cfm & 0x7f));
337 if (urbs_kargs >= urnat_addr)
340 if ((urnat_addr - 63) >= urbs_kargs)
342 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_kargs);
347 * First, figure out which bit number slot 0 in user-land maps
348 * to in the kernel rnat. Do this by figuring out how many
349 * register slots we're beyond the user's backingstore and
350 * then computing the equivalent address in kernel space.
352 num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
353 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
354 shift = ia64_rse_slot_num(slot0_kaddr);
355 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
356 rnat0_kaddr = rnat1_kaddr - 64;
358 if (ubspstore + 63 > urnat_addr) {
359 /* some bits need to be place in pt->ar_rnat: */
360 umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
361 pt->ar_rnat = (pt->ar_rnat & ~umask) | (urnat & umask);
367 * Note: Section 11.1 of the EAS guarantees that bit 63 of an
368 * rnat slot is ignored. so we don't have to clear it here.
370 rnat0 = (urnat << shift);
372 if (rnat0_kaddr >= kbsp)
373 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat0 & m);
374 else if (rnat0_kaddr > krbs)
375 *rnat0_kaddr = ((*rnat0_kaddr & ~m) | (rnat0 & m));
377 rnat1 = (urnat >> (63 - shift));
378 m = mask >> (63 - shift);
379 if (rnat1_kaddr >= kbsp)
380 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat1 & m);
381 else if (rnat1_kaddr > krbs)
382 *rnat1_kaddr = ((*rnat1_kaddr & ~m) | (rnat1 & m));
386 on_kernel_rbs (unsigned long addr, unsigned long bspstore,
387 unsigned long urbs_end)
389 unsigned long *rnat_addr = ia64_rse_rnat_addr((unsigned long *)
391 return (addr >= bspstore && addr <= (unsigned long) rnat_addr);
395 * Read a word from the user-level backing store of task CHILD. ADDR
396 * is the user-level address to read the word from, VAL a pointer to
397 * the return value, and USER_BSP gives the end of the user-level
398 * backing store (i.e., it's the address that would be in ar.bsp after
399 * the user executed a "cover" instruction).
401 * This routine takes care of accessing the kernel register backing
402 * store for those registers that got spilled there. It also takes
403 * care of calculating the appropriate RNaT collection words.
406 ia64_peek (struct task_struct *child, struct switch_stack *child_stack,
407 unsigned long user_rbs_end, unsigned long addr, long *val)
409 unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end, *rnat_addr;
410 struct pt_regs *child_regs;
414 urbs_end = (long *) user_rbs_end;
415 laddr = (unsigned long *) addr;
416 child_regs = task_pt_regs(child);
417 bspstore = (unsigned long *) child_regs->ar_bspstore;
418 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
419 if (on_kernel_rbs(addr, (unsigned long) bspstore,
420 (unsigned long) urbs_end))
423 * Attempt to read the RBS in an area that's actually
424 * on the kernel RBS => read the corresponding bits in
427 rnat_addr = ia64_rse_rnat_addr(laddr);
428 ret = get_rnat(child, child_stack, krbs, rnat_addr, urbs_end);
430 if (laddr == rnat_addr) {
431 /* return NaT collection word itself */
436 if (((1UL << ia64_rse_slot_num(laddr)) & ret) != 0) {
438 * It is implementation dependent whether the
439 * data portion of a NaT value gets saved on a
440 * st8.spill or RSE spill (e.g., see EAS 2.6,
441 * 4.4.4.6 Register Spill and Fill). To get
442 * consistent behavior across all possible
443 * IA-64 implementations, we return zero in
450 if (laddr < urbs_end) {
452 * The desired word is on the kernel RBS and
455 regnum = ia64_rse_num_regs(bspstore, laddr);
456 *val = *ia64_rse_skip_regs(krbs, regnum);
460 copied = access_process_vm(child, addr, &ret, sizeof(ret), 0);
461 if (copied != sizeof(ret))
468 ia64_poke (struct task_struct *child, struct switch_stack *child_stack,
469 unsigned long user_rbs_end, unsigned long addr, long val)
471 unsigned long *bspstore, *krbs, regnum, *laddr;
472 unsigned long *urbs_end = (long *) user_rbs_end;
473 struct pt_regs *child_regs;
475 laddr = (unsigned long *) addr;
476 child_regs = task_pt_regs(child);
477 bspstore = (unsigned long *) child_regs->ar_bspstore;
478 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
479 if (on_kernel_rbs(addr, (unsigned long) bspstore,
480 (unsigned long) urbs_end))
483 * Attempt to write the RBS in an area that's actually
484 * on the kernel RBS => write the corresponding bits
487 if (ia64_rse_is_rnat_slot(laddr))
488 put_rnat(child, child_stack, krbs, laddr, val,
491 if (laddr < urbs_end) {
492 regnum = ia64_rse_num_regs(bspstore, laddr);
493 *ia64_rse_skip_regs(krbs, regnum) = val;
496 } else if (access_process_vm(child, addr, &val, sizeof(val), 1)
503 * Calculate the address of the end of the user-level register backing
504 * store. This is the address that would have been stored in ar.bsp
505 * if the user had executed a "cover" instruction right before
506 * entering the kernel. If CFMP is not NULL, it is used to return the
507 * "current frame mask" that was active at the time the kernel was
511 ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt,
514 unsigned long *krbs, *bspstore, cfm = pt->cr_ifs;
517 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
518 bspstore = (unsigned long *) pt->ar_bspstore;
519 ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
522 ndirty += (cfm & 0x7f);
524 cfm &= ~(1UL << 63); /* clear valid bit */
528 return (unsigned long) ia64_rse_skip_regs(bspstore, ndirty);
532 * Synchronize (i.e, write) the RSE backing store living in kernel
533 * space to the VM of the CHILD task. SW and PT are the pointers to
534 * the switch_stack and pt_regs structures, respectively.
535 * USER_RBS_END is the user-level address at which the backing store
539 ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
540 unsigned long user_rbs_start, unsigned long user_rbs_end)
542 unsigned long addr, val;
545 /* now copy word for word from kernel rbs to user rbs: */
546 for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
547 ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
550 if (access_process_vm(child, addr, &val, sizeof(val), 1)
558 * Write f32-f127 back to task->thread.fph if it has been modified.
561 ia64_flush_fph (struct task_struct *task)
563 struct ia64_psr *psr = ia64_psr(task_pt_regs(task));
566 * Prevent migrating this task while
567 * we're fiddling with the FPU state
570 if (ia64_is_local_fpu_owner(task) && psr->mfh) {
572 task->thread.flags |= IA64_THREAD_FPH_VALID;
573 ia64_save_fpu(&task->thread.fph[0]);
579 * Sync the fph state of the task so that it can be manipulated
580 * through thread.fph. If necessary, f32-f127 are written back to
581 * thread.fph or, if the fph state hasn't been used before, thread.fph
582 * is cleared to zeroes. Also, access to f32-f127 is disabled to
583 * ensure that the task picks up the state from thread.fph when it
587 ia64_sync_fph (struct task_struct *task)
589 struct ia64_psr *psr = ia64_psr(task_pt_regs(task));
591 ia64_flush_fph(task);
592 if (!(task->thread.flags & IA64_THREAD_FPH_VALID)) {
593 task->thread.flags |= IA64_THREAD_FPH_VALID;
594 memset(&task->thread.fph, 0, sizeof(task->thread.fph));
602 access_fr (struct unw_frame_info *info, int regnum, int hi,
603 unsigned long *data, int write_access)
605 struct ia64_fpreg fpval;
608 ret = unw_get_fr(info, regnum, &fpval);
613 fpval.u.bits[hi] = *data;
614 ret = unw_set_fr(info, regnum, fpval);
616 *data = fpval.u.bits[hi];
619 #endif /* access_fr() */
622 * Change the machine-state of CHILD such that it will return via the normal
623 * kernel exit-path, rather than the syscall-exit path.
626 convert_to_non_syscall (struct task_struct *child, struct pt_regs *pt,
629 struct unw_frame_info info, prev_info;
630 unsigned long ip, sp, pr;
632 unw_init_from_blocked_task(&info, child);
635 if (unw_unwind(&info) < 0)
638 unw_get_sp(&info, &sp);
639 if ((long)((unsigned long)child + IA64_STK_OFFSET - sp)
640 < IA64_PT_REGS_SIZE) {
641 dprintk("ptrace.%s: ran off the top of the kernel "
642 "stack\n", __FUNCTION__);
645 if (unw_get_pr (&prev_info, &pr) < 0) {
646 unw_get_rp(&prev_info, &ip);
647 dprintk("ptrace.%s: failed to read "
648 "predicate register (ip=0x%lx)\n",
652 if (unw_is_intr_frame(&info)
653 && (pr & (1UL << PRED_USER_STACK)))
658 * Note: at the time of this call, the target task is blocked
659 * in notify_resume_user() and by clearling PRED_LEAVE_SYSCALL
660 * (aka, "pLvSys") we redirect execution from
661 * .work_pending_syscall_end to .work_processed_kernel.
663 unw_get_pr(&prev_info, &pr);
664 pr &= ~((1UL << PRED_SYSCALL) | (1UL << PRED_LEAVE_SYSCALL));
665 pr |= (1UL << PRED_NON_SYSCALL);
666 unw_set_pr(&prev_info, pr);
668 pt->cr_ifs = (1UL << 63) | cfm;
670 * Clear the memory that is NOT written on syscall-entry to
671 * ensure we do not leak kernel-state to user when execution
677 memset(&pt->r16, 0, 16*8); /* clear r16-r31 */
678 memset(&pt->f6, 0, 6*16); /* clear f6-f11 */
686 access_nat_bits (struct task_struct *child, struct pt_regs *pt,
687 struct unw_frame_info *info,
688 unsigned long *data, int write_access)
690 unsigned long regnum, nat_bits, scratch_unat, dummy = 0;
695 scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
696 if (unw_set_ar(info, UNW_AR_UNAT, scratch_unat) < 0) {
697 dprintk("ptrace: failed to set ar.unat\n");
700 for (regnum = 4; regnum <= 7; ++regnum) {
701 unw_get_gr(info, regnum, &dummy, &nat);
702 unw_set_gr(info, regnum, dummy,
703 (nat_bits >> regnum) & 1);
706 if (unw_get_ar(info, UNW_AR_UNAT, &scratch_unat) < 0) {
707 dprintk("ptrace: failed to read ar.unat\n");
710 nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
711 for (regnum = 4; regnum <= 7; ++regnum) {
712 unw_get_gr(info, regnum, &dummy, &nat);
713 nat_bits |= (nat != 0) << regnum;
721 /* "asmlinkage" so the input arguments are preserved... */
724 syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
725 long arg4, long arg5, long arg6, long arg7,
728 if (test_thread_flag(TIF_SYSCALL_TRACE))
729 tracehook_report_syscall(®s, 0);
731 if (unlikely(current->audit_context)) {
735 if (IS_IA32_PROCESS(®s)) {
737 arch = AUDIT_ARCH_I386;
740 arch = AUDIT_ARCH_IA64;
743 audit_syscall_entry(arch, syscall, arg0, arg1, arg2, arg3);
748 /* "asmlinkage" so the input arguments are preserved... */
751 syscall_trace_leave (long arg0, long arg1, long arg2, long arg3,
752 long arg4, long arg5, long arg6, long arg7,
755 if (unlikely(current->audit_context)) {
756 int success = AUDITSC_RESULT(regs.r10);
757 long result = regs.r8;
759 if (success != AUDITSC_SUCCESS)
761 audit_syscall_exit(success, result);
764 if (test_thread_flag(TIF_SYSCALL_TRACE))
765 tracehook_report_syscall(®s, 1);
767 if (test_thread_flag(TIF_SINGLESTEP)) {
768 force_sig(SIGTRAP, current); /* XXX */
769 tracehook_report_syscall_step(®s);
776 /* Utrace implementation starts here */
778 typedef struct utrace_get {
783 typedef struct utrace_set {
785 const void __user *ubuf;
788 typedef struct utrace_getset {
789 struct task_struct *target;
790 const struct utrace_regset *regset;
801 access_elf_gpreg(struct task_struct *target, struct unw_frame_info *info,
802 unsigned long addr, unsigned long *data, int write_access)
805 unsigned long *ptr = NULL;
809 pt = task_pt_regs(target);
811 case ELF_GR_OFFSET(1):
814 case ELF_GR_OFFSET(2):
815 case ELF_GR_OFFSET(3):
816 ptr = (void *)&pt->r2 + (addr - ELF_GR_OFFSET(2));
818 case ELF_GR_OFFSET(4) ... ELF_GR_OFFSET(7):
820 /* read NaT bit first: */
823 ret = unw_get_gr(info, addr/8, &dummy, &nat);
827 return unw_access_gr(info, addr/8, data, &nat, write_access);
828 case ELF_GR_OFFSET(8) ... ELF_GR_OFFSET(11):
829 ptr = (void *)&pt->r8 + addr - ELF_GR_OFFSET(8);
831 case ELF_GR_OFFSET(12):
832 case ELF_GR_OFFSET(13):
833 ptr = (void *)&pt->r12 + addr - ELF_GR_OFFSET(12);
835 case ELF_GR_OFFSET(14):
838 case ELF_GR_OFFSET(15):
849 access_elf_breg(struct task_struct *target, struct unw_frame_info *info,
850 unsigned long addr, unsigned long *data, int write_access)
853 unsigned long *ptr = NULL;
855 pt = task_pt_regs(target);
857 case ELF_BR_OFFSET(0):
860 case ELF_BR_OFFSET(1) ... ELF_BR_OFFSET(5):
861 return unw_access_br(info, (addr - ELF_BR_OFFSET(0))/8,
863 case ELF_BR_OFFSET(6):
866 case ELF_BR_OFFSET(7):
877 access_elf_areg(struct task_struct *target, struct unw_frame_info *info,
878 unsigned long addr, unsigned long *data, int write_access)
881 unsigned long cfm, urbs_end, rnat_addr;
882 unsigned long *ptr = NULL;
884 pt = task_pt_regs(target);
885 if (addr >= ELF_AR_RSC_OFFSET && addr <= ELF_AR_SSD_OFFSET) {
887 case ELF_AR_RSC_OFFSET:
890 pt->ar_rsc = *data | (3 << 2);
894 case ELF_AR_BSP_OFFSET:
896 * By convention, we use PT_AR_BSP to refer to
897 * the end of the user-level backing store.
898 * Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof)
899 * to get the real value of ar.bsp at the time
900 * the kernel was entered.
902 * Furthermore, when changing the contents of
903 * PT_AR_BSP (or PT_CFM) we MUST copy any
904 * users-level stacked registers that are
905 * stored on the kernel stack back to
906 * user-space because otherwise, we might end
907 * up clobbering kernel stacked registers.
908 * Also, if this happens while the task is
909 * blocked in a system call, which convert the
910 * state such that the non-system-call exit
911 * path is used. This ensures that the proper
912 * state will be picked up when resuming
913 * execution. However, it *also* means that
914 * once we write PT_AR_BSP/PT_CFM, it won't be
915 * possible to modify the syscall arguments of
916 * the pending system call any longer. This
917 * shouldn't be an issue because modifying
918 * PT_AR_BSP/PT_CFM generally implies that
919 * we're either abandoning the pending system
920 * call or that we defer it's re-execution
921 * (e.g., due to GDB doing an inferior
924 urbs_end = ia64_get_user_rbs_end(target, pt, &cfm);
926 if (*data != urbs_end) {
927 if (ia64_sync_user_rbs(target, info->sw,
932 convert_to_non_syscall(target,
936 * Simulate user-level write
940 pt->ar_bspstore = *data;
945 case ELF_AR_BSPSTORE_OFFSET: // ar_bsp_store
946 ptr = &pt->ar_bspstore;
948 case ELF_AR_RNAT_OFFSET: // ar_rnat
949 urbs_end = ia64_get_user_rbs_end(target, pt, NULL);
950 rnat_addr = (long) ia64_rse_rnat_addr((long *)
953 return ia64_poke(target, info->sw, urbs_end,
956 return ia64_peek(target, info->sw, urbs_end,
958 case ELF_AR_CCV_OFFSET: // ar_ccv
961 case ELF_AR_UNAT_OFFSET: // ar_unat
964 case ELF_AR_FPSR_OFFSET: // ar_fpsr
967 case ELF_AR_PFS_OFFSET: // ar_pfs
970 case ELF_AR_LC_OFFSET: // ar_lc
971 return unw_access_ar(info, UNW_AR_LC, data,
973 case ELF_AR_EC_OFFSET: // ar_ec
974 return unw_access_ar(info, UNW_AR_EC, data,
976 case ELF_AR_CSD_OFFSET: // ar_csd
979 case ELF_AR_SSD_OFFSET: // ar_ssd
982 } else if (addr >= ELF_CR_IIP_OFFSET && addr <= ELF_CR_IPSR_OFFSET) {
984 case ELF_CR_IIP_OFFSET:
988 urbs_end = ia64_get_user_rbs_end(target, pt, &cfm);
990 if (((cfm ^ *data) & PFM_MASK) != 0) {
991 if (ia64_sync_user_rbs(target, info->sw,
996 convert_to_non_syscall(target,
999 pt->cr_ifs = ((pt->cr_ifs & ~PFM_MASK)
1000 | (*data & PFM_MASK));
1005 case ELF_CR_IPSR_OFFSET:
1007 pt->cr_ipsr = ((*data & IPSR_MASK)
1008 | (pt->cr_ipsr & ~IPSR_MASK));
1010 *data = (pt->cr_ipsr & IPSR_MASK);
1013 } else if (addr == ELF_NAT_OFFSET)
1014 return access_nat_bits(target, pt, info,
1015 data, write_access);
1016 else if (addr == ELF_PR_OFFSET)
1030 access_elf_reg(struct task_struct *target, struct unw_frame_info *info,
1031 unsigned long addr, unsigned long *data, int write_access)
1033 if (addr >= ELF_GR_OFFSET(1) && addr <= ELF_GR_OFFSET(15))
1034 return access_elf_gpreg(target, info, addr, data, write_access);
1035 else if (addr >= ELF_BR_OFFSET(0) && addr <= ELF_BR_OFFSET(7))
1036 return access_elf_breg(target, info, addr, data, write_access);
1038 return access_elf_areg(target, info, addr, data, write_access);
1041 void do_gpregs_get(struct unw_frame_info *info, void *arg)
1044 utrace_getset_t *dst = arg;
1046 unsigned int i, index, min_copy;
1048 if (unw_unwind_to_user(info) < 0)
1054 * NaT bits (for r0-r31; bit N == 1 iff rN is a NaT)
1055 * predicate registers (p0-p63)
1058 * ar.rsc ar.bsp ar.bspstore ar.rnat
1059 * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec
1064 if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(1)) {
1065 dst->ret = utrace_regset_copyout_zero(&dst->pos, &dst->count,
1068 0, ELF_GR_OFFSET(1));
1069 if (dst->ret || dst->count == 0)
1074 if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(16)) {
1075 index = (dst->pos - ELF_GR_OFFSET(1)) / sizeof(elf_greg_t);
1076 min_copy = ELF_GR_OFFSET(16) > (dst->pos + dst->count) ?
1077 (dst->pos + dst->count) : ELF_GR_OFFSET(16);
1078 for (i = dst->pos; i < min_copy; i += sizeof(elf_greg_t), index++)
1079 if (access_elf_reg(dst->target, info, i,
1080 &tmp[index], 0) < 0) {
1084 dst->ret = utrace_regset_copyout(&dst->pos, &dst->count,
1085 &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
1086 ELF_GR_OFFSET(1), ELF_GR_OFFSET(16));
1087 if (dst->ret || dst->count == 0)
1092 if (dst->count > 0 && dst->pos < ELF_NAT_OFFSET) {
1093 pt = task_pt_regs(dst->target);
1094 dst->ret = utrace_regset_copyout(&dst->pos, &dst->count,
1095 &dst->u.get.kbuf, &dst->u.get.ubuf, &pt->r16,
1096 ELF_GR_OFFSET(16), ELF_NAT_OFFSET);
1097 if (dst->ret || dst->count == 0)
1101 /* nat, pr, b0 - b7 */
1102 if (dst->count > 0 && dst->pos < ELF_CR_IIP_OFFSET) {
1103 index = (dst->pos - ELF_NAT_OFFSET) / sizeof(elf_greg_t);
1104 min_copy = ELF_CR_IIP_OFFSET > (dst->pos + dst->count) ?
1105 (dst->pos + dst->count) : ELF_CR_IIP_OFFSET;
1106 for (i = dst->pos; i < min_copy; i += sizeof(elf_greg_t), index++)
1107 if (access_elf_reg(dst->target, info, i,
1108 &tmp[index], 0) < 0) {
1112 dst->ret = utrace_regset_copyout(&dst->pos, &dst->count,
1113 &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
1114 ELF_NAT_OFFSET, ELF_CR_IIP_OFFSET);
1115 if (dst->ret || dst->count == 0)
1119 /* ip cfm psr ar.rsc ar.bsp ar.bspstore ar.rnat
1120 * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
1122 if (dst->count > 0 && dst->pos < (ELF_AR_END_OFFSET)) {
1123 index = (dst->pos - ELF_CR_IIP_OFFSET) / sizeof(elf_greg_t);
1124 min_copy = ELF_AR_END_OFFSET > (dst->pos + dst->count) ?
1125 (dst->pos + dst->count) : ELF_AR_END_OFFSET;
1126 for (i = dst->pos; i < min_copy; i += sizeof(elf_greg_t), index++)
1127 if (access_elf_reg(dst->target, info, i,
1128 &tmp[index], 0) < 0) {
1132 dst->ret = utrace_regset_copyout(&dst->pos, &dst->count,
1133 &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
1134 ELF_CR_IIP_OFFSET, ELF_AR_END_OFFSET);
1138 void do_gpregs_set(struct unw_frame_info *info, void *arg)
1141 utrace_getset_t *dst = arg;
1143 unsigned int i, index;
1145 if (unw_unwind_to_user(info) < 0)
1149 if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(1)) {
1150 dst->ret = utrace_regset_copyin_ignore(&dst->pos, &dst->count,
1153 0, ELF_GR_OFFSET(1));
1154 if (dst->ret || dst->count == 0)
1159 if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(16)) {
1161 index = (dst->pos - ELF_GR_OFFSET(1)) / sizeof(elf_greg_t);
1162 dst->ret = utrace_regset_copyin(&dst->pos, &dst->count,
1163 &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
1164 ELF_GR_OFFSET(1), ELF_GR_OFFSET(16));
1167 for ( ; i < dst->pos; i += sizeof(elf_greg_t), index++)
1168 if (access_elf_reg(dst->target, info, i,
1169 &tmp[index], 1) < 0) {
1173 if (dst->count == 0)
1178 if (dst->count > 0 && dst->pos < ELF_NAT_OFFSET) {
1179 pt = task_pt_regs(dst->target);
1180 dst->ret = utrace_regset_copyin(&dst->pos, &dst->count,
1181 &dst->u.set.kbuf, &dst->u.set.ubuf, &pt->r16,
1182 ELF_GR_OFFSET(16), ELF_NAT_OFFSET);
1183 if (dst->ret || dst->count == 0)
1187 /* nat, pr, b0 - b7 */
1188 if (dst->count > 0 && dst->pos < ELF_CR_IIP_OFFSET) {
1190 index = (dst->pos - ELF_NAT_OFFSET) / sizeof(elf_greg_t);
1191 dst->ret = utrace_regset_copyin(&dst->pos, &dst->count,
1192 &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
1193 ELF_NAT_OFFSET, ELF_CR_IIP_OFFSET);
1196 for (; i < dst->pos; i += sizeof(elf_greg_t), index++)
1197 if (access_elf_reg(dst->target, info, i,
1198 &tmp[index], 1) < 0) {
1202 if (dst->count == 0)
1206 /* ip cfm psr ar.rsc ar.bsp ar.bspstore ar.rnat
1207 * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
1209 if (dst->count > 0 && dst->pos < (ELF_AR_END_OFFSET)) {
1211 index = (dst->pos - ELF_CR_IIP_OFFSET) / sizeof(elf_greg_t);
1212 dst->ret = utrace_regset_copyin(&dst->pos, &dst->count,
1213 &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
1214 ELF_CR_IIP_OFFSET, ELF_AR_END_OFFSET);
1217 for ( ; i < dst->pos; i += sizeof(elf_greg_t), index++)
1218 if (access_elf_reg(dst->target, info, i,
1219 &tmp[index], 1) < 0) {
1226 #define ELF_FP_OFFSET(i) (i * sizeof(elf_fpreg_t))
1228 void do_fpregs_get(struct unw_frame_info *info, void *arg)
1230 utrace_getset_t *dst = arg;
1231 struct task_struct *task = dst->target;
1232 elf_fpreg_t tmp[30];
1233 int index, min_copy, i;
1235 if (unw_unwind_to_user(info) < 0)
1238 /* Skip pos 0 and 1 */
1239 if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(2)) {
1240 dst->ret = utrace_regset_copyout_zero(&dst->pos, &dst->count,
1243 0, ELF_FP_OFFSET(2));
1244 if (dst->count == 0 || dst->ret)
1249 if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(32)) {
1250 index = (dst->pos - ELF_FP_OFFSET(2)) / sizeof(elf_fpreg_t);
1251 min_copy = min(((unsigned int)ELF_FP_OFFSET(32)),
1252 dst->pos + dst->count);
1253 for (i = dst->pos; i < min_copy; i += sizeof(elf_fpreg_t), index++)
1254 if (unw_get_fr(info, i / sizeof(elf_fpreg_t),
1259 dst->ret = utrace_regset_copyout(&dst->pos, &dst->count,
1260 &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
1261 ELF_FP_OFFSET(2), ELF_FP_OFFSET(32));
1262 if (dst->count == 0 || dst->ret)
1267 if (dst->count > 0) {
1268 ia64_flush_fph(dst->target);
1269 if (task->thread.flags & IA64_THREAD_FPH_VALID)
1270 dst->ret = utrace_regset_copyout(
1271 &dst->pos, &dst->count,
1272 &dst->u.get.kbuf, &dst->u.get.ubuf,
1273 &dst->target->thread.fph,
1274 ELF_FP_OFFSET(32), -1);
1276 /* Zero fill instead. */
1277 dst->ret = utrace_regset_copyout_zero(
1278 &dst->pos, &dst->count,
1279 &dst->u.get.kbuf, &dst->u.get.ubuf,
1280 ELF_FP_OFFSET(32), -1);
1284 void do_fpregs_set(struct unw_frame_info *info, void *arg)
1286 utrace_getset_t *dst = arg;
1287 elf_fpreg_t fpreg, tmp[30];
1288 int index, start, end;
1290 if (unw_unwind_to_user(info) < 0)
1293 /* Skip pos 0 and 1 */
1294 if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(2)) {
1295 dst->ret = utrace_regset_copyin_ignore(&dst->pos, &dst->count,
1298 0, ELF_FP_OFFSET(2));
1299 if (dst->count == 0 || dst->ret)
1304 if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(32)) {
1306 end = min(((unsigned int)ELF_FP_OFFSET(32)),
1307 dst->pos + dst->count);
1308 dst->ret = utrace_regset_copyin(&dst->pos, &dst->count,
1309 &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
1310 ELF_FP_OFFSET(2), ELF_FP_OFFSET(32));
1314 if (start & 0xF) { // only write high part
1315 if (unw_get_fr(info, start / sizeof(elf_fpreg_t),
1320 tmp[start / sizeof(elf_fpreg_t) - 2].u.bits[0]
1324 if (end & 0xF) { // only write low part
1325 if (unw_get_fr(info, end / sizeof(elf_fpreg_t), &fpreg)) {
1329 tmp[end / sizeof(elf_fpreg_t) -2].u.bits[1]
1331 end = (end + 0xF) & ~0xFUL;
1334 for ( ; start < end ; start += sizeof(elf_fpreg_t)) {
1335 index = start / sizeof(elf_fpreg_t);
1336 if (unw_set_fr(info, index, tmp[index - 2])){
1341 if (dst->ret || dst->count == 0)
1346 if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(128)) {
1347 ia64_sync_fph(dst->target);
1348 dst->ret = utrace_regset_copyin(&dst->pos, &dst->count,
1351 &dst->target->thread.fph,
1352 ELF_FP_OFFSET(32), -1);
1357 do_regset_call(void (*call)(struct unw_frame_info *, void *),
1358 struct task_struct *target,
1359 const struct utrace_regset *regset,
1360 unsigned int pos, unsigned int count,
1361 const void *kbuf, const void __user *ubuf)
1363 utrace_getset_t info = { .target = target, .regset = regset,
1364 .pos = pos, .count = count,
1365 .u.set = { .kbuf = kbuf, .ubuf = ubuf },
1368 if (target == current)
1369 unw_init_running(call, &info);
1371 struct unw_frame_info ufi;
1372 memset(&ufi, 0, sizeof(ufi));
1373 unw_init_from_blocked_task(&ufi, target);
1374 (*call)(&ufi, &info);
1381 gpregs_get(struct task_struct *target,
1382 const struct utrace_regset *regset,
1383 unsigned int pos, unsigned int count,
1384 void *kbuf, void __user *ubuf)
1386 return do_regset_call(do_gpregs_get, target, regset, pos, count, kbuf, ubuf);
1389 static int gpregs_set(struct task_struct *target,
1390 const struct utrace_regset *regset,
1391 unsigned int pos, unsigned int count,
1392 const void *kbuf, const void __user *ubuf)
1394 return do_regset_call(do_gpregs_set, target, regset, pos, count, kbuf, ubuf);
1397 static void do_gpregs_writeback(struct unw_frame_info *info, void *arg)
1400 utrace_getset_t *dst = arg;
1401 unsigned long urbs_end;
1403 if (unw_unwind_to_user(info) < 0)
1405 pt = task_pt_regs(dst->target);
1406 urbs_end = ia64_get_user_rbs_end(dst->target, pt, NULL);
1407 dst->ret = ia64_sync_user_rbs(dst->target, info->sw, pt->ar_bspstore, urbs_end);
1410 * This is called to write back the register backing store.
1411 * ptrace does this before it stops, so that a tracer reading the user
1412 * memory after the thread stops will get the current register data.
1415 gpregs_writeback(struct task_struct *target,
1416 const struct utrace_regset *regset,
1419 return do_regset_call(do_gpregs_writeback, target, regset, 0, 0, NULL, NULL);
1423 fpregs_active(struct task_struct *target, const struct utrace_regset *regset)
1425 return (target->thread.flags & IA64_THREAD_FPH_VALID) ? 128 : 32;
1428 static int fpregs_get(struct task_struct *target,
1429 const struct utrace_regset *regset,
1430 unsigned int pos, unsigned int count,
1431 void *kbuf, void __user *ubuf)
1433 return do_regset_call(do_fpregs_get, target, regset, pos, count, kbuf, ubuf);
1436 static int fpregs_set(struct task_struct *target,
1437 const struct utrace_regset *regset,
1438 unsigned int pos, unsigned int count,
1439 const void *kbuf, const void __user *ubuf)
1441 return do_regset_call(do_fpregs_set, target, regset, pos, count, kbuf, ubuf);
1444 static int dbregs_get(struct task_struct *target,
1445 const struct utrace_regset *regset,
1446 unsigned int pos, unsigned int count,
1447 void *kbuf, void __user *ubuf)
1451 #ifdef CONFIG_PERFMON
1453 * Check if debug registers are used by perfmon. This
1454 * test must be done once we know that we can do the
1455 * operation, i.e. the arguments are all valid, but
1456 * before we start modifying the state.
1458 * Perfmon needs to keep a count of how many processes
1459 * are trying to modify the debug registers for system
1460 * wide monitoring sessions.
1462 * We also include read access here, because they may
1463 * cause the PMU-installed debug register state
1464 * (dbr[], ibr[]) to be reset. The two arrays are also
1465 * used by perfmon, but we do not use
1466 * IA64_THREAD_DBG_VALID. The registers are restored
1467 * by the PMU context switch code.
1469 if (pfm_use_debug_registers(target))
1473 if (!(target->thread.flags & IA64_THREAD_DBG_VALID))
1474 ret = utrace_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
1478 if (target == current)
1479 ia64_load_debug_regs(&target->thread.dbr[0]);
1480 preempt_enable_no_resched();
1481 ret = utrace_regset_copyout(&pos, &count, &kbuf, &ubuf,
1482 &target->thread.dbr, 0, -1);
1488 static int dbregs_set(struct task_struct *target,
1489 const struct utrace_regset *regset,
1490 unsigned int pos, unsigned int count,
1491 const void *kbuf, const void __user *ubuf)
1495 #ifdef CONFIG_PERFMON
1496 if (pfm_use_debug_registers(target))
1501 if (!(target->thread.flags & IA64_THREAD_DBG_VALID)){
1502 target->thread.flags |= IA64_THREAD_DBG_VALID;
1503 memset(target->thread.dbr, 0, 2 * sizeof(target->thread.dbr));
1504 } else if (target == current){
1506 ia64_save_debug_regs(&target->thread.dbr[0]);
1507 preempt_enable_no_resched();
1510 ret = utrace_regset_copyin(&pos, &count, &kbuf, &ubuf,
1511 &target->thread.dbr, 0, -1);
1513 for (i = 1; i < IA64_NUM_DBG_REGS; i += 2) {
1514 target->thread.dbr[i] &= ~(7UL << 56);
1515 target->thread.ibr[i] &= ~(7UL << 56);
1521 if (target == current){
1523 ia64_load_debug_regs(&target->thread.dbr[0]);
1524 preempt_enable_no_resched();
1529 static const struct utrace_regset native_regsets[] = {
1532 .size = sizeof(elf_greg_t), .align = sizeof(elf_greg_t),
1533 .get = gpregs_get, .set = gpregs_set,
1534 .writeback = gpregs_writeback
1538 .size = sizeof(elf_fpreg_t), .align = sizeof(elf_fpreg_t),
1539 .get = fpregs_get, .set = fpregs_set, .active = fpregs_active
1542 .n = 2 * IA64_NUM_DBG_REGS, .size = sizeof(long),
1543 .align = sizeof(long),
1544 .get = dbregs_get, .set = dbregs_set
1548 const struct utrace_regset_view utrace_ia64_native = {
1550 .e_machine = EM_IA_64,
1551 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
1553 EXPORT_SYMBOL_GPL(utrace_ia64_native);
1555 #endif /* CONFIG_UTRACE */
1558 #ifdef CONFIG_PTRACE
1560 #define WORD(member, num) \
1561 offsetof(struct pt_all_user_regs, member), \
1562 offsetof(struct pt_all_user_regs, member) + num * sizeof(long)
1563 static const struct ptrace_layout_segment pt_all_user_regs_layout[] = {
1564 {WORD(nat, 1), 0, ELF_NAT_OFFSET},
1565 {WORD(cr_iip, 1), 0, ELF_CR_IIP_OFFSET},
1566 {WORD(cfm, 1), 0, ELF_CFM_OFFSET},
1567 {WORD(cr_ipsr, 1), 0, ELF_CR_IPSR_OFFSET},
1568 {WORD(pr, 1), 0, ELF_PR_OFFSET},
1569 {WORD(gr[0], 1), -1, -1},
1570 {WORD(gr[1], 31), 0, ELF_GR_OFFSET(1)},
1571 {WORD(br[0], 8), 0, ELF_BR_OFFSET(0)},
1572 {WORD(ar[0], 16), -1, -1},
1573 {WORD(ar[PT_AUR_RSC], 4), 0, ELF_AR_RSC_OFFSET},
1574 {WORD(ar[PT_AUR_RNAT+1], 12), -1, -1},
1575 {WORD(ar[PT_AUR_CCV], 1), 0, ELF_AR_CCV_OFFSET},
1576 {WORD(ar[PT_AUR_CCV+1], 3), -1, -1},
1577 {WORD(ar[PT_AUR_UNAT], 1), 0, ELF_AR_UNAT_OFFSET},
1578 {WORD(ar[PT_AUR_UNAT+1], 3), -1, -1},
1579 {WORD(ar[PT_AUR_FPSR], 1), 0, ELF_AR_FPSR_OFFSET},
1580 {WORD(ar[PT_AUR_FPSR+1], 23), -1, -1},
1581 {WORD(ar[PT_AUR_PFS], 3), 0, ELF_AR_PFS_OFFSET},
1582 {WORD(ar[PT_AUR_EC+1], 62), -1, -1},
1583 {offsetof(struct pt_all_user_regs, fr[0]),
1584 offsetof(struct pt_all_user_regs, fr[2]),
1586 {offsetof(struct pt_all_user_regs, fr[2]),
1587 offsetof(struct pt_all_user_regs, fr[128]),
1588 1, 2 * sizeof(elf_fpreg_t)},
1593 #define NEXT(addr, sum) (addr + sum * sizeof(long))
1594 static const struct ptrace_layout_segment pt_uarea_layout[] = {
1595 {PT_F32, PT_NAT_BITS, 1, ELF_FP_OFFSET(32)},
1596 {PT_NAT_BITS, NEXT(PT_NAT_BITS, 1), 0, ELF_NAT_OFFSET},
1597 {PT_F2, PT_F10, 1, ELF_FP_OFFSET(2)},
1598 {PT_F10, PT_R4, 1, ELF_FP_OFFSET(10)},
1599 {PT_R4, PT_B1, 0, ELF_GR_OFFSET(4)},
1600 {PT_B1, PT_AR_EC, 0, ELF_BR_OFFSET(1)},
1601 {PT_AR_EC, PT_AR_LC, 0, ELF_AR_EC_OFFSET},
1602 {PT_AR_LC, NEXT(PT_AR_LC, 1), 0, ELF_AR_LC_OFFSET},
1603 {PT_CR_IPSR, PT_CR_IIP, 0, ELF_CR_IPSR_OFFSET},
1604 {PT_CR_IIP, PT_AR_UNAT, 0, ELF_CR_IIP_OFFSET},
1605 {PT_AR_UNAT, PT_AR_PFS, 0, ELF_AR_UNAT_OFFSET},
1606 {PT_AR_PFS, PT_AR_RSC, 0, ELF_AR_PFS_OFFSET},
1607 {PT_AR_RSC, PT_AR_RNAT, 0, ELF_AR_RSC_OFFSET},
1608 {PT_AR_RNAT, PT_AR_BSPSTORE, 0, ELF_AR_RNAT_OFFSET},
1609 {PT_AR_BSPSTORE,PT_PR, 0, ELF_AR_BSPSTORE_OFFSET},
1610 {PT_PR, PT_B6, 0, ELF_PR_OFFSET},
1611 {PT_B6, PT_AR_BSP, 0, ELF_BR_OFFSET(6)},
1612 {PT_AR_BSP, PT_R1, 0, ELF_AR_BSP_OFFSET},
1613 {PT_R1, PT_R12, 0, ELF_GR_OFFSET(1)},
1614 {PT_R12, PT_R8, 0, ELF_GR_OFFSET(12)},
1615 {PT_R8, PT_R16, 0, ELF_GR_OFFSET(8)},
1616 {PT_R16, PT_AR_CCV, 0, ELF_GR_OFFSET(16)},
1617 {PT_AR_CCV, PT_AR_FPSR, 0, ELF_AR_CCV_OFFSET},
1618 {PT_AR_FPSR, PT_B0, 0, ELF_AR_FPSR_OFFSET},
1619 {PT_B0, PT_B7, 0, ELF_BR_OFFSET(0)},
1620 {PT_B7, PT_F6, 0, ELF_BR_OFFSET(7)},
1621 {PT_F6, PT_AR_CSD, 1, ELF_FP_OFFSET(6)},
1622 {PT_AR_CSD, NEXT(PT_AR_CSD, 2), 0, ELF_AR_CSD_OFFSET},
1623 {PT_DBR, NEXT(PT_DBR, 8), 2, 0},
1624 {PT_IBR, NEXT(PT_IBR, 8), 2, 8 * sizeof(long)},
1629 int arch_ptrace(long *request, struct task_struct *child,
1630 struct utrace_attached_engine *engine,
1631 unsigned long addr, unsigned long data, long *val)
1635 case PTRACE_OLD_GETSIGINFO:
1636 *request = PTRACE_GETSIGINFO;
1638 case PTRACE_OLD_SETSIGINFO:
1639 *request = PTRACE_SETSIGINFO;
1642 case PTRACE_PEEKTEXT: /* read word at location addr. */
1643 case PTRACE_PEEKDATA:
1644 ret = access_process_vm(child, addr, val, sizeof(*val), 0);
1645 ret = ret == sizeof(*val) ? 0 : -EIO;
1648 case PTRACE_PEEKUSR:
1649 return ptrace_layout_access(child, engine,
1650 utrace_native_view(current),
1654 case PTRACE_POKEUSR:
1655 return ptrace_pokeusr(child, engine,
1656 pt_uarea_layout, addr, data);
1658 case PTRACE_GETREGS:
1659 case PTRACE_SETREGS:
1660 return ptrace_layout_access(child, engine,
1661 utrace_native_view(current),
1662 pt_all_user_regs_layout,
1663 0, sizeof(struct pt_all_user_regs),
1664 (void __user *) data, NULL,
1665 *request == PTRACE_SETREGS);
1670 #endif /* CONFIG_PTRACE */