2 * Kernel support for the ptrace() and syscall tracing interfaces.
4 * Copyright (C) 1999-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Derived from the x86 and Alpha versions. Most of the code in here
8 * could actually be factored into a common set of routines.
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp_lock.h>
18 #include <linux/user.h>
19 #include <linux/security.h>
21 #include <asm/pgtable.h>
22 #include <asm/processor.h>
23 #include <asm/ptrace_offsets.h>
25 #include <asm/system.h>
26 #include <asm/uaccess.h>
27 #include <asm/unwind.h>
29 #include <asm/perfmon.h>
34 #define p4 (1UL << 4) /* for pSys (see entry.h) */
35 #define p5 (1UL << 5) /* for pNonSys (see entry.h) */
38 * Bits in the PSR that we allow ptrace() to change:
39 * be, up, ac, mfl, mfh (the user mask; five bits total)
40 * db (debug breakpoint fault; one bit)
41 * id (instruction debug fault disable; one bit)
42 * dd (data debug fault disable; one bit)
43 * ri (restart instruction; two bits)
44 * is (instruction set; one bit)
46 #define IPSR_WRITE_MASK \
47 (IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
48 #define IPSR_READ_MASK IPSR_WRITE_MASK
50 #define PTRACE_DEBUG 0
53 # define dprintk(format...) printk(format)
56 # define dprintk(format...)
59 /* Return TRUE if PT was created due to kernel-entry via a system-call. */
62 in_syscall (struct pt_regs *pt)
64 return (long) pt->cr_ifs >= 0;
68 * Collect the NaT bits for r1-r31 from scratch_unat and return a NaT
69 * bitset where bit i is set iff the NaT bit of register i is set.
72 ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat)
74 # define GET_BITS(first, last, unat) \
76 unsigned long bit = ia64_unat_pos(&pt->r##first); \
77 unsigned long mask = ((1UL << (last - first + 1)) - 1) << first; \
80 dist = 64 + bit - first; \
83 ia64_rotr(unat, dist) & mask; \
88 * Registers that are stored consecutively in struct pt_regs can be handled in
89 * parallel. If the register order in struct_pt_regs changes, this code MUST be
92 val = GET_BITS( 1, 1, scratch_unat);
93 val |= GET_BITS( 2, 3, scratch_unat);
94 val |= GET_BITS(12, 13, scratch_unat);
95 val |= GET_BITS(14, 14, scratch_unat);
96 val |= GET_BITS(15, 15, scratch_unat);
97 val |= GET_BITS( 8, 11, scratch_unat);
98 val |= GET_BITS(16, 31, scratch_unat);
105 * Set the NaT bits for the scratch registers according to NAT and
106 * return the resulting unat (assuming the scratch registers are
110 ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat)
112 # define PUT_BITS(first, last, nat) \
114 unsigned long bit = ia64_unat_pos(&pt->r##first); \
115 unsigned long mask = ((1UL << (last - first + 1)) - 1) << first; \
118 dist = 64 + bit - first; \
120 dist = bit - first; \
121 ia64_rotl(nat & mask, dist); \
123 unsigned long scratch_unat;
126 * Registers that are stored consecutively in struct pt_regs can be handled in
127 * parallel. If the register order in struct_pt_regs changes, this code MUST be
130 scratch_unat = PUT_BITS( 1, 1, nat);
131 scratch_unat |= PUT_BITS( 2, 3, nat);
132 scratch_unat |= PUT_BITS(12, 13, nat);
133 scratch_unat |= PUT_BITS(14, 14, nat);
134 scratch_unat |= PUT_BITS(15, 15, nat);
135 scratch_unat |= PUT_BITS( 8, 11, nat);
136 scratch_unat |= PUT_BITS(16, 31, nat);
143 #define IA64_MLX_TEMPLATE 0x2
144 #define IA64_MOVL_OPCODE 6
147 ia64_increment_ip (struct pt_regs *regs)
149 unsigned long w0, ri = ia64_psr(regs)->ri + 1;
154 } else if (ri == 2) {
155 get_user(w0, (char __user *) regs->cr_iip + 0);
156 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
158 * rfi'ing to slot 2 of an MLX bundle causes
159 * an illegal operation fault. We don't want
166 ia64_psr(regs)->ri = ri;
170 ia64_decrement_ip (struct pt_regs *regs)
172 unsigned long w0, ri = ia64_psr(regs)->ri - 1;
174 if (ia64_psr(regs)->ri == 0) {
177 get_user(w0, (char __user *) regs->cr_iip + 0);
178 if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
180 * rfi'ing to slot 2 of an MLX bundle causes
181 * an illegal operation fault. We don't want
187 ia64_psr(regs)->ri = ri;
191 * This routine is used to read an rnat bits that are stored on the kernel backing store.
192 * Since, in general, the alignment of the user and kernel are different, this is not
193 * completely trivial. In essence, we need to construct the user RNAT based on up to two
194 * kernel RNAT values and/or the RNAT value saved in the child's pt_regs.
198 * +--------+ <-- lowest address
205 * | slot01 | > child_regs->ar_rnat
207 * | slot02 | / kernel rbs
208 * +--------+ +--------+
209 * <- child_regs->ar_bspstore | slot61 | <-- krbs
210 * +- - - - + +--------+
212 * +- - - - + +--------+
214 * +- - - - + +--------+
216 * +- - - - + +--------+
221 * | slot01 | > child_stack->ar_rnat
225 * <--- child_stack->ar_bspstore
227 * The way to think of this code is as follows: bit 0 in the user rnat corresponds to some
228 * bit N (0 <= N <= 62) in one of the kernel rnat value. The kernel rnat value holding
229 * this bit is stored in variable rnat0. rnat1 is loaded with the kernel rnat value that
230 * form the upper bits of the user rnat value.
234 * o when reading the rnat "below" the first rnat slot on the kernel backing store,
235 * rnat0/rnat1 are set to 0 and the low order bits are merged in from pt->ar_rnat.
237 * o when reading the rnat "above" the last rnat slot on the kernel backing store,
238 * rnat0/rnat1 gets its value from sw->ar_rnat.
241 get_rnat (struct task_struct *task, struct switch_stack *sw,
242 unsigned long *krbs, unsigned long *urnat_addr, unsigned long *urbs_end)
244 unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr, umask = 0, mask, m;
245 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
246 long num_regs, nbits;
249 pt = ia64_task_regs(task);
250 kbsp = (unsigned long *) sw->ar_bspstore;
251 ubspstore = (unsigned long *) pt->ar_bspstore;
253 if (urbs_end < urnat_addr)
254 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_end);
257 mask = (1UL << nbits) - 1;
259 * First, figure out which bit number slot 0 in user-land maps to in the kernel
260 * rnat. Do this by figuring out how many register slots we're beyond the user's
261 * backingstore and then computing the equivalent address in kernel space.
263 num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
264 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
265 shift = ia64_rse_slot_num(slot0_kaddr);
266 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
267 rnat0_kaddr = rnat1_kaddr - 64;
269 if (ubspstore + 63 > urnat_addr) {
270 /* some bits need to be merged in from pt->ar_rnat */
271 umask = ((1UL << ia64_rse_slot_num(ubspstore)) - 1) & mask;
272 urnat = (pt->ar_rnat & umask);
279 if (rnat0_kaddr >= kbsp)
281 else if (rnat0_kaddr > krbs)
282 rnat0 = *rnat0_kaddr;
283 urnat |= (rnat0 & m) >> shift;
285 m = mask >> (63 - shift);
286 if (rnat1_kaddr >= kbsp)
288 else if (rnat1_kaddr > krbs)
289 rnat1 = *rnat1_kaddr;
290 urnat |= (rnat1 & m) << (63 - shift);
295 * The reverse of get_rnat.
298 put_rnat (struct task_struct *task, struct switch_stack *sw,
299 unsigned long *krbs, unsigned long *urnat_addr, unsigned long urnat,
300 unsigned long *urbs_end)
302 unsigned long rnat0 = 0, rnat1 = 0, *slot0_kaddr, umask = 0, mask, m;
303 unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
304 long num_regs, nbits;
306 unsigned long cfm, *urbs_kargs;
308 pt = ia64_task_regs(task);
309 kbsp = (unsigned long *) sw->ar_bspstore;
310 ubspstore = (unsigned long *) pt->ar_bspstore;
312 urbs_kargs = urbs_end;
313 if (in_syscall(pt)) {
315 * If entered via syscall, don't allow user to set rnat bits
319 urbs_kargs = ia64_rse_skip_regs(urbs_end, -(cfm & 0x7f));
322 if (urbs_kargs >= urnat_addr)
325 if ((urnat_addr - 63) >= urbs_kargs)
327 nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_kargs);
329 mask = (1UL << nbits) - 1;
332 * First, figure out which bit number slot 0 in user-land maps to in the kernel
333 * rnat. Do this by figuring out how many register slots we're beyond the user's
334 * backingstore and then computing the equivalent address in kernel space.
336 num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
337 slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
338 shift = ia64_rse_slot_num(slot0_kaddr);
339 rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
340 rnat0_kaddr = rnat1_kaddr - 64;
342 if (ubspstore + 63 > urnat_addr) {
343 /* some bits need to be place in pt->ar_rnat: */
344 umask = ((1UL << ia64_rse_slot_num(ubspstore)) - 1) & mask;
345 pt->ar_rnat = (pt->ar_rnat & ~umask) | (urnat & umask);
351 * Note: Section 11.1 of the EAS guarantees that bit 63 of an
352 * rnat slot is ignored. so we don't have to clear it here.
354 rnat0 = (urnat << shift);
356 if (rnat0_kaddr >= kbsp)
357 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat0 & m);
358 else if (rnat0_kaddr > krbs)
359 *rnat0_kaddr = ((*rnat0_kaddr & ~m) | (rnat0 & m));
361 rnat1 = (urnat >> (63 - shift));
362 m = mask >> (63 - shift);
363 if (rnat1_kaddr >= kbsp)
364 sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat1 & m);
365 else if (rnat1_kaddr > krbs)
366 *rnat1_kaddr = ((*rnat1_kaddr & ~m) | (rnat1 & m));
370 on_kernel_rbs (unsigned long addr, unsigned long bspstore, unsigned long urbs_end)
372 return (addr >= bspstore
373 && addr <= (unsigned long) ia64_rse_rnat_addr((unsigned long *) urbs_end));
377 * Read a word from the user-level backing store of task CHILD. ADDR is the user-level
378 * address to read the word from, VAL a pointer to the return value, and USER_BSP gives
379 * the end of the user-level backing store (i.e., it's the address that would be in ar.bsp
380 * after the user executed a "cover" instruction).
382 * This routine takes care of accessing the kernel register backing store for those
383 * registers that got spilled there. It also takes care of calculating the appropriate
384 * RNaT collection words.
387 ia64_peek (struct task_struct *child, struct switch_stack *child_stack, unsigned long user_rbs_end,
388 unsigned long addr, long *val)
390 unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end, *rnat_addr;
391 struct pt_regs *child_regs;
395 urbs_end = (long *) user_rbs_end;
396 laddr = (unsigned long *) addr;
397 child_regs = ia64_task_regs(child);
398 bspstore = (unsigned long *) child_regs->ar_bspstore;
399 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
400 if (on_kernel_rbs(addr, (unsigned long) bspstore, (unsigned long) urbs_end)) {
402 * Attempt to read the RBS in an area that's actually on the kernel RBS =>
403 * read the corresponding bits in the kernel RBS.
405 rnat_addr = ia64_rse_rnat_addr(laddr);
406 ret = get_rnat(child, child_stack, krbs, rnat_addr, urbs_end);
408 if (laddr == rnat_addr) {
409 /* return NaT collection word itself */
414 if (((1UL << ia64_rse_slot_num(laddr)) & ret) != 0) {
416 * It is implementation dependent whether the data portion of a
417 * NaT value gets saved on a st8.spill or RSE spill (e.g., see
418 * EAS 2.6, 4.4.4.6 Register Spill and Fill). To get consistent
419 * behavior across all possible IA-64 implementations, we return
426 if (laddr < urbs_end) {
427 /* the desired word is on the kernel RBS and is not a NaT */
428 regnum = ia64_rse_num_regs(bspstore, laddr);
429 *val = *ia64_rse_skip_regs(krbs, regnum);
433 copied = access_process_vm(child, addr, &ret, sizeof(ret), 0);
434 if (copied != sizeof(ret))
441 ia64_poke (struct task_struct *child, struct switch_stack *child_stack, unsigned long user_rbs_end,
442 unsigned long addr, long val)
444 unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end = (long *) user_rbs_end;
445 struct pt_regs *child_regs;
447 laddr = (unsigned long *) addr;
448 child_regs = ia64_task_regs(child);
449 bspstore = (unsigned long *) child_regs->ar_bspstore;
450 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
451 if (on_kernel_rbs(addr, (unsigned long) bspstore, (unsigned long) urbs_end)) {
453 * Attempt to write the RBS in an area that's actually on the kernel RBS
454 * => write the corresponding bits in the kernel RBS.
456 if (ia64_rse_is_rnat_slot(laddr))
457 put_rnat(child, child_stack, krbs, laddr, val, urbs_end);
459 if (laddr < urbs_end) {
460 regnum = ia64_rse_num_regs(bspstore, laddr);
461 *ia64_rse_skip_regs(krbs, regnum) = val;
464 } else if (access_process_vm(child, addr, &val, sizeof(val), 1) != sizeof(val)) {
471 * Calculate the address of the end of the user-level register backing store. This is the
472 * address that would have been stored in ar.bsp if the user had executed a "cover"
473 * instruction right before entering the kernel. If CFMP is not NULL, it is used to
474 * return the "current frame mask" that was active at the time the kernel was entered.
477 ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt, unsigned long *cfmp)
479 unsigned long *krbs, *bspstore, cfm = pt->cr_ifs;
482 krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
483 bspstore = (unsigned long *) pt->ar_bspstore;
484 ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
487 ndirty += (cfm & 0x7f);
489 cfm &= ~(1UL << 63); /* clear valid bit */
493 return (unsigned long) ia64_rse_skip_regs(bspstore, ndirty);
497 * Synchronize (i.e, write) the RSE backing store living in kernel space to the VM of the
498 * CHILD task. SW and PT are the pointers to the switch_stack and pt_regs structures,
499 * respectively. USER_RBS_END is the user-level address at which the backing store ends.
502 ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
503 unsigned long user_rbs_start, unsigned long user_rbs_end)
505 unsigned long addr, val;
508 /* now copy word for word from kernel rbs to user rbs: */
509 for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
510 ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
513 if (access_process_vm(child, addr, &val, sizeof(val), 1) != sizeof(val))
520 thread_matches (struct task_struct *thread, unsigned long addr)
522 unsigned long thread_rbs_end;
523 struct pt_regs *thread_regs;
525 if (ptrace_check_attach(thread, 0) < 0)
527 * If the thread is not in an attachable state, we'll ignore it.
528 * The net effect is that if ADDR happens to overlap with the
529 * portion of the thread's register backing store that is
530 * currently residing on the thread's kernel stack, then ptrace()
531 * may end up accessing a stale value. But if the thread isn't
532 * stopped, that's a problem anyhow, so we're doing as well as we
537 thread_regs = ia64_task_regs(thread);
538 thread_rbs_end = ia64_get_user_rbs_end(thread, thread_regs, NULL);
539 if (!on_kernel_rbs(addr, thread_regs->ar_bspstore, thread_rbs_end))
542 return 1; /* looks like we've got a winner */
546 * GDB apparently wants to be able to read the register-backing store of any thread when
547 * attached to a given process. If we are peeking or poking an address that happens to
548 * reside in the kernel-backing store of another thread, we need to attach to that thread,
549 * because otherwise we end up accessing stale data.
551 * task_list_lock must be read-locked before calling this routine!
553 static struct task_struct *
554 find_thread_for_addr (struct task_struct *child, unsigned long addr)
556 struct task_struct *g, *p;
557 struct mm_struct *mm;
560 if (!(mm = get_task_mm(child)))
563 mm_users = atomic_read(&mm->mm_users) - 1; /* -1 because of our get_task_mm()... */
565 goto out; /* not multi-threaded */
568 * First, traverse the child's thread-list. Good for scalability with
573 if (thread_matches(p, addr)) {
579 } while ((p = next_thread(p)) != child);
581 do_each_thread(g, p) {
585 if (thread_matches(p, addr)) {
589 } while_each_thread(g, p);
596 * Write f32-f127 back to task->thread.fph if it has been modified.
599 ia64_flush_fph (struct task_struct *task)
601 struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
603 if (ia64_is_local_fpu_owner(task) && psr->mfh) {
605 task->thread.flags |= IA64_THREAD_FPH_VALID;
606 ia64_save_fpu(&task->thread.fph[0]);
611 * Sync the fph state of the task so that it can be manipulated
612 * through thread.fph. If necessary, f32-f127 are written back to
613 * thread.fph or, if the fph state hasn't been used before, thread.fph
614 * is cleared to zeroes. Also, access to f32-f127 is disabled to
615 * ensure that the task picks up the state from thread.fph when it
619 ia64_sync_fph (struct task_struct *task)
621 struct ia64_psr *psr = ia64_psr(ia64_task_regs(task));
623 ia64_flush_fph(task);
624 if (!(task->thread.flags & IA64_THREAD_FPH_VALID)) {
625 task->thread.flags |= IA64_THREAD_FPH_VALID;
626 memset(&task->thread.fph, 0, sizeof(task->thread.fph));
633 access_fr (struct unw_frame_info *info, int regnum, int hi, unsigned long *data, int write_access)
635 struct ia64_fpreg fpval;
638 ret = unw_get_fr(info, regnum, &fpval);
643 fpval.u.bits[hi] = *data;
644 ret = unw_set_fr(info, regnum, fpval);
646 *data = fpval.u.bits[hi];
651 * Change the machine-state of CHILD such that it will return via the normal
652 * kernel exit-path, rather than the syscall-exit path.
655 convert_to_non_syscall (struct task_struct *child, struct pt_regs *pt, unsigned long cfm)
657 struct unw_frame_info info, prev_info;
658 unsigned long ip, pr;
660 unw_init_from_blocked_task(&info, child);
663 if (unw_unwind(&info) < 0)
665 if (unw_get_rp(&info, &ip) < 0)
667 if (ip < FIXADDR_USER_END)
671 unw_get_pr(&prev_info, &pr);
674 unw_set_pr(&prev_info, pr);
676 pt->cr_ifs = (1UL << 63) | cfm;
680 access_uarea (struct task_struct *child, unsigned long addr, unsigned long *data, int write_access)
682 unsigned long *ptr, regnum, urbs_end, rnat_addr, cfm;
683 struct switch_stack *sw;
686 pt = ia64_task_regs(child);
687 sw = (struct switch_stack *) (child->thread.ksp + 16);
689 if ((addr & 0x7) != 0) {
690 dprintk("ptrace: unaligned register address 0x%lx\n", addr);
694 if (addr < PT_F127 + 16) {
697 ia64_sync_fph(child);
699 ia64_flush_fph(child);
700 ptr = (unsigned long *) ((unsigned long) &child->thread.fph + addr);
701 } else if ((addr >= PT_F10) && (addr < PT_F11 + 16)) {
702 /* scratch registers untouched by kernel (saved in pt_regs) */
703 ptr = (unsigned long *)
704 ((long) pt + offsetof(struct pt_regs, f10) + addr - PT_F10);
705 } else if (addr >= PT_F12 && addr < PT_F15 + 16) {
706 /* scratch registers untouched by kernel (saved in switch_stack) */
707 ptr = (unsigned long *) ((long) sw + (addr - PT_NAT_BITS - 32));
708 } else if (addr < PT_AR_LC + 8) {
709 /* preserved state: */
710 unsigned long nat_bits, scratch_unat, dummy = 0;
711 struct unw_frame_info info;
715 unw_init_from_blocked_task(&info, child);
716 if (unw_unwind_to_user(&info) < 0)
723 scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
724 if (unw_set_ar(&info, UNW_AR_UNAT, scratch_unat) < 0) {
725 dprintk("ptrace: failed to set ar.unat\n");
728 for (regnum = 4; regnum <= 7; ++regnum) {
729 unw_get_gr(&info, regnum, &dummy, &nat);
730 unw_set_gr(&info, regnum, dummy, (nat_bits >> regnum) & 1);
733 if (unw_get_ar(&info, UNW_AR_UNAT, &scratch_unat) < 0) {
734 dprintk("ptrace: failed to read ar.unat\n");
737 nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
738 for (regnum = 4; regnum <= 7; ++regnum) {
739 unw_get_gr(&info, regnum, &dummy, &nat);
740 nat_bits |= (nat != 0) << regnum;
746 case PT_R4: case PT_R5: case PT_R6: case PT_R7:
748 /* read NaT bit first: */
751 ret = unw_get_gr(&info, (addr - PT_R4)/8 + 4, &dummy, &nat);
755 return unw_access_gr(&info, (addr - PT_R4)/8 + 4, data, &nat,
758 case PT_B1: case PT_B2: case PT_B3: case PT_B4: case PT_B5:
759 return unw_access_br(&info, (addr - PT_B1)/8 + 1, data, write_access);
762 return unw_access_ar(&info, UNW_AR_EC, data, write_access);
765 return unw_access_ar(&info, UNW_AR_LC, data, write_access);
768 if (addr >= PT_F2 && addr < PT_F5 + 16)
769 return access_fr(&info, (addr - PT_F2)/16 + 2, (addr & 8) != 0,
771 else if (addr >= PT_F16 && addr < PT_F31 + 16)
772 return access_fr(&info, (addr - PT_F16)/16 + 16, (addr & 8) != 0,
775 dprintk("ptrace: rejecting access to register address 0x%lx\n",
780 } else if (addr < PT_F9+16) {
785 * By convention, we use PT_AR_BSP to refer to the end of the user-level
786 * backing store. Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof) to get
787 * the real value of ar.bsp at the time the kernel was entered.
789 * Furthermore, when changing the contents of PT_AR_BSP (or
790 * PT_CFM) we MUST copy any users-level stacked registers that are
791 * stored on the kernel stack back to user-space because
792 * otherwise, we might end up clobbering kernel stacked registers.
793 * Also, if this happens while the task is blocked in a system
794 * call, which convert the state such that the non-system-call
795 * exit path is used. This ensures that the proper state will be
796 * picked up when resuming execution. However, it *also* means
797 * that once we write PT_AR_BSP/PT_CFM, it won't be possible to
798 * modify the syscall arguments of the pending system call any
799 * longer. This shouldn't be an issue because modifying
800 * PT_AR_BSP/PT_CFM generally implies that we're either abandoning
801 * the pending system call or that we defer it's re-execution
802 * (e.g., due to GDB doing an inferior function call).
804 urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
806 if (*data != urbs_end) {
807 if (ia64_sync_user_rbs(child, sw,
808 pt->ar_bspstore, urbs_end) < 0)
811 convert_to_non_syscall(child, pt, cfm);
812 /* simulate user-level write of ar.bsp: */
814 pt->ar_bspstore = *data;
821 urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
823 if (((cfm ^ *data) & 0x3fffffffffUL) != 0) {
824 if (ia64_sync_user_rbs(child, sw,
825 pt->ar_bspstore, urbs_end) < 0)
828 convert_to_non_syscall(child, pt, cfm);
829 pt->cr_ifs = ((pt->cr_ifs & ~0x3fffffffffUL)
830 | (*data & 0x3fffffffffUL));
838 pt->cr_ipsr = ((*data & IPSR_WRITE_MASK)
839 | (pt->cr_ipsr & ~IPSR_WRITE_MASK));
841 *data = (pt->cr_ipsr & IPSR_READ_MASK);
845 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
846 rnat_addr = (long) ia64_rse_rnat_addr((long *) urbs_end);
848 return ia64_poke(child, sw, urbs_end, rnat_addr, *data);
850 return ia64_peek(child, sw, urbs_end, rnat_addr, data);
853 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, r1));
856 case PT_R2: case PT_R3:
857 ptr = (unsigned long *)
858 ((long) pt + offsetof(struct pt_regs, r2) + addr - PT_R2);
860 case PT_R8: case PT_R9: case PT_R10: case PT_R11:
861 ptr = (unsigned long *)
862 ((long) pt + offsetof(struct pt_regs, r8)+ addr - PT_R8);
864 case PT_R12: case PT_R13:
865 ptr = (unsigned long *)
866 ((long) pt + offsetof(struct pt_regs, r12)+ addr - PT_R12);
869 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, r14));
872 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, r15));
874 case PT_R16: case PT_R17: case PT_R18: case PT_R19:
875 case PT_R20: case PT_R21: case PT_R22: case PT_R23:
876 case PT_R24: case PT_R25: case PT_R26: case PT_R27:
877 case PT_R28: case PT_R29: case PT_R30: case PT_R31:
878 ptr = (unsigned long *)
879 ((long) pt + offsetof(struct pt_regs, r16) + addr - PT_R16);
882 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, b0));
885 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, b6));
888 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, b7));
890 case PT_F6: case PT_F6+8: case PT_F7: case PT_F7+8:
891 case PT_F8: case PT_F8+8: case PT_F9: case PT_F9+8:
892 ptr = (unsigned long *)
893 ((long) pt + offsetof(struct pt_regs, f6) + addr - PT_F6);
896 ptr = (unsigned long *)
897 ((long) pt + offsetof(struct pt_regs, ar_bspstore));
900 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_rsc));
903 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_unat));
906 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_pfs));
909 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_ccv));
912 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, ar_fpsr));
915 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, cr_iip));
918 ptr = (unsigned long *) ((long) pt + offsetof(struct pt_regs, pr));
920 /* scratch register */
923 /* disallow accessing anything else... */
924 dprintk("ptrace: rejecting access to register address 0x%lx\n",
928 } else if (addr <= PT_AR_SSD) {
929 ptr = (unsigned long *)
930 ((long) pt + offsetof(struct pt_regs, ar_csd) + addr - PT_AR_CSD);
932 /* access debug registers */
934 if (addr >= PT_IBR) {
935 regnum = (addr - PT_IBR) >> 3;
936 ptr = &child->thread.ibr[0];
938 regnum = (addr - PT_DBR) >> 3;
939 ptr = &child->thread.dbr[0];
943 dprintk("ptrace: rejecting access to register address 0x%lx\n", addr);
946 #ifdef CONFIG_PERFMON
948 * Check if debug registers are used by perfmon. This test must be done
949 * once we know that we can do the operation, i.e. the arguments are all
950 * valid, but before we start modifying the state.
952 * Perfmon needs to keep a count of how many processes are trying to
953 * modify the debug registers for system wide monitoring sessions.
955 * We also include read access here, because they may cause the
956 * PMU-installed debug register state (dbr[], ibr[]) to be reset. The two
957 * arrays are also used by perfmon, but we do not use
958 * IA64_THREAD_DBG_VALID. The registers are restored by the PMU context
961 if (pfm_use_debug_registers(child)) return -1;
964 if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
965 child->thread.flags |= IA64_THREAD_DBG_VALID;
966 memset(child->thread.dbr, 0, sizeof(child->thread.dbr));
967 memset(child->thread.ibr, 0, sizeof(child->thread.ibr));
973 /* don't let the user set kernel-level breakpoints... */
974 *ptr = *data & ~(7UL << 56);
987 ptrace_getregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
989 unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val;
990 struct unw_frame_info info;
991 struct ia64_fpreg fpval;
992 struct switch_stack *sw;
998 retval = verify_area(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs));
1003 pt = ia64_task_regs(child);
1004 sw = (struct switch_stack *) (child->thread.ksp + 16);
1005 unw_init_from_blocked_task(&info, child);
1006 if (unw_unwind_to_user(&info) < 0) {
1010 if (((unsigned long) ppr & 0x7) != 0) {
1011 dprintk("ptrace:unaligned register address %p\n", ppr);
1015 if (access_uarea(child, PT_CR_IPSR, &psr, 0) < 0
1016 || access_uarea(child, PT_AR_EC, &ec, 0) < 0
1017 || access_uarea(child, PT_AR_LC, &lc, 0) < 0
1018 || access_uarea(child, PT_AR_RNAT, &rnat, 0) < 0
1019 || access_uarea(child, PT_AR_BSP, &bsp, 0) < 0
1020 || access_uarea(child, PT_CFM, &cfm, 0)
1021 || access_uarea(child, PT_NAT_BITS, &nat_bits, 0))
1028 retval |= __put_user(pt->cr_iip, &ppr->cr_iip);
1029 retval |= __put_user(psr, &ppr->cr_ipsr);
1033 retval |= __put_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
1034 retval |= __put_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
1035 retval |= __put_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
1036 retval |= __put_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
1037 retval |= __put_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
1038 retval |= __put_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
1040 retval |= __put_user(ec, &ppr->ar[PT_AUR_EC]);
1041 retval |= __put_user(lc, &ppr->ar[PT_AUR_LC]);
1042 retval |= __put_user(rnat, &ppr->ar[PT_AUR_RNAT]);
1043 retval |= __put_user(bsp, &ppr->ar[PT_AUR_BSP]);
1044 retval |= __put_user(cfm, &ppr->cfm);
1048 retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long));
1049 retval |= __copy_to_user(&ppr->gr[2], &pt->r2, sizeof(long) *2);
1053 for (i = 4; i < 8; i++) {
1054 if (unw_access_gr(&info, i, &val, &nat, 0) < 0)
1056 retval |= __put_user(val, &ppr->gr[i]);
1061 retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4);
1065 retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 2);
1066 retval |= __copy_to_user(&ppr->gr[14], &pt->r14, sizeof(long));
1067 retval |= __copy_to_user(&ppr->gr[15], &pt->r15, sizeof(long));
1071 retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16);
1075 retval |= __put_user(pt->b0, &ppr->br[0]);
1079 for (i = 1; i < 6; i++) {
1080 if (unw_access_br(&info, i, &val, 0) < 0)
1082 __put_user(val, &ppr->br[i]);
1087 retval |= __put_user(pt->b6, &ppr->br[6]);
1088 retval |= __put_user(pt->b7, &ppr->br[7]);
1092 for (i = 2; i < 6; i++) {
1093 if (unw_get_fr(&info, i, &fpval) < 0)
1095 retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
1100 retval |= __copy_to_user(&ppr->fr[6], &pt->f6, sizeof(struct ia64_fpreg) * 6);
1102 /* fp scratch regs(12-15) */
1104 retval |= __copy_to_user(&ppr->fr[12], &sw->f12, sizeof(struct ia64_fpreg) * 4);
1108 for (i = 16; i < 32; i++) {
1109 if (unw_get_fr(&info, i, &fpval) < 0)
1111 retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
1116 ia64_flush_fph(child);
1117 retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph, sizeof(ppr->fr[32]) * 96);
1121 retval |= __put_user(pt->pr, &ppr->pr);
1125 retval |= __put_user(nat_bits, &ppr->nat);
1127 ret = retval ? -EIO : 0;
1132 ptrace_setregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
1134 unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val = 0;
1135 struct unw_frame_info info;
1136 struct switch_stack *sw;
1137 struct ia64_fpreg fpval;
1142 memset(&fpval, 0, sizeof(fpval));
1144 retval = verify_area(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs));
1149 pt = ia64_task_regs(child);
1150 sw = (struct switch_stack *) (child->thread.ksp + 16);
1151 unw_init_from_blocked_task(&info, child);
1152 if (unw_unwind_to_user(&info) < 0) {
1156 if (((unsigned long) ppr & 0x7) != 0) {
1157 dprintk("ptrace:unaligned register address %p\n", ppr);
1165 retval |= __get_user(pt->cr_iip, &ppr->cr_iip);
1166 retval |= __get_user(psr, &ppr->cr_ipsr);
1170 retval |= __get_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
1171 retval |= __get_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
1172 retval |= __get_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
1173 retval |= __get_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
1174 retval |= __get_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
1175 retval |= __get_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
1177 retval |= __get_user(ec, &ppr->ar[PT_AUR_EC]);
1178 retval |= __get_user(lc, &ppr->ar[PT_AUR_LC]);
1179 retval |= __get_user(rnat, &ppr->ar[PT_AUR_RNAT]);
1180 retval |= __get_user(bsp, &ppr->ar[PT_AUR_BSP]);
1181 retval |= __get_user(cfm, &ppr->cfm);
1185 retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long));
1186 retval |= __copy_from_user(&pt->r2, &ppr->gr[2], sizeof(long) * 2);
1190 for (i = 4; i < 8; i++) {
1191 retval |= __get_user(val, &ppr->gr[i]);
1192 if (unw_set_gr(&info, i, val, 0) < 0) /* NaT bit will be set via PT_NAT_BITS */
1198 retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4);
1202 retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 2);
1203 retval |= __copy_from_user(&pt->r14, &ppr->gr[14], sizeof(long));
1204 retval |= __copy_from_user(&pt->r15, &ppr->gr[15], sizeof(long));
1208 retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16);
1212 retval |= __get_user(pt->b0, &ppr->br[0]);
1216 for (i = 1; i < 6; i++) {
1217 retval |= __get_user(val, &ppr->br[i]);
1218 unw_set_br(&info, i, val);
1223 retval |= __get_user(pt->b6, &ppr->br[6]);
1224 retval |= __get_user(pt->b7, &ppr->br[7]);
1228 for (i = 2; i < 6; i++) {
1229 retval |= __copy_from_user(&fpval, &ppr->fr[i], sizeof(fpval));
1230 if (unw_set_fr(&info, i, fpval) < 0)
1236 retval |= __copy_from_user(&pt->f6, &ppr->fr[6], sizeof(ppr->fr[6]) * 6);
1238 /* fp scratch regs(12-15) */
1240 retval |= __copy_from_user(&sw->f12, &ppr->fr[12], sizeof(ppr->fr[12]) * 4);
1244 for (i = 16; i < 32; i++) {
1245 retval |= __copy_from_user(&fpval, &ppr->fr[i], sizeof(fpval));
1246 if (unw_set_fr(&info, i, fpval) < 0)
1252 ia64_sync_fph(child);
1253 retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32], sizeof(ppr->fr[32]) * 96);
1257 retval |= __get_user(pt->pr, &ppr->pr);
1261 retval |= __get_user(nat_bits, &ppr->nat);
1263 retval |= access_uarea(child, PT_CR_IPSR, &psr, 1);
1264 retval |= access_uarea(child, PT_AR_EC, &ec, 1);
1265 retval |= access_uarea(child, PT_AR_LC, &lc, 1);
1266 retval |= access_uarea(child, PT_AR_RNAT, &rnat, 1);
1267 retval |= access_uarea(child, PT_AR_BSP, &bsp, 1);
1268 retval |= access_uarea(child, PT_CFM, &cfm, 1);
1269 retval |= access_uarea(child, PT_NAT_BITS, &nat_bits, 1);
1271 ret = retval ? -EIO : 0;
1276 * Called by kernel/ptrace.c when detaching..
1278 * Make sure the single step bit is not set.
1281 ptrace_disable (struct task_struct *child)
1283 struct ia64_psr *child_psr = ia64_psr(ia64_task_regs(child));
1285 /* make sure the single step/take-branch tra bits are not set: */
1291 sys_ptrace (long request, pid_t pid, unsigned long addr, unsigned long data,
1292 long arg4, long arg5, long arg6, long arg7, long stack)
1294 struct pt_regs *pt, *regs = (struct pt_regs *) &stack;
1295 unsigned long urbs_end, peek_or_poke;
1296 struct task_struct *child;
1297 struct switch_stack *sw;
1302 if (request == PTRACE_TRACEME) {
1303 /* are we already being traced? */
1304 if (current->ptrace & PT_PTRACED)
1306 ret = security_ptrace(current->parent, current);
1309 current->ptrace |= PT_PTRACED;
1314 peek_or_poke = (request == PTRACE_PEEKTEXT || request == PTRACE_PEEKDATA
1315 || request == PTRACE_POKETEXT || request == PTRACE_POKEDATA);
1317 read_lock(&tasklist_lock);
1319 child = find_task_by_pid(pid);
1322 child = find_thread_for_addr(child, addr);
1323 get_task_struct(child);
1326 read_unlock(&tasklist_lock);
1329 if (!vx_check(vx_task_xid(child), VX_WATCH|VX_IDENT))
1333 if (pid == 1) /* no messing around with init! */
1336 if (request == PTRACE_ATTACH) {
1337 ret = ptrace_attach(child);
1341 ret = ptrace_check_attach(child, request == PTRACE_KILL);
1345 pt = ia64_task_regs(child);
1346 sw = (struct switch_stack *) (child->thread.ksp + 16);
1349 case PTRACE_PEEKTEXT:
1350 case PTRACE_PEEKDATA: /* read word at location addr */
1351 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1352 ret = ia64_peek(child, sw, urbs_end, addr, &data);
1355 regs->r8 = 0; /* ensure "ret" is not mistaken as an error code */
1359 case PTRACE_POKETEXT:
1360 case PTRACE_POKEDATA: /* write the word at location addr */
1361 urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
1362 ret = ia64_poke(child, sw, urbs_end, addr, data);
1365 case PTRACE_PEEKUSR: /* read the word at addr in the USER area */
1366 if (access_uarea(child, addr, &data, 0) < 0) {
1371 regs->r8 = 0; /* ensure "ret" is not mistaken as an error code */
1374 case PTRACE_POKEUSR: /* write the word at addr in the USER area */
1375 if (access_uarea(child, addr, &data, 1) < 0) {
1382 case PTRACE_OLD_GETSIGINFO: /* for backwards-compatibility */
1383 ret = ptrace_request(child, PTRACE_GETSIGINFO, addr, data);
1386 case PTRACE_OLD_SETSIGINFO: /* for backwards-compatibility */
1387 ret = ptrace_request(child, PTRACE_SETSIGINFO, addr, data);
1390 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
1391 case PTRACE_CONT: /* restart after signal. */
1395 if (request == PTRACE_SYSCALL)
1396 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1398 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1399 child->exit_code = data;
1401 /* make sure the single step/taken-branch trap bits are not set: */
1402 ia64_psr(pt)->ss = 0;
1403 ia64_psr(pt)->tb = 0;
1405 wake_up_process(child);
1411 * Make the child exit. Best I can do is send it a
1412 * sigkill. Perhaps it should be put in the status
1413 * that it wants to exit.
1415 if (child->exit_state == EXIT_ZOMBIE) /* already dead */
1417 child->exit_code = SIGKILL;
1419 /* make sure the single step/take-branch tra bits are not set: */
1420 ia64_psr(pt)->ss = 0;
1421 ia64_psr(pt)->tb = 0;
1423 wake_up_process(child);
1427 case PTRACE_SINGLESTEP: /* let child execute for one instruction */
1428 case PTRACE_SINGLEBLOCK:
1433 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
1434 if (request == PTRACE_SINGLESTEP) {
1435 ia64_psr(pt)->ss = 1;
1437 ia64_psr(pt)->tb = 1;
1439 child->exit_code = data;
1441 /* give it a chance to run. */
1442 wake_up_process(child);
1446 case PTRACE_DETACH: /* detach a process that was attached. */
1447 ret = ptrace_detach(child, data);
1450 case PTRACE_GETREGS:
1451 ret = ptrace_getregs(child, (struct pt_all_user_regs __user *) data);
1454 case PTRACE_SETREGS:
1455 ret = ptrace_setregs(child, (struct pt_all_user_regs __user *) data);
1459 ret = ptrace_request(child, request, addr, data);
1463 put_task_struct(child);
1471 syscall_trace (void)
1473 if (!test_thread_flag(TIF_SYSCALL_TRACE))
1475 if (!(current->ptrace & PT_PTRACED))
1478 * The 0x80 provides a way for the tracing parent to distinguish between a syscall
1479 * stop and SIGTRAP delivery.
1481 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0));
1484 * This isn't the same as continuing with a signal, but it will do for normal use.
1485 * strace only continues with a signal if the stopping signal is not SIGTRAP.
1488 if (current->exit_code) {
1489 send_sig(current->exit_code, current, 1);
1490 current->exit_code = 0;
1494 /* "asmlinkage" so the input arguments are preserved... */
1497 syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
1498 long arg4, long arg5, long arg6, long arg7, long stack)
1500 struct pt_regs *regs = (struct pt_regs *) &stack;
1503 if (unlikely(current->audit_context)) {
1504 if (IS_IA32_PROCESS(regs))
1507 syscall = regs->r15;
1509 audit_syscall_entry(current, syscall, arg0, arg1, arg2, arg3);
1512 if (test_thread_flag(TIF_SYSCALL_TRACE) && (current->ptrace & PT_PTRACED))
1516 /* "asmlinkage" so the input arguments are preserved... */
1519 syscall_trace_leave (long arg0, long arg1, long arg2, long arg3,
1520 long arg4, long arg5, long arg6, long arg7, long stack)
1522 if (unlikely(current->audit_context))
1523 audit_syscall_exit(current, ((struct pt_regs *) &stack)->r8);
1525 if (test_thread_flag(TIF_SYSCALL_TRACE) && (current->ptrace & PT_PTRACED))