2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
8 * Copyright (C) 1999 VA Linux Systems
9 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
11 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
12 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
13 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
14 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
15 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
16 * 01/07/99 S.Eranian added the support for command line argument
17 * 06/24/99 W.Drummond added boot_cpu_data.
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
23 #include <linux/acpi.h>
24 #include <linux/bootmem.h>
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/kernel.h>
28 #include <linux/reboot.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
31 #include <linux/string.h>
32 #include <linux/threads.h>
33 #include <linux/tty.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #include <linux/efi.h>
37 #include <linux/initrd.h>
40 #include <asm/machvec.h>
42 #include <asm/meminit.h>
44 #include <asm/patch.h>
45 #include <asm/pgtable.h>
46 #include <asm/processor.h>
48 #include <asm/sections.h>
49 #include <asm/serial.h>
51 #include <asm/system.h>
52 #include <asm/unistd.h>
54 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
55 # error "struct cpuinfo_ia64 too big!"
59 unsigned long __per_cpu_offset[NR_CPUS];
60 EXPORT_SYMBOL(__per_cpu_offset);
63 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
64 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
65 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
66 unsigned long ia64_cycles_per_usec;
67 struct ia64_boot_param *ia64_boot_param;
68 struct screen_info screen_info;
70 unsigned long ia64_max_cacheline_size;
71 unsigned long ia64_iobase; /* virtual address for I/O accesses */
72 EXPORT_SYMBOL(ia64_iobase);
73 struct io_space io_space[MAX_IO_SPACES];
74 EXPORT_SYMBOL(io_space);
75 unsigned int num_io_spaces;
77 unsigned char aux_device_present = 0xaa; /* XXX remove this when legacy I/O is gone */
80 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
81 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
82 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
83 * address of the second buffer must be aligned to (merge_mask+1) in order to be
84 * mergeable). By default, we assume there is no I/O MMU which can merge physically
85 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
88 unsigned long ia64_max_iommu_merge_mask = ~0UL;
89 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
91 #define COMMAND_LINE_SIZE 512
93 char saved_command_line[COMMAND_LINE_SIZE]; /* used in proc filesystem */
96 * We use a special marker for the end of memory and it uses the extra (+1) slot
98 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
103 * Filter incoming memory segments based on the primitive map created from the boot
104 * parameters. Segments contained in the map are removed from the memory ranges. A
105 * caller-specified function is called with the memory ranges that remain after filtering.
106 * This routine does not assume the incoming segments are sorted.
109 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
111 unsigned long range_start, range_end, prev_start;
112 void (*func)(unsigned long, unsigned long, int);
116 if (start == PAGE_OFFSET) {
117 printk(KERN_WARNING "warning: skipping physical page 0\n");
119 if (start >= end) return 0;
123 * lowest possible address(walker uses virtual)
125 prev_start = PAGE_OFFSET;
128 for (i = 0; i < num_rsvd_regions; ++i) {
129 range_start = max(start, prev_start);
130 range_end = min(end, rsvd_region[i].start);
132 if (range_start < range_end)
133 call_pernode_memory(__pa(range_start), range_end - range_start, func);
135 /* nothing more available in this segment */
136 if (range_end == end) return 0;
138 prev_start = rsvd_region[i].end;
140 /* end of memory marker allows full processing inside loop body */
145 sort_regions (struct rsvd_region *rsvd_region, int max)
149 /* simple bubble sorting */
151 for (j = 0; j < max; ++j) {
152 if (rsvd_region[j].start > rsvd_region[j+1].start) {
153 struct rsvd_region tmp;
154 tmp = rsvd_region[j];
155 rsvd_region[j] = rsvd_region[j + 1];
156 rsvd_region[j + 1] = tmp;
163 * reserve_memory - setup reserved memory areas
165 * Setup the reserved memory areas set aside for the boot parameters,
166 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
167 * see include/asm-ia64/meminit.h if you need to define more.
170 reserve_memory (void)
175 * none of the entries in this table overlap
177 rsvd_region[n].start = (unsigned long) ia64_boot_param;
178 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
181 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
182 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
185 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
186 rsvd_region[n].end = (rsvd_region[n].start
187 + strlen(__va(ia64_boot_param->command_line)) + 1);
190 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
191 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
194 #ifdef CONFIG_BLK_DEV_INITRD
195 if (ia64_boot_param->initrd_start) {
196 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
197 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
202 /* end of memory marker */
203 rsvd_region[n].start = ~0UL;
204 rsvd_region[n].end = ~0UL;
207 num_rsvd_regions = n;
209 sort_regions(rsvd_region, num_rsvd_regions);
213 * find_initrd - get initrd parameters from the boot parameter structure
215 * Grab the initrd start and end from the boot parameter struct given us by
221 #ifdef CONFIG_BLK_DEV_INITRD
222 if (ia64_boot_param->initrd_start) {
223 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
224 initrd_end = initrd_start+ia64_boot_param->initrd_size;
226 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
227 initrd_start, ia64_boot_param->initrd_size);
235 extern unsigned long ia64_iobase;
236 unsigned long phys_iobase;
239 * Set `iobase' to the appropriate address in region 6 (uncached access range).
241 * The EFI memory map is the "preferred" location to get the I/O port space base,
242 * rather the relying on AR.KR0. This should become more clear in future SAL
243 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
244 * found in the memory map.
246 phys_iobase = efi_get_iobase();
248 /* set AR.KR0 since this is all we use it for anyway */
249 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
251 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
252 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
254 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
256 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
258 /* setup legacy IO port space */
259 io_space[0].mmio_base = ia64_iobase;
260 io_space[0].sparse = 1;
264 #ifdef CONFIG_SERIAL_8250_CONSOLE
266 setup_serial_legacy (void)
268 struct uart_port port;
269 unsigned int i, iobase[] = {0x3f8, 0x2f8};
271 printk(KERN_INFO "Registering legacy COM ports for serial console\n");
272 memset(&port, 0, sizeof(port));
273 port.iotype = SERIAL_IO_PORT;
274 port.uartclk = BASE_BAUD * 16;
275 for (i = 0; i < ARRAY_SIZE(iobase); i++) {
277 port.iobase = iobase[i];
278 early_serial_setup(&port);
284 setup_arch (char **cmdline_p)
288 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
290 *cmdline_p = __va(ia64_boot_param->command_line);
291 strlcpy(saved_command_line, *cmdline_p, sizeof(saved_command_line));
296 #ifdef CONFIG_IA64_GENERIC
297 machvec_init(acpi_get_sysname());
300 #ifdef CONFIG_ACPI_BOOT
301 /* Initialize the ACPI boot-time table parser */
303 # ifdef CONFIG_ACPI_NUMA
308 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
310 #endif /* CONFIG_APCI_BOOT */
314 /* process SAL system table: */
315 ia64_sal_init(efi.sal_systab);
318 cpu_physical_id(0) = hard_smp_processor_id();
321 cpu_init(); /* initialize the bootstrap CPU */
323 #ifdef CONFIG_ACPI_BOOT
326 #ifdef CONFIG_SERIAL_8250_CONSOLE
327 #ifdef CONFIG_SERIAL_8250_HCDP
329 void setup_serial_hcdp(void *);
330 setup_serial_hcdp(efi.hcdp);
334 setup_serial_legacy();
338 # if defined(CONFIG_DUMMY_CONSOLE)
339 conswitchp = &dummy_con;
341 # if defined(CONFIG_VGA_CONSOLE)
343 * Non-legacy systems may route legacy VGA MMIO range to system
344 * memory. vga_con probes the MMIO hole, so memory looks like
345 * a VGA device to it. The EFI memory map can tell us if it's
346 * memory so we can avoid this problem.
348 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
349 conswitchp = &vga_con;
353 /* enable IA-64 Machine Check Abort Handling */
356 platform_setup(cmdline_p);
361 * Display cpu info for all cpu's.
364 show_cpuinfo (struct seq_file *m, void *v)
367 # define lpj c->loops_per_jiffy
368 # define cpunum c->cpu
370 # define lpj loops_per_jiffy
375 const char *feature_name;
377 { 1UL << 0, "branchlong" },
378 { 1UL << 1, "spontaneous deferral"},
379 { 1UL << 2, "16-byte atomic ops" }
381 char family[32], features[128], *cp, sep;
382 struct cpuinfo_ia64 *c = v;
389 case 0x07: memcpy(family, "Itanium", 8); break;
390 case 0x1f: memcpy(family, "Itanium 2", 10); break;
391 default: sprintf(family, "%u", c->family); break;
394 /* build the feature string: */
395 memcpy(features, " standard", 10);
398 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
399 if (mask & feature_bits[i].mask) {
404 strcpy(cp, feature_bits[i].feature_name);
405 cp += strlen(feature_bits[i].feature_name);
406 mask &= ~feature_bits[i].mask;
410 /* print unknown features as a hex value: */
413 sprintf(cp, " 0x%lx", mask);
424 "features :%s\n" /* don't change this---it _is_ right! */
427 "cpu MHz : %lu.%06lu\n"
428 "itc MHz : %lu.%06lu\n"
429 "BogoMIPS : %lu.%02lu\n\n",
430 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
431 features, c->ppn, c->number,
432 c->proc_freq / 1000000, c->proc_freq % 1000000,
433 c->itc_freq / 1000000, c->itc_freq % 1000000,
434 lpj*HZ/500000, (lpj*HZ/5000) % 100);
439 c_start (struct seq_file *m, loff_t *pos)
442 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
445 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
449 c_next (struct seq_file *m, void *v, loff_t *pos)
452 return c_start(m, pos);
456 c_stop (struct seq_file *m, void *v)
460 struct seq_operations cpuinfo_op = {
468 identify_cpu (struct cpuinfo_ia64 *c)
471 unsigned long bits[5];
477 u64 ppn; /* processor serial number */
481 unsigned revision : 8;
484 unsigned archrev : 8;
485 unsigned reserved : 24;
491 pal_vm_info_1_u_t vm1;
492 pal_vm_info_2_u_t vm2;
494 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
497 for (i = 0; i < 5; ++i)
498 cpuid.bits[i] = ia64_get_cpuid(i);
500 memcpy(c->vendor, cpuid.field.vendor, 16);
502 c->cpu = smp_processor_id();
504 c->ppn = cpuid.field.ppn;
505 c->number = cpuid.field.number;
506 c->revision = cpuid.field.revision;
507 c->model = cpuid.field.model;
508 c->family = cpuid.field.family;
509 c->archrev = cpuid.field.archrev;
510 c->features = cpuid.field.features;
512 status = ia64_pal_vm_summary(&vm1, &vm2);
513 if (status == PAL_STATUS_SUCCESS) {
514 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
515 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
517 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
518 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
522 setup_per_cpu_areas (void)
524 /* start_kernel() requires this... */
528 get_max_cacheline_size (void)
530 unsigned long line_size, max = 1;
531 u64 l, levels, unique_caches;
532 pal_cache_config_info_t cci;
535 status = ia64_pal_cache_summary(&levels, &unique_caches);
537 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
538 __FUNCTION__, status);
539 max = SMP_CACHE_BYTES;
543 for (l = 0; l < levels; ++l) {
544 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
548 "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
549 __FUNCTION__, l, status);
550 max = SMP_CACHE_BYTES;
552 line_size = 1 << cci.pcci_line_size;
557 if (max > ia64_max_cacheline_size)
558 ia64_max_cacheline_size = max;
562 * cpu_init() initializes state that is per-CPU. This function acts
563 * as a 'CPU state barrier', nothing should get across.
568 extern void __devinit ia64_mmu_init (void *);
569 unsigned long num_phys_stacked;
570 pal_vm_info_2_u_t vmi;
571 unsigned int max_ctx;
572 struct cpuinfo_ia64 *cpu_info;
575 cpu_data = per_cpu_init();
577 get_max_cacheline_size();
580 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
581 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
582 * depends on the data returned by identify_cpu(). We break the dependency by
583 * accessing cpu_data() through the canonical per-CPU address.
585 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
586 identify_cpu(cpu_info);
588 #ifdef CONFIG_MCKINLEY
590 # define FEATURE_SET 16
591 struct ia64_pal_retval iprv;
593 if (cpu_info->family == 0x1f) {
594 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
595 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
596 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
597 (iprv.v1 | 0x80), FEATURE_SET, 0);
602 /* Clear the stack memory reserved for pt_regs: */
603 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
605 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
608 * Initialize default control register to defer all speculative faults. The
609 * kernel MUST NOT depend on a particular setting of these bits (in other words,
610 * the kernel must have recovery code for all speculative accesses). Turn on
611 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
612 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
615 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
616 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
617 atomic_inc(&init_mm.mm_count);
618 current->active_mm = &init_mm;
622 ia64_mmu_init(ia64_imva(cpu_data));
624 #ifdef CONFIG_IA32_SUPPORT
628 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
631 /* disable all local interrupt sources: */
632 ia64_set_itv(1 << 16);
633 ia64_set_lrr0(1 << 16);
634 ia64_set_lrr1(1 << 16);
635 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
636 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
638 /* clear TPR & XTP to enable all interrupt classes: */
639 ia64_setreg(_IA64_REG_CR_TPR, 0);
644 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
645 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
646 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
648 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
649 max_ctx = (1U << 15) - 1; /* use architected minimum */
651 while (max_ctx < ia64_ctx.max_ctx) {
652 unsigned int old = ia64_ctx.max_ctx;
653 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
657 if (ia64_pal_rse_info(&num_phys_stacked, 0) != 0) {
658 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
660 num_phys_stacked = 96;
662 /* size of physical stacked register partition plus 8 bytes: */
663 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
670 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
671 (unsigned long) __end___mckinley_e9_bundles);