2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * Copyright (C) 2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn_helgaas@hp.com>
10 * Note: Above list of copyright holders is incomplete...
12 #include <linux/config.h>
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/smp_lock.h>
22 #include <linux/spinlock.h>
24 #include <asm/machvec.h>
26 #include <asm/segment.h>
27 #include <asm/system.h>
37 #include <asm/hw_irq.h>
44 #define DBG(x...) printk(x)
49 struct pci_fixup pcibios_fixups[1];
52 * Low-level SAL-based PCI configuration access functions. Note that SAL
53 * calls are already serialized (via sal_lock), so we don't need another
54 * synchronization mechanism here.
57 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
58 ((u64)(seg << 24) | (u64)(bus << 16) | \
59 (u64)(devfn << 8) | (u64)(reg))
61 /* SAL 3.2 adds support for extended config space. */
63 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
64 ((u64)(seg << 28) | (u64)(bus << 20) | \
65 (u64)(devfn << 12) | (u64)(reg))
68 pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
70 u64 addr, mode, data = 0;
73 if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 4095))
76 if ((seg | reg) <= 255) {
77 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
80 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
83 result = ia64_sal_pci_config_read(addr, mode, len, &data);
91 pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
95 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
98 if ((seg | reg) <= 255) {
99 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
102 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
105 return ia64_sal_pci_config_write(addr, mode, len, value);
108 static struct pci_raw_ops pci_sal_ops = {
109 .read = pci_sal_read,
110 .write = pci_sal_write
113 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
116 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
118 return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
119 devfn, where, size, value);
123 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
125 return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
126 devfn, where, size, value);
129 static struct pci_ops pci_root_ops = {
137 if (!acpi_pci_irq_init())
138 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
140 printk(KERN_WARNING "PCI: Invalid ACPI-PCI IRQ routing table\n");
144 subsys_initcall(pci_acpi_init);
146 /* Called by ACPI when it finds a new root bus. */
148 static struct pci_controller * __devinit
149 alloc_pci_controller (int seg)
151 struct pci_controller *controller;
153 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
157 memset(controller, 0, sizeof(*controller));
158 controller->segment = seg;
163 alloc_resource (char *name, struct resource *root, unsigned long start, unsigned long end,
166 struct resource *res;
168 res = kmalloc(sizeof(*res), GFP_KERNEL);
172 memset(res, 0, sizeof(*res));
178 if (insert_resource(root, res)) {
187 add_io_space (struct acpi_resource_address64 *addr)
193 if (addr->address_translation_offset == 0)
194 return IO_SPACE_BASE(0); /* part of legacy IO space */
196 if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
199 offset = (u64) ioremap(addr->address_translation_offset, 0);
200 for (i = 0; i < num_io_spaces; i++)
201 if (io_space[i].mmio_base == offset &&
202 io_space[i].sparse == sparse)
203 return IO_SPACE_BASE(i);
205 if (num_io_spaces == MAX_IO_SPACES) {
206 printk("Too many IO port spaces\n");
211 io_space[i].mmio_base = offset;
212 io_space[i].sparse = sparse;
214 return IO_SPACE_BASE(i);
217 static acpi_status __devinit
218 count_window (struct acpi_resource *resource, void *data)
220 unsigned int *windows = (unsigned int *) data;
221 struct acpi_resource_address64 addr;
224 status = acpi_resource_to_address64(resource, &addr);
225 if (ACPI_SUCCESS(status))
226 if (addr.resource_type == ACPI_MEMORY_RANGE ||
227 addr.resource_type == ACPI_IO_RANGE)
233 struct pci_root_info {
234 struct pci_controller *controller;
238 static acpi_status __devinit
239 add_window (struct acpi_resource *res, void *data)
241 struct pci_root_info *info = (struct pci_root_info *) data;
242 struct pci_window *window;
243 struct acpi_resource_address64 addr;
245 unsigned long flags, offset = 0;
246 struct resource *root;
248 status = acpi_resource_to_address64(res, &addr);
249 if (ACPI_SUCCESS(status)) {
250 if (!addr.address_length)
253 if (addr.resource_type == ACPI_MEMORY_RANGE) {
254 flags = IORESOURCE_MEM;
255 root = &iomem_resource;
256 offset = addr.address_translation_offset;
257 } else if (addr.resource_type == ACPI_IO_RANGE) {
258 flags = IORESOURCE_IO;
259 root = &ioport_resource;
260 offset = add_io_space(&addr);
266 window = &info->controller->window[info->controller->windows++];
267 window->resource.flags |= flags;
268 window->resource.start = addr.min_address_range;
269 window->resource.end = addr.max_address_range;
270 window->offset = offset;
272 if (alloc_resource(info->name, root, addr.min_address_range + offset,
273 addr.max_address_range + offset, flags))
274 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
275 addr.min_address_range + offset, addr.max_address_range + offset,
276 root->name, info->name);
282 struct pci_bus * __devinit
283 pci_acpi_scan_root (struct acpi_device *device, int domain, int bus)
285 struct pci_root_info info;
286 struct pci_controller *controller;
287 unsigned int windows = 0;
290 controller = alloc_pci_controller(domain);
294 controller->acpi_handle = device->handle;
296 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, &windows);
297 controller->window = kmalloc(sizeof(*controller->window) * windows, GFP_KERNEL);
298 if (!controller->window)
301 name = kmalloc(16, GFP_KERNEL);
305 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
306 info.controller = controller;
308 acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, &info);
310 return pci_scan_bus(bus, &pci_root_ops, controller);
313 kfree(controller->window);
321 pcibios_fixup_device_resources (struct pci_dev *dev, struct pci_bus *bus)
323 struct pci_controller *controller = PCI_CONTROLLER(dev);
324 struct pci_window *window;
327 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
328 if (!dev->resource[i].start)
331 #define contains(win, res) ((res)->start >= (win)->start && \
332 (res)->end <= (win)->end)
334 for (j = 0; j < controller->windows; j++) {
335 window = &controller->window[j];
336 if (((dev->resource[i].flags & IORESOURCE_MEM &&
337 window->resource.flags & IORESOURCE_MEM) ||
338 (dev->resource[i].flags & IORESOURCE_IO &&
339 window->resource.flags & IORESOURCE_IO)) &&
340 contains(&window->resource, &dev->resource[i])) {
341 dev->resource[i].start += window->offset;
342 dev->resource[i].end += window->offset;
345 pci_claim_resource(dev, i);
350 * Called after each bus is probed, but before its children are examined.
353 pcibios_fixup_bus (struct pci_bus *b)
355 struct list_head *ln;
357 for (ln = b->devices.next; ln != &b->devices; ln = ln->next)
358 pcibios_fixup_device_resources(pci_dev_b(ln), b);
364 pcibios_update_irq (struct pci_dev *dev, int irq)
366 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
368 /* ??? FIXME -- record old value for shutdown. */
372 pcibios_enable_resources (struct pci_dev *dev, int mask)
381 pci_read_config_word(dev, PCI_COMMAND, &cmd);
383 for (idx=0; idx<6; idx++) {
384 /* Only set up the desired resources. */
385 if (!(mask & (1 << idx)))
388 r = &dev->resource[idx];
389 if (!r->start && r->end) {
391 "PCI: Device %s not available because of resource collisions\n",
395 if (r->flags & IORESOURCE_IO)
396 cmd |= PCI_COMMAND_IO;
397 if (r->flags & IORESOURCE_MEM)
398 cmd |= PCI_COMMAND_MEMORY;
400 if (dev->resource[PCI_ROM_RESOURCE].start)
401 cmd |= PCI_COMMAND_MEMORY;
402 if (cmd != old_cmd) {
403 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
404 pci_write_config_word(dev, PCI_COMMAND, cmd);
410 pcibios_enable_device (struct pci_dev *dev, int mask)
414 ret = pcibios_enable_resources(dev, mask);
418 return acpi_pci_irq_enable(dev);
422 pcibios_align_resource (void *data, struct resource *res,
423 unsigned long size, unsigned long align)
428 * PCI BIOS setup, always defaults to SAL interface
431 pcibios_setup (char *str)
437 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
438 enum pci_mmap_state mmap_state, int write_combine)
441 * I/O space cannot be accessed via normal processor loads and stores on this
444 if (mmap_state == pci_mmap_io)
446 * XXX we could relax this for I/O spaces for which ACPI indicates that
447 * the space is 1-to-1 mapped. But at the moment, we don't support
448 * multiple PCI address spaces and the legacy I/O space is not 1-to-1
449 * mapped, so this is moot.
454 * Leave vm_pgoff as-is, the PCI space address is the physical address on this
457 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
460 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
462 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
464 if (remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
465 vma->vm_end - vma->vm_start, vma->vm_page_prot))
472 * pci_cacheline_size - determine cacheline size for PCI devices
475 * We want to use the line-size of the outer-most cache. We assume
476 * that this line-size is the same for all CPUs.
478 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
480 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
483 pci_cacheline_size (void)
485 u64 levels, unique_caches;
487 pal_cache_config_info_t cci;
488 static u8 cacheline_size;
491 return cacheline_size;
493 status = ia64_pal_cache_summary(&levels, &unique_caches);
495 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
496 __FUNCTION__, status);
497 return SMP_CACHE_BYTES;
500 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
503 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
504 __FUNCTION__, status);
505 return SMP_CACHE_BYTES;
507 cacheline_size = 1 << cci.pcci_line_size;
508 return cacheline_size;
512 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
513 * @dev: the PCI device for which MWI is enabled
515 * For ia64, we can get the cacheline sizes from PAL.
517 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
520 pcibios_prep_mwi (struct pci_dev *dev)
522 unsigned long desired_linesize, current_linesize;
526 desired_linesize = pci_cacheline_size();
528 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
529 current_linesize = 4 * pci_linesize;
530 if (desired_linesize != current_linesize) {
531 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
532 pci_name(dev), current_linesize);
533 if (current_linesize > desired_linesize) {
534 printk(" expected %lu bytes instead\n", desired_linesize);
537 printk(" correcting to %lu\n", desired_linesize);
538 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
544 int pci_vector_resources(int last, int nr_released)
546 int count = nr_released;
548 count += (IA64_LAST_DEVICE_VECTOR - last);