2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * Copyright (C) 2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn_helgaas@hp.com>
10 * Note: Above list of copyright holders is incomplete...
12 #include <linux/config.h>
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/smp_lock.h>
22 #include <linux/spinlock.h>
24 #include <asm/machvec.h>
26 #include <asm/segment.h>
27 #include <asm/system.h>
37 #include <asm/hw_irq.h>
44 #define DBG(x...) printk(x)
49 static int pci_routeirq;
52 * Low-level SAL-based PCI configuration access functions. Note that SAL
53 * calls are already serialized (via sal_lock), so we don't need another
54 * synchronization mechanism here.
57 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
58 ((u64)(seg << 24) | (u64)(bus << 16) | \
59 (u64)(devfn << 8) | (u64)(reg))
61 /* SAL 3.2 adds support for extended config space. */
63 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
64 ((u64)(seg << 28) | (u64)(bus << 20) | \
65 (u64)(devfn << 12) | (u64)(reg))
68 pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
70 u64 addr, mode, data = 0;
73 if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 4095))
76 if ((seg | reg) <= 255) {
77 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
80 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
83 result = ia64_sal_pci_config_read(addr, mode, len, &data);
91 pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
95 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
98 if ((seg | reg) <= 255) {
99 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
102 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
105 return ia64_sal_pci_config_write(addr, mode, len, value);
108 static struct pci_raw_ops pci_sal_ops = {
109 .read = pci_sal_read,
110 .write = pci_sal_write
113 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
116 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
118 return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
119 devfn, where, size, value);
123 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
125 return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
126 devfn, where, size, value);
129 struct pci_ops pci_root_ops = {
137 struct pci_dev *dev = NULL;
139 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
142 extern acpi_status acpi_map_iosapic (acpi_handle, u32, void*, void**);
144 acpi_get_devices(NULL, acpi_map_iosapic, NULL, NULL);
149 * PCI IRQ routing is set up by pci_enable_device(), but we
150 * also do it here in case there are still broken drivers that
151 * don't use pci_enable_device().
153 printk(KERN_INFO "** Routing PCI interrupts for all devices because \"pci=routeirq\"\n");
154 printk(KERN_INFO "** was specified. If this was required to make a driver work,\n");
155 printk(KERN_INFO "** please email the output of \"lspci\" to bjorn.helgaas@hp.com\n");
156 printk(KERN_INFO "** so I can fix the driver.\n");
157 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
158 acpi_pci_irq_enable(dev);
160 printk(KERN_INFO "** PCI interrupts are no longer routed automatically. If this\n");
161 printk(KERN_INFO "** causes a device to stop working, it is probably because the\n");
162 printk(KERN_INFO "** driver failed to call pci_enable_device(). As a temporary\n");
163 printk(KERN_INFO "** workaround, the \"pci=routeirq\" argument restores the old\n");
164 printk(KERN_INFO "** behavior. If this argument makes the device work again,\n");
165 printk(KERN_INFO "** please email the output of \"lspci\" to bjorn.helgaas@hp.com\n");
166 printk(KERN_INFO "** so I can fix the driver.\n");
172 subsys_initcall(pci_acpi_init);
174 /* Called by ACPI when it finds a new root bus. */
176 static struct pci_controller * __devinit
177 alloc_pci_controller (int seg)
179 struct pci_controller *controller;
181 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
185 memset(controller, 0, sizeof(*controller));
186 controller->segment = seg;
191 alloc_resource (char *name, struct resource *root, unsigned long start, unsigned long end,
194 struct resource *res;
196 res = kmalloc(sizeof(*res), GFP_KERNEL);
200 memset(res, 0, sizeof(*res));
206 if (insert_resource(root, res)) {
215 add_io_space (struct acpi_resource_address64 *addr)
221 if (addr->address_translation_offset == 0)
222 return IO_SPACE_BASE(0); /* part of legacy IO space */
224 if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
227 offset = (u64) ioremap(addr->address_translation_offset, 0);
228 for (i = 0; i < num_io_spaces; i++)
229 if (io_space[i].mmio_base == offset &&
230 io_space[i].sparse == sparse)
231 return IO_SPACE_BASE(i);
233 if (num_io_spaces == MAX_IO_SPACES) {
234 printk("Too many IO port spaces\n");
239 io_space[i].mmio_base = offset;
240 io_space[i].sparse = sparse;
242 return IO_SPACE_BASE(i);
245 static acpi_status __devinit
246 count_window (struct acpi_resource *resource, void *data)
248 unsigned int *windows = (unsigned int *) data;
249 struct acpi_resource_address64 addr;
252 status = acpi_resource_to_address64(resource, &addr);
253 if (ACPI_SUCCESS(status))
254 if (addr.resource_type == ACPI_MEMORY_RANGE ||
255 addr.resource_type == ACPI_IO_RANGE)
261 struct pci_root_info {
262 struct pci_controller *controller;
266 static acpi_status __devinit
267 add_window (struct acpi_resource *res, void *data)
269 struct pci_root_info *info = (struct pci_root_info *) data;
270 struct pci_window *window;
271 struct acpi_resource_address64 addr;
273 unsigned long flags, offset = 0;
274 struct resource *root;
276 status = acpi_resource_to_address64(res, &addr);
277 if (ACPI_SUCCESS(status)) {
278 if (!addr.address_length)
281 if (addr.resource_type == ACPI_MEMORY_RANGE) {
282 flags = IORESOURCE_MEM;
283 root = &iomem_resource;
284 offset = addr.address_translation_offset;
285 } else if (addr.resource_type == ACPI_IO_RANGE) {
286 flags = IORESOURCE_IO;
287 root = &ioport_resource;
288 offset = add_io_space(&addr);
294 window = &info->controller->window[info->controller->windows++];
295 window->resource.flags = flags;
296 window->resource.start = addr.min_address_range;
297 window->resource.end = addr.max_address_range;
298 window->offset = offset;
300 if (alloc_resource(info->name, root, addr.min_address_range + offset,
301 addr.max_address_range + offset, flags))
302 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
303 addr.min_address_range + offset, addr.max_address_range + offset,
304 root->name, info->name);
310 struct pci_bus * __devinit
311 pci_acpi_scan_root (struct acpi_device *device, int domain, int bus)
313 struct pci_root_info info;
314 struct pci_controller *controller;
315 unsigned int windows = 0;
318 controller = alloc_pci_controller(domain);
322 controller->acpi_handle = device->handle;
324 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, &windows);
325 controller->window = kmalloc(sizeof(*controller->window) * windows, GFP_KERNEL);
326 if (!controller->window)
329 name = kmalloc(16, GFP_KERNEL);
333 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
334 info.controller = controller;
336 acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, &info);
338 return pci_scan_bus(bus, &pci_root_ops, controller);
341 kfree(controller->window);
348 void pcibios_resource_to_bus(struct pci_dev *dev,
349 struct pci_bus_region *region, struct resource *res)
351 struct pci_controller *controller = PCI_CONTROLLER(dev);
352 unsigned long offset = 0;
355 for (i = 0; i < controller->windows; i++) {
356 struct pci_window *window = &controller->window[i];
357 if (!(window->resource.flags & res->flags))
359 if (window->resource.start > res->start - window->offset)
361 if (window->resource.end < res->end - window->offset)
363 offset = window->offset;
367 region->start = res->start - offset;
368 region->end = res->end - offset;
371 void pcibios_bus_to_resource(struct pci_dev *dev,
372 struct resource *res, struct pci_bus_region *region)
374 struct pci_controller *controller = PCI_CONTROLLER(dev);
375 unsigned long offset = 0;
378 for (i = 0; i < controller->windows; i++) {
379 struct pci_window *window = &controller->window[i];
380 if (!(window->resource.flags & res->flags))
382 if (window->resource.start > region->start)
384 if (window->resource.end < region->end)
386 offset = window->offset;
390 res->start = region->start + offset;
391 res->end = region->end + offset;
394 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
396 struct pci_bus_region region;
398 int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
399 PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
401 for (i = 0; i < limit; i++) {
402 if (!dev->resource[i].flags)
404 region.start = dev->resource[i].start;
405 region.end = dev->resource[i].end;
406 pcibios_bus_to_resource(dev, &dev->resource[i], ®ion);
407 pci_claim_resource(dev, i);
412 * Called after each bus is probed, but before its children are examined.
415 pcibios_fixup_bus (struct pci_bus *b)
419 list_for_each_entry(dev, &b->devices, bus_list)
420 pcibios_fixup_device_resources(dev);
426 pcibios_update_irq (struct pci_dev *dev, int irq)
428 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
430 /* ??? FIXME -- record old value for shutdown. */
434 pcibios_enable_resources (struct pci_dev *dev, int mask)
443 pci_read_config_word(dev, PCI_COMMAND, &cmd);
445 for (idx=0; idx<6; idx++) {
446 /* Only set up the desired resources. */
447 if (!(mask & (1 << idx)))
450 r = &dev->resource[idx];
451 if (!r->start && r->end) {
453 "PCI: Device %s not available because of resource collisions\n",
457 if (r->flags & IORESOURCE_IO)
458 cmd |= PCI_COMMAND_IO;
459 if (r->flags & IORESOURCE_MEM)
460 cmd |= PCI_COMMAND_MEMORY;
462 if (dev->resource[PCI_ROM_RESOURCE].start)
463 cmd |= PCI_COMMAND_MEMORY;
464 if (cmd != old_cmd) {
465 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
466 pci_write_config_word(dev, PCI_COMMAND, cmd);
472 pcibios_enable_device (struct pci_dev *dev, int mask)
476 ret = pcibios_enable_resources(dev, mask);
480 return acpi_pci_irq_enable(dev);
484 pcibios_align_resource (void *data, struct resource *res,
485 unsigned long size, unsigned long align)
490 * PCI BIOS setup, always defaults to SAL interface
493 pcibios_setup (char *str)
495 if (!strcmp(str, "routeirq"))
501 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
502 enum pci_mmap_state mmap_state, int write_combine)
505 * I/O space cannot be accessed via normal processor loads and
506 * stores on this platform.
508 if (mmap_state == pci_mmap_io)
510 * XXX we could relax this for I/O spaces for which ACPI
511 * indicates that the space is 1-to-1 mapped. But at the
512 * moment, we don't support multiple PCI address spaces and
513 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
518 * Leave vm_pgoff as-is, the PCI space address is the physical
519 * address on this platform.
521 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
524 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
526 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
528 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
529 vma->vm_end - vma->vm_start, vma->vm_page_prot))
536 * pci_cacheline_size - determine cacheline size for PCI devices
539 * We want to use the line-size of the outer-most cache. We assume
540 * that this line-size is the same for all CPUs.
542 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
544 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
547 pci_cacheline_size (void)
549 u64 levels, unique_caches;
551 pal_cache_config_info_t cci;
552 static u8 cacheline_size;
555 return cacheline_size;
557 status = ia64_pal_cache_summary(&levels, &unique_caches);
559 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
560 __FUNCTION__, status);
561 return SMP_CACHE_BYTES;
564 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
567 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
568 __FUNCTION__, status);
569 return SMP_CACHE_BYTES;
571 cacheline_size = 1 << cci.pcci_line_size;
572 return cacheline_size;
576 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
577 * @dev: the PCI device for which MWI is enabled
579 * For ia64, we can get the cacheline sizes from PAL.
581 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
584 pcibios_prep_mwi (struct pci_dev *dev)
586 unsigned long desired_linesize, current_linesize;
590 desired_linesize = pci_cacheline_size();
592 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
593 current_linesize = 4 * pci_linesize;
594 if (desired_linesize != current_linesize) {
595 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
596 pci_name(dev), current_linesize);
597 if (current_linesize > desired_linesize) {
598 printk(" expected %lu bytes instead\n", desired_linesize);
601 printk(" correcting to %lu\n", desired_linesize);
602 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
608 int pci_vector_resources(int last, int nr_released)
610 int count = nr_released;
612 count += (IA64_LAST_DEVICE_VECTOR - last);