2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
9 #include <linux/types.h>
10 #include <asm/sn/sgi.h>
11 #include <asm/sn/sn_cpuid.h>
12 #include <asm/uaccess.h>
13 #include <asm/sn/iograph.h>
14 #include <asm/sn/pci/pciio.h>
15 #include <asm/sn/pci/pcibr.h>
16 #include <asm/sn/pci/pcibr_private.h>
17 #include <asm/sn/pci/pci_defs.h>
18 #include <asm/sn/sn_private.h>
19 #include <asm/sn/sn_sal.h>
21 extern pcibr_info_t pcibr_info_get(vertex_hdl_t);
22 extern int pcibr_widget_to_bus(vertex_hdl_t pcibr_vhdl);
23 extern pcibr_info_t pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
24 extern int pcibr_slot_initial_rrb_alloc(vertex_hdl_t,pciio_slot_t);
25 extern int pcibr_pcix_rbars_calc(pcibr_soft_t);
27 extern char *pci_space[];
29 int pcibr_slot_info_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
30 int pcibr_slot_info_free(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
31 int pcibr_slot_addr_space_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
32 int pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft, pciio_slot_t slot);
33 int pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
34 int pcibr_slot_guest_info_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
35 int pcibr_slot_call_device_attach(vertex_hdl_t pcibr_vhdl,
36 pciio_slot_t slot, int drv_flags);
37 int pcibr_slot_call_device_detach(vertex_hdl_t pcibr_vhdl,
38 pciio_slot_t slot, int drv_flags);
39 int pcibr_slot_detach(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot,
40 int drv_flags, char *l1_msg, int *sub_errorp);
41 static int pcibr_probe_slot(pcibr_soft_t, cfg_p, unsigned int *);
42 static int pcibr_probe_work(pcibr_soft_t pcibr_soft, void *addr, int len, void *valp);
43 void pcibr_device_info_free(vertex_hdl_t, pciio_slot_t);
44 iopaddr_t pcibr_bus_addr_alloc(pcibr_soft_t, pciio_win_info_t,
45 pciio_space_t, int, int, int);
46 void pcibr_bus_addr_free(pciio_win_info_t);
47 cfg_p pcibr_find_capability(cfg_p, unsigned);
48 extern uint64_t do_pcibr_config_get(cfg_p, unsigned, unsigned);
49 void do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
50 int pcibr_slot_pwr(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot, int up, char *err_msg);
54 * PCI-X Max Outstanding Split Transactions translation array and Max Memory
55 * Read Byte Count translation array, as defined in the PCI-X Specification.
56 * Section 7.2.3 & 7.2.4 of PCI-X Specification - rev 1.0
58 #define MAX_SPLIT_TABLE 8
59 #define MAX_READCNT_TABLE 4
60 int max_splittrans_to_numbuf[MAX_SPLIT_TABLE] = {1, 2, 3, 4, 8, 12, 16, 32};
61 int max_readcount_to_bufsize[MAX_READCNT_TABLE] = {512, 1024, 2048, 4096 };
63 #ifdef CONFIG_HOTPLUG_PCI_SGI
66 * PCI slot manipulation errors from the system controller, and their
67 * associated descriptions
69 #define SYSCTL_REQERR_BASE (-106000)
70 #define SYSCTL_PCI_ERROR_BASE (SYSCTL_REQERR_BASE - 100)
71 #define SYSCTL_PCIX_ERROR_BASE (SYSCTL_REQERR_BASE - 3000)
73 struct sysctl_pci_error_s {
78 } sysctl_pci_errors[] = {
80 #define SYSCTL_PCI_UNINITIALIZED (SYSCTL_PCI_ERROR_BASE - 0)
81 { SYSCTL_PCI_UNINITIALIZED, "module not initialized" },
83 #define SYSCTL_PCI_UNSUPPORTED_BUS (SYSCTL_PCI_ERROR_BASE - 1)
84 { SYSCTL_PCI_UNSUPPORTED_BUS, "unsupported bus" },
86 #define SYSCTL_PCI_UNSUPPORTED_SLOT (SYSCTL_PCI_ERROR_BASE - 2)
87 { SYSCTL_PCI_UNSUPPORTED_SLOT, "unsupported slot" },
89 #define SYSCTL_PCI_POWER_NOT_OKAY (SYSCTL_PCI_ERROR_BASE - 3)
90 { SYSCTL_PCI_POWER_NOT_OKAY, "slot power not okay" },
92 #define SYSCTL_PCI_CARD_NOT_PRESENT (SYSCTL_PCI_ERROR_BASE - 4)
93 { SYSCTL_PCI_CARD_NOT_PRESENT, "card not present" },
95 #define SYSCTL_PCI_POWER_LIMIT (SYSCTL_PCI_ERROR_BASE - 5)
96 { SYSCTL_PCI_POWER_LIMIT, "power limit reached - some cards not powered up" },
98 #define SYSCTL_PCI_33MHZ_ON_66MHZ (SYSCTL_PCI_ERROR_BASE - 6)
99 { SYSCTL_PCI_33MHZ_ON_66MHZ, "cannot add a 33 MHz card to an active 66 MHz bus" },
101 #define SYSCTL_PCI_INVALID_ORDER (SYSCTL_PCI_ERROR_BASE - 7)
102 { SYSCTL_PCI_INVALID_ORDER, "invalid reset order" },
104 #define SYSCTL_PCI_DOWN_33MHZ (SYSCTL_PCI_ERROR_BASE - 8)
105 { SYSCTL_PCI_DOWN_33MHZ, "cannot power down a 33 MHz card on an active bus" },
107 #define SYSCTL_PCI_RESET_33MHZ (SYSCTL_PCI_ERROR_BASE - 9)
108 { SYSCTL_PCI_RESET_33MHZ, "cannot reset a 33 MHz card on an active bus" },
110 #define SYSCTL_PCI_SLOT_NOT_UP (SYSCTL_PCI_ERROR_BASE - 10)
111 { SYSCTL_PCI_SLOT_NOT_UP, "cannot reset a slot that is not powered up" },
113 #define SYSCTL_PCIX_UNINITIALIZED (SYSCTL_PCIX_ERROR_BASE - 0)
114 { SYSCTL_PCIX_UNINITIALIZED, "module not initialized" },
116 #define SYSCTL_PCIX_UNSUPPORTED_BUS (SYSCTL_PCIX_ERROR_BASE - 1)
117 { SYSCTL_PCIX_UNSUPPORTED_BUS, "unsupported bus" },
119 #define SYSCTL_PCIX_UNSUPPORTED_SLOT (SYSCTL_PCIX_ERROR_BASE - 2)
120 { SYSCTL_PCIX_UNSUPPORTED_SLOT, "unsupported slot" },
122 #define SYSCTL_PCIX_POWER_NOT_OKAY (SYSCTL_PCIX_ERROR_BASE - 3)
123 { SYSCTL_PCIX_POWER_NOT_OKAY, "slot power not okay" },
125 #define SYSCTL_PCIX_CARD_NOT_PRESENT (SYSCTL_PCIX_ERROR_BASE - 4)
126 { SYSCTL_PCIX_CARD_NOT_PRESENT, "card not present" },
128 #define SYSCTL_PCIX_POWER_LIMIT (SYSCTL_PCIX_ERROR_BASE - 5)
129 { SYSCTL_PCIX_POWER_LIMIT, "power limit reached - some cards not powered up" },
131 #define SYSCTL_PCIX_33MHZ_ON_66MHZ (SYSCTL_PCIX_ERROR_BASE - 6)
132 { SYSCTL_PCIX_33MHZ_ON_66MHZ, "cannot add a 33 MHz card to an active 66 MHz bus" },
134 #define SYSCTL_PCIX_PCI_ON_PCIX (SYSCTL_PCIX_ERROR_BASE - 7)
135 { SYSCTL_PCIX_PCI_ON_PCIX, "cannot add a PCI card to an active PCIX bus" },
137 #define SYSCTL_PCIX_ANYTHING_ON_133MHZ (SYSCTL_PCIX_ERROR_BASE - 8)
138 { SYSCTL_PCIX_ANYTHING_ON_133MHZ, "cannot add any card to an active 133MHz PCIX bus" },
140 #define SYSCTL_PCIX_X66MHZ_ON_X100MHZ (SYSCTL_PCIX_ERROR_BASE - 9)
141 { SYSCTL_PCIX_X66MHZ_ON_X100MHZ, "cannot add a PCIX 66MHz card to an active 100MHz PCIX bus" },
143 #define SYSCTL_PCIX_INVALID_ORDER (SYSCTL_PCIX_ERROR_BASE - 10)
144 { SYSCTL_PCIX_INVALID_ORDER, "invalid reset order" },
146 #define SYSCTL_PCIX_DOWN_33MHZ (SYSCTL_PCIX_ERROR_BASE - 11)
147 { SYSCTL_PCIX_DOWN_33MHZ, "cannot power down a 33 MHz card on an active bus" },
149 #define SYSCTL_PCIX_RESET_33MHZ (SYSCTL_PCIX_ERROR_BASE - 12)
150 { SYSCTL_PCIX_RESET_33MHZ, "cannot reset a 33 MHz card on an active bus" },
152 #define SYSCTL_PCIX_SLOT_NOT_UP (SYSCTL_PCIX_ERROR_BASE - 13)
153 { SYSCTL_PCIX_SLOT_NOT_UP, "cannot reset a slot that is not powered up" },
155 #define SYSCTL_PCIX_INVALID_BUS_SETTING (SYSCTL_PCIX_ERROR_BASE - 14)
156 { SYSCTL_PCIX_INVALID_BUS_SETTING, "invalid bus type/speed selection (PCIX<66MHz, PCI>66MHz)" },
158 #define SYSCTL_PCIX_INVALID_DEPENDENT_SLOT (SYSCTL_PCIX_ERROR_BASE - 15)
159 { SYSCTL_PCIX_INVALID_DEPENDENT_SLOT, "invalid dependent slot in PCI slot configuration" },
161 #define SYSCTL_PCIX_SHARED_IDSELECT (SYSCTL_PCIX_ERROR_BASE - 16)
162 { SYSCTL_PCIX_SHARED_IDSELECT, "cannot enable two slots sharing the same IDSELECT" },
164 #define SYSCTL_PCIX_SLOT_DISABLED (SYSCTL_PCIX_ERROR_BASE - 17)
165 { SYSCTL_PCIX_SLOT_DISABLED, "slot is disabled" },
167 }; /* end sysctl_pci_errors[] */
170 * look up an error message for PCI operations that fail
173 sysctl_pci_error_lookup(int error, char *err_msg)
176 struct sysctl_pci_error_s *e = sysctl_pci_errors;
179 i < (sizeof(sysctl_pci_errors) / sizeof(*e));
182 if (e->error == error)
184 strcpy(err_msg, e->msg);
189 sprintf(err_msg, "unrecognized PCI error type");
194 * This is a place holder routine to keep track of all the
195 * slot-specific initialization that needs to be done.
196 * This is usually called when we want to initialize a new
197 * PCI card on the bus.
200 pcibr_slot_attach(vertex_hdl_t pcibr_vhdl,
206 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
209 if (!(pcibr_soft->bs_slot[slot].slot_status & PCI_SLOT_POWER_ON)) {
213 /* Power-up the slot */
214 error = pcibr_slot_pwr(pcibr_vhdl, slot, PCI_REQ_SLOT_POWER_ON, l1_msg);
221 pcibr_soft->bs_slot[slot].slot_status &= ~PCI_SLOT_POWER_MASK;
222 pcibr_soft->bs_slot[slot].slot_status |= PCI_SLOT_POWER_ON;
225 /* The speed/mode of the bus may have changed due to the hotplug */
226 speed = pcireg_speed_get(pcibr_soft);
227 mode = pcireg_mode_get(pcibr_soft);
228 pcibr_soft->bs_bridge_mode = ((speed << 1) | mode);
231 * Allow cards like the Alteon Gigabit Ethernet Adapter to complete
232 * on-card initialization following the slot reset
234 set_current_state (TASK_INTERRUPTIBLE);
235 schedule_timeout (HZ);
237 /* Find out what is out there */
238 error = pcibr_slot_info_init(pcibr_vhdl, slot);
243 return(PCI_SLOT_INFO_INIT_ERR);
246 /* Set up the address space for this slot in the PCI land */
248 error = pcibr_slot_addr_space_init(pcibr_vhdl, slot);
253 return(PCI_SLOT_ADDR_INIT_ERR);
256 /* Allocate the PCI-X Read Buffer Attribute Registers (RBARs)*/
257 if (IS_PCIX(pcibr_soft)) {
260 /* Recalculate the RBARs for all the devices on the bus. Only
261 * return an error if we error for the given 'slot'
263 pcibr_soft->bs_pcix_rbar_inuse = 0;
264 pcibr_soft->bs_pcix_rbar_avail = NUM_RBAR;
265 pcibr_soft->bs_pcix_rbar_percent_allowed =
266 pcibr_pcix_rbars_calc(pcibr_soft);
267 for (tmp_slot = pcibr_soft->bs_min_slot;
268 tmp_slot < PCIBR_NUM_SLOTS(pcibr_soft); ++tmp_slot) {
269 if (tmp_slot == slot)
270 continue; /* skip this 'slot', we do it below */
271 (void)pcibr_slot_pcix_rbar_init(pcibr_soft, tmp_slot);
274 error = pcibr_slot_pcix_rbar_init(pcibr_soft, slot);
278 return(PCI_SLOT_RBAR_ALLOC_ERR);
282 /* Setup the device register */
283 error = pcibr_slot_device_init(pcibr_vhdl, slot);
288 return(PCI_SLOT_DEV_INIT_ERR);
291 /* Setup host/guest relations */
292 error = pcibr_slot_guest_info_init(pcibr_vhdl, slot);
297 return(PCI_SLOT_GUEST_INIT_ERR);
300 /* Initial RRB management */
301 error = pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
306 return(PCI_SLOT_RRB_ALLOC_ERR);
311 /* Call the device attach */
312 error = pcibr_slot_call_device_attach(pcibr_vhdl, slot, drv_flags);
317 if (error == EUNATCH)
318 return(PCI_NO_DRIVER);
320 return(PCI_SLOT_DRV_ATTACH_ERR);
328 * Enable the PCI slot for a hot-plug insert.
331 pcibr_slot_enable(vertex_hdl_t pcibr_vhdl, struct pcibr_slot_enable_req_s *req_p)
333 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
334 pciio_slot_t slot = req_p->req_device;
337 /* Make sure that we are dealing with a bridge device vertex */
339 return(PCI_NOT_A_BRIDGE);
342 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HOTPLUG, pcibr_vhdl,
343 "pcibr_slot_enable: pcibr_soft=0x%lx, slot=%d, req_p=0x%lx\n",
344 pcibr_soft, slot, req_p));
346 /* Check for the valid slot */
347 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
348 return(PCI_NOT_A_SLOT);
350 if (pcibr_soft->bs_slot[slot].slot_status & PCI_SLOT_ENABLE_CMPLT) {
351 error = PCI_SLOT_ALREADY_UP;
355 error = pcibr_slot_attach(pcibr_vhdl, slot, 0,
356 req_p->req_resp.resp_l1_msg,
357 &req_p->req_resp.resp_sub_errno);
359 req_p->req_resp.resp_l1_msg[PCI_L1_QSIZE] = '\0';
368 * Disable the PCI slot for a hot-plug removal.
371 pcibr_slot_disable(vertex_hdl_t pcibr_vhdl, struct pcibr_slot_disable_req_s *req_p)
373 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
374 pciio_slot_t slot = req_p->req_device;
376 pciio_slot_t tmp_slot;
378 /* Make sure that we are dealing with a bridge device vertex */
380 return(PCI_NOT_A_BRIDGE);
383 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HOTPLUG, pcibr_vhdl,
384 "pcibr_slot_disable: pcibr_soft=0x%lx, slot=%d, req_p=0x%lx\n",
385 pcibr_soft, slot, req_p));
387 /* Check for valid slot */
388 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
389 return(PCI_NOT_A_SLOT);
391 if ((pcibr_soft->bs_slot[slot].slot_status & PCI_SLOT_DISABLE_CMPLT) ||
392 ((pcibr_soft->bs_slot[slot].slot_status & PCI_SLOT_STATUS_MASK) == 0)) {
393 error = PCI_SLOT_ALREADY_DOWN;
395 * RJR - Should we invoke an L1 slot power-down command just in case
396 * a previous shut-down failed to power-down the slot?
401 /* Do not allow the last 33 MHz card to be removed */
402 if (IS_33MHZ(pcibr_soft)) {
403 for (tmp_slot = pcibr_soft->bs_first_slot;
404 tmp_slot <= pcibr_soft->bs_last_slot; tmp_slot++)
405 if (tmp_slot != slot)
406 if (pcibr_soft->bs_slot[tmp_slot].slot_status & PCI_SLOT_POWER_ON) {
411 error = PCI_EMPTY_33MHZ;
416 if (req_p->req_action == PCI_REQ_SLOT_ELIGIBLE)
419 error = pcibr_slot_detach(pcibr_vhdl, slot, 1,
420 req_p->req_resp.resp_l1_msg,
421 &req_p->req_resp.resp_sub_errno);
423 req_p->req_resp.resp_l1_msg[PCI_L1_QSIZE] = '\0';
432 * Power-up or power-down a PCI slot. This routines makes calls to
433 * the L1 system controller driver which requires "external" slot#.
436 pcibr_slot_pwr(vertex_hdl_t pcibr_vhdl,
441 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
446 nasid = NASID_GET(pcibr_soft->bs_base);
447 connection_type = SAL_SYSCTL_IO_XTALK;
449 rv = (int) ia64_sn_sysctl_iobrick_pci_op
452 (u64) pcibr_widget_to_bus(pcibr_vhdl),
453 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
454 (up ? SAL_SYSCTL_PCI_POWER_UP : SAL_SYSCTL_PCI_POWER_DOWN));
457 /* everything's okay; no error message */
461 /* there was a problem; look up an appropriate error message */
462 sysctl_pci_error_lookup(rv, err_msg);
467 #endif /* CONFIG_HOTPLUG_PCI_SGI */
470 * pcibr_slot_info_init
471 * Probe for this slot and see if it is populated.
472 * If it is populated initialize the generic PCI infrastructural
473 * information associated with this particular PCI device.
476 pcibr_slot_info_init(vertex_hdl_t pcibr_vhdl,
479 pcibr_soft_t pcibr_soft;
480 pcibr_info_h pcibr_infoh;
481 pcibr_info_t pcibr_info;
486 pciio_vendor_id_t vendor;
487 pciio_device_id_t device;
496 pciio_function_t rfunc;
498 vertex_hdl_t conn_vhdl;
499 pcibr_soft_slot_t slotp;
502 /* Get the basic software information required to proceed */
503 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
507 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
510 /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
511 * is done by the host slot then we are done.
513 if (pcibr_soft->bs_slot[slot].has_host) {
517 /* Try to read the device-id/vendor-id from the config space */
518 cfgw = pcibr_slot_config_addr(pcibr_soft, slot, 0);
520 if (pcibr_probe_slot(pcibr_soft, cfgw, &idword))
523 slotp = &pcibr_soft->bs_slot[slot];
524 #ifdef CONFIG_HOTPLUG_PCI_SGI
525 slotp->slot_status |= SLOT_POWER_UP;
528 vendor = 0xFFFF & idword;
529 device = 0xFFFF & (idword >> 16);
531 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PROBE, pcibr_vhdl,
532 "pcibr_slot_info_init: slot=%d, vendor=0x%x, device=0x%x\n",
533 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), vendor, device));
535 /* If the vendor id is not valid then the slot is not populated
538 if (vendor == 0xFFFF)
541 htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
543 rfunc = PCIIO_FUNC_NONE;
546 /* NOTE: if a card claims to be multifunction
547 * but only responds to config space 0, treat
548 * it as a unifunction card.
551 if (htype & 0x80) { /* MULTIFUNCTION */
552 for (func = 1; func < 8; ++func) {
553 cfgw = pcibr_func_config_addr(pcibr_soft, 0, slot, func, 0);
554 if (pcibr_probe_slot(pcibr_soft, cfgw, &idwords[func])) {
558 vendor = 0xFFFF & idwords[func];
559 if (vendor == 0xFFFF) {
566 cfgw = pcibr_slot_config_addr(pcibr_soft, slot, 0);
568 pcibr_infoh = kmalloc(nfunc*sizeof (*(pcibr_infoh)), GFP_KERNEL);
569 if ( !pcibr_infoh ) {
572 memset(pcibr_infoh, 0, nfunc*sizeof (*(pcibr_infoh)));
574 pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
575 pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
577 for (func = 0; func < nfunc; ++func) {
581 if (pfail & (1 << func))
584 idword = idwords[func];
585 cfgw = pcibr_func_config_addr(pcibr_soft, 0, slot, func, 0);
587 device = 0xFFFF & (idword >> 16);
588 htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
594 "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
595 pcibr_soft->bs_name, slot, func, htype);
598 nbars = PCI_CFG_BASE_ADDRS;
601 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
602 "pcibr_slot_info_init: slot=%d, func=%d, cfgw=0x%lx\n",
603 PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), func, cfgw));
606 * If the latency timer has already been set, by prom or by the
607 * card itself, use that value. Otherwise look at the device's
608 * 'min_gnt' and attempt to calculate a latency time.
610 * NOTE: For now if the device is on the 'real time' arbitration
611 * ring we don't set the latency timer.
613 * WAR: SGI's IOC3 and RAD devices target abort if you write a
614 * single byte into their config space. So don't set the Latency
615 * Timer for these devices
618 lt_time = do_pcibr_config_get(cfgw, PCI_CFG_LATENCY_TIMER, 1);
619 device_reg = pcireg_device_get(pcibr_soft, slot);
620 if ((lt_time == 0) && !(device_reg & BRIDGE_DEV_RT)) {
622 unsigned min_gnt_mult;
624 /* 'min_gnt' indicates how long of a burst period a device
625 * needs in increments of 250ns. But latency timer is in
626 * PCI clock cycles, so a conversion is needed.
628 min_gnt = do_pcibr_config_get(cfgw, PCI_MIN_GNT, 1);
630 if (IS_133MHZ(pcibr_soft))
631 min_gnt_mult = 32; /* 250ns @ 133MHz in clocks */
632 else if (IS_100MHZ(pcibr_soft))
633 min_gnt_mult = 24; /* 250ns @ 100MHz in clocks */
634 else if (IS_66MHZ(pcibr_soft))
635 min_gnt_mult = 16; /* 250ns @ 66MHz, in clocks */
637 min_gnt_mult = 8; /* 250ns @ 33MHz, in clocks */
639 if ((min_gnt != 0) && ((min_gnt * min_gnt_mult) < 256))
640 lt_time = (min_gnt * min_gnt_mult);
642 lt_time = 4 * min_gnt_mult; /* 1 micro second */
644 do_pcibr_config_set(cfgw, PCI_CFG_LATENCY_TIMER, 1, lt_time);
646 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
647 "pcibr_slot_info_init: set Latency Timer for slot=%d, "
648 "func=%d, to 0x%x\n",
649 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, lt_time));
653 /* In our architecture the setting of the cacheline size isn't
654 * beneficial for cards in PCI mode, but in PCI-X mode devices
655 * can optionally use the cacheline size value for internal
656 * device optimizations (See 7.1.5 of the PCI-X v1.0 spec).
657 * NOTE: cachline size is in doubleword increments
659 if (IS_PCIX(pcibr_soft)) {
660 if (!do_pcibr_config_get(cfgw, PCI_CFG_CACHE_LINE, 1)) {
661 do_pcibr_config_set(cfgw, PCI_CFG_CACHE_LINE, 1, 0x20);
662 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
663 "pcibr_slot_info_init: set CacheLine for slot=%d, "
664 "func=%d, to 0x20\n",
665 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func));
669 /* Get the PCI-X capability if running in PCI-X mode. If the func
670 * doesnt have a pcix capability, allocate a PCIIO_VENDOR_ID_NONE
671 * pcibr_info struct so the device driver for that function is not
674 if (IS_PCIX(pcibr_soft)) {
675 if (!(pcix_cap = pcibr_find_capability(cfgw, PCI_CAP_PCIX))) {
677 "%s: Bus running in PCI-X mode, But card in slot %d, "
678 "func %d not PCI-X capable\n",
679 pcibr_soft->bs_name, slot, func);
680 pcibr_device_info_new(pcibr_soft, slot, PCIIO_FUNC_NONE,
681 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
684 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
685 "pcibr_slot_info_init: PCI-X capability at 0x%lx for "
686 "slot=%d, func=%d\n",
687 pcix_cap, PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func));
692 pcibr_info = pcibr_device_info_new
693 (pcibr_soft, slot, rfunc, vendor, device);
695 /* Keep a running total of the number of PIC-X functions on the bus
696 * and the number of max outstanding split trasnactions that they
697 * have requested. NOTE: "pcix_cap != NULL" implies IS_PCIX()
699 pcibr_info->f_pcix_cap = (cap_pcix_type0_t *)pcix_cap;
700 if (pcibr_info->f_pcix_cap) {
701 int max_out; /* max outstanding splittrans from status reg */
703 pcibr_soft->bs_pcix_num_funcs++;
704 max_out = pcibr_info->f_pcix_cap->pcix_type0_status.max_out_split;
705 pcibr_soft->bs_pcix_split_tot += max_splittrans_to_numbuf[max_out];
708 conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
710 slotp->slot_conn = conn_vhdl;
712 cmd_reg = do_pcibr_config_get(cfgw, PCI_CFG_COMMAND, 4);
714 wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
716 for (win = 0; win < nbars; ++win) {
717 iopaddr_t base, mask, code;
721 * GET THE BASE & SIZE OF THIS WINDOW:
723 * The low two or four bits of the BASE register
724 * determines which address space we are in; the
725 * rest is a base address. BASE registers
726 * determine windows that are power-of-two sized
727 * and naturally aligned, so we can get the size
728 * of a window by writing all-ones to the
729 * register, reading it back, and seeing which
730 * bits are used for decode; the least
731 * significant nonzero bit is also the size of
734 * WARNING: someone may already have allocated
735 * some PCI space to this window, and in fact
736 * PIO may be in process at this very moment
737 * from another processor (or even from this
738 * one, if we get interrupted)! So, if the BASE
739 * already has a nonzero address, be generous
740 * and use the LSBit of that address as the
741 * size; this could overstate the window size.
742 * Usually, when one card is set up, all are set
743 * up; so, since we don't bitch about
744 * overlapping windows, we are ok.
746 * UNFORTUNATELY, some cards do not clear their
747 * BASE registers on reset. I have two heuristics
748 * that can detect such cards: first, if the
749 * decode enable is turned off for the space
750 * that the window uses, we can disregard the
751 * initial value. second, if the address is
752 * outside the range that we use, we can disregard
755 * This is looking very PCI generic. Except for
756 * knowing how many slots and where their config
757 * spaces are, this window loop and the next one
758 * could probably be shared with other PCI host
759 * adapters. It would be interesting to see if
760 * this could be pushed up into pciio, when we
761 * start supporting more PCI providers.
763 base = do_pcibr_config_get(wptr, (win * 4), 4);
765 if (base & PCI_BA_IO_SPACE) {
766 /* BASE is in I/O space. */
767 space = PCIIO_SPACE_IO;
773 } else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
774 base = 0; /* decode not enabled */
777 /* BASE is in MEM space. */
778 space = PCIIO_SPACE_MEM;
780 code = base & PCI_BA_MEM_LOCATION; /* extract BAR type */
784 } else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
785 base = 0; /* decode not enabled */
786 } else if (base & 0xC0000000) {
787 base = 0; /* outside permissable range */
788 } else if ((code == PCI_BA_MEM_64BIT) &&
789 (do_pcibr_config_get(wptr, ((win + 1)*4), 4) != 0)) {
790 base = 0; /* outside permissable range */
794 if (base != 0) { /* estimate size */
795 pciio_space_t tmp_space = space;
801 * Reserve this space in the relavent address map. Don't
802 * care about the return code from pcibr_bus_addr_alloc().
805 if (space == PCIIO_SPACE_MEM && code != PCI_BA_MEM_1MEG) {
806 tmp_space = PCIIO_SPACE_MEM32;
809 tmp_base = pcibr_bus_addr_alloc(pcibr_soft,
810 &pcibr_info->f_window[win],
814 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
815 "pcibr_slot_info_init: slot=%d, func=%d win %d "
816 "reserving space %s [0x%lx..0x%lx], tmp_base 0x%lx\n",
817 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, win,
818 pci_space[tmp_space], (uint64_t)base,
819 (uint64_t)(base + size - 1), (uint64_t)tmp_base));
820 } else { /* calculate size */
821 do_pcibr_config_set(wptr, (win * 4), 4, ~0); /* write 1's */
822 size = do_pcibr_config_get(wptr, (win * 4), 4); /* read back */
823 size &= mask; /* keep addr */
824 size &= -size; /* keep lsbit */
829 pcibr_info->f_window[win].w_space = space;
830 pcibr_info->f_window[win].w_base = base;
831 pcibr_info->f_window[win].w_size = size;
833 if (code == PCI_BA_MEM_64BIT) {
834 win++; /* skip upper half */
835 do_pcibr_config_set(wptr, (win * 4), 4, 0); /* must be zero */
844 * pcibr_find_capability
845 * Walk the list of capabilities (if it exists) looking for
846 * the requested capability. Return a cfg_p pointer to the
847 * capability if found, else return NULL
850 pcibr_find_capability(cfg_p cfgw,
855 int defend_against_circular_linkedlist = 0;
857 /* Check to see if there is a capabilities pointer in the cfg header */
858 if (!(do_pcibr_config_get(cfgw, PCI_CFG_STATUS, 2) & PCI_STAT_CAP_LIST)) {
863 * Read up the capabilities head pointer from the configuration header.
864 * Capabilities are stored as a linked list in the lower 48 dwords of
865 * config space and are dword aligned. (Note: spec states the least two
866 * significant bits of the next pointer must be ignored, so we mask
869 cap_nxt = (do_pcibr_config_get(cfgw, PCI_CAPABILITIES_PTR, 1) & 0xfc);
871 while (cap_nxt && (defend_against_circular_linkedlist <= 48)) {
872 cap_id = do_pcibr_config_get(cfgw, cap_nxt, 1);
873 if (cap_id == capability) {
874 return (cfg_p)((char *)cfgw + cap_nxt);
876 cap_nxt = (do_pcibr_config_get(cfgw, cap_nxt+1, 1) & 0xfc);
877 defend_against_circular_linkedlist++;
884 * pcibr_slot_info_free
885 * Remove all the PCI infrastructural information associated
886 * with a particular PCI device.
889 pcibr_slot_info_free(vertex_hdl_t pcibr_vhdl,
892 pcibr_soft_t pcibr_soft;
893 pcibr_info_h pcibr_infoh;
896 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
901 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
904 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
906 pcibr_device_info_free(pcibr_vhdl, slot);
908 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
910 pcibr_soft->bs_slot[slot].bss_ninfo = 0;
916 * pcibr_slot_pcix_rbar_init
917 * Allocate RBARs to the PCI-X functions on a given device
920 pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft,
923 pcibr_info_h pcibr_infoh;
924 pcibr_info_t pcibr_info;
928 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
931 if ((nfunc = pcibr_soft->bs_slot[slot].bss_ninfo) < 1)
934 if (!(pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos))
937 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl,
938 "pcibr_slot_pcix_rbar_init for slot %d\n",
939 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot)));
940 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl,
941 "\tslot/func\trequested\tgiven\tinuse\tavail\n"));
943 for (func = 0; func < nfunc; ++func) {
944 cap_pcix_type0_t *pcix_cap_p;
945 cap_pcix_stat_reg_t *pcix_statreg_p;
946 cap_pcix_cmd_reg_t *pcix_cmdreg_p;
949 if (!(pcibr_info = pcibr_infoh[func]))
952 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
955 if (!(pcix_cap_p = pcibr_info->f_pcix_cap))
958 pcix_statreg_p = &pcix_cap_p->pcix_type0_status;
959 pcix_cmdreg_p = &pcix_cap_p->pcix_type0_command;
961 /* If there are enough RBARs to satify the number of "max outstanding
962 * transactions" each function requested (bs_pcix_rbar_percent_allowed
963 * is 100%), then give each function what it requested, otherwise give
964 * the functions a "percentage of what they requested".
966 if (pcibr_soft->bs_pcix_rbar_percent_allowed >= 100) {
967 pcix_cmdreg_p->max_split = pcix_statreg_p->max_out_split;
968 num_rbar = max_splittrans_to_numbuf[pcix_cmdreg_p->max_split];
969 pcibr_soft->bs_pcix_rbar_inuse += num_rbar;
970 pcibr_soft->bs_pcix_rbar_avail -= num_rbar;
971 pcix_cmdreg_p->max_mem_read_cnt = pcix_statreg_p->max_mem_read_cnt;
973 int index; /* index into max_splittrans_to_numbuf table */
974 int max_out; /* max outstanding transactions given to func */
976 /* Calculate the percentage of RBARs this function can have.
977 * NOTE: Every function gets at least 1 RBAR (thus the "+1").
978 * bs_pcix_rbar_percent_allowed is the percentage of what was
979 * requested less this 1 RBAR that all functions automatically
982 max_out = ((max_splittrans_to_numbuf[pcix_statreg_p->max_out_split]
983 * pcibr_soft->bs_pcix_rbar_percent_allowed) / 100) + 1;
985 /* round down the newly caclulated max_out to a valid number in
986 * max_splittrans_to_numbuf[]
988 for (index = 0; index < MAX_SPLIT_TABLE-1; index++)
989 if (max_splittrans_to_numbuf[index + 1] > max_out)
992 pcix_cmdreg_p->max_split = index;
993 num_rbar = max_splittrans_to_numbuf[pcix_cmdreg_p->max_split];
994 pcibr_soft->bs_pcix_rbar_inuse += num_rbar;
995 pcibr_soft->bs_pcix_rbar_avail -= num_rbar;
996 pcix_cmdreg_p->max_mem_read_cnt = pcix_statreg_p->max_mem_read_cnt;
999 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl,
1000 "\t %d/%d \t %d \t %d \t %d \t %d\n",
1001 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func,
1002 max_splittrans_to_numbuf[pcix_statreg_p->max_out_split],
1003 max_splittrans_to_numbuf[pcix_cmdreg_p->max_split],
1004 pcibr_soft->bs_pcix_rbar_inuse,
1005 pcibr_soft->bs_pcix_rbar_avail));
1012 * pcibr_slot_addr_space_init
1013 * Reserve chunks of PCI address space as required by
1014 * the base registers in the card.
1017 pcibr_slot_addr_space_init(vertex_hdl_t pcibr_vhdl,
1020 pcibr_soft_t pcibr_soft;
1021 pcibr_info_h pcibr_infoh;
1022 pcibr_info_t pcibr_info;
1032 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1037 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1040 /* allocate address space,
1041 * for windows that have not been
1042 * previously assigned.
1044 if (pcibr_soft->bs_slot[slot].has_host) {
1048 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
1052 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
1057 * Try to make the DevIO windows not
1058 * overlap by pushing the "io" and "hi"
1059 * allocation areas up to the next one
1060 * or two megabyte bound. This also
1061 * keeps them from being zero.
1063 * DO NOT do this with "pci_lo" since
1064 * the entire "lo" area is only a
1065 * megabyte, total ...
1067 align_slot = (slot < 2) ? 0x200000 : 0x100000;
1069 for (func = 0; func < nfunc; ++func) {
1072 pciio_space_t space;
1075 unsigned pci_cfg_cmd_reg;
1076 unsigned pci_cfg_cmd_reg_add = 0;
1078 pcibr_info = pcibr_infoh[func];
1083 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
1086 cfgw = pcibr_func_config_addr(pcibr_soft, 0, slot, func, 0);
1087 wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
1089 if ((do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1) & 0x7f) != 0)
1092 nbars = PCI_CFG_BASE_ADDRS;
1094 for (win = 0; win < nbars; ++win) {
1095 space = pcibr_info->f_window[win].w_space;
1096 base = pcibr_info->f_window[win].w_base;
1097 size = pcibr_info->f_window[win].w_size;
1103 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1104 "pcibr_slot_addr_space_init: slot=%d, "
1105 "func=%d win %d is in space %s [0x%lx..0x%lx], "
1106 "allocated by prom\n",
1107 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, win,
1108 pci_space[space], (uint64_t)base,
1109 (uint64_t)(base + size - 1)));
1111 continue; /* already allocated */
1114 align = (win) ? size : align_slot;
1116 if (align < PAGE_SIZE)
1117 align = PAGE_SIZE; /* ie. 0x00004000 */
1120 case PCIIO_SPACE_IO:
1121 base = pcibr_bus_addr_alloc(pcibr_soft,
1122 &pcibr_info->f_window[win],
1129 case PCIIO_SPACE_MEM:
1130 if ((do_pcibr_config_get(wptr, (win * 4), 4) &
1131 PCI_BA_MEM_LOCATION) == PCI_BA_MEM_1MEG) {
1133 /* allocate from 20-bit PCI space */
1134 base = pcibr_bus_addr_alloc(pcibr_soft,
1135 &pcibr_info->f_window[win],
1141 /* allocate from 32-bit or 64-bit PCI space */
1142 base = pcibr_bus_addr_alloc(pcibr_soft,
1143 &pcibr_info->f_window[win],
1153 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1154 "pcibr_slot_addr_space_init: slot=%d, window %d "
1155 "had bad space code %d\n",
1156 PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), win, space));
1158 pcibr_info->f_window[win].w_base = base;
1159 do_pcibr_config_set(wptr, (win * 4), 4, base);
1162 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1163 "pcibr_slot_addr_space_init: slot=%d, func=%d. win %d "
1164 "is in space %s [0x%lx..0x%lx], allocated by pcibr\n",
1165 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, win,
1166 pci_space[space], (uint64_t)base,
1167 (uint64_t)(base + size - 1)));
1169 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1170 "pcibr_slot_addr_space_init: slot=%d, func=%d, win %d, "
1171 "unable to alloc 0x%lx in space %s\n",
1172 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, win,
1173 (uint64_t)size, pci_space[space]));
1178 * Allocate space for the EXPANSION ROM
1182 wptr = cfgw + PCI_EXPANSION_ROM / 4;
1183 do_pcibr_config_set(wptr, 0, 4, 0xFFFFF000);
1184 mask = do_pcibr_config_get(wptr, 0, 4);
1185 if (mask & 0xFFFFF000) {
1186 size = mask & -mask;
1187 base = pcibr_bus_addr_alloc(pcibr_soft,
1188 &pcibr_info->f_rwindow,
1194 do_pcibr_config_set(wptr, 0, 4, base);
1195 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1196 "pcibr_slot_addr_space_init: slot=%d, func=%d, "
1197 "ROM in [0x%X..0x%X], allocated by pcibr\n",
1198 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
1199 func, base, base + size - 1));
1203 pcibr_info->f_rbase = base;
1204 pcibr_info->f_rsize = size;
1207 * if necessary, update the board's
1208 * command register to enable decoding
1209 * in the windows we added.
1211 * There are some bits we always want to
1214 pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
1217 * The Adaptec 1160 FC Controller WAR #767995:
1218 * The part incorrectly ignores the upper 32 bits of a 64 bit
1219 * address when decoding references to its registers so to
1220 * keep it from responding to a bus cycle that it shouldn't
1221 * we only use I/O space to get at it's registers. Don't
1222 * enable memory space accesses on that PCI device.
1224 #define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
1225 #define FCADP_DEVID 0x1160 /* Adaptec 1160 Device ID from fcadp.h */
1227 if ((pcibr_info->f_vendor != FCADP_VENDID) ||
1228 (pcibr_info->f_device != FCADP_DEVID))
1229 pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
1231 pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
1233 pci_cfg_cmd_reg = do_pcibr_config_get(cfgw, PCI_CFG_COMMAND, 4);
1234 pci_cfg_cmd_reg &= 0xFFFF;
1235 if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
1236 do_pcibr_config_set(cfgw, PCI_CFG_COMMAND, 4,
1237 pci_cfg_cmd_reg | pci_cfg_cmd_reg_add);
1243 * pcibr_slot_device_init
1244 * Setup the device register in the bridge for this PCI slot.
1248 pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl,
1251 pcibr_soft_t pcibr_soft;
1254 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1259 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1263 * Adjustments to Device(x) and init of bss_device shadow
1265 devreg = pcireg_device_get(pcibr_soft, slot);
1266 devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
1269 * Enable virtual channels by default (exception: see PIC WAR below)
1271 devreg |= BRIDGE_DEV_VIRTUAL_EN;
1274 * PIC WAR. PV# 855271: Disable virtual channels in the PIC since
1275 * it can cause problems with 32-bit devices. We'll set the bit in
1276 * pcibr_try_set_device() iff we're 64-bit and requesting virtual
1279 if (PCIBR_WAR_ENABLED(PV855271, pcibr_soft)) {
1280 devreg &= ~BRIDGE_DEV_VIRTUAL_EN;
1282 devreg |= BRIDGE_DEV_COH;
1284 pcibr_soft->bs_slot[slot].bss_device = devreg;
1285 pcireg_device_set(pcibr_soft, slot, devreg);
1287 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEVREG, pcibr_vhdl,
1288 "pcibr_slot_device_init: Device(%d): 0x%x\n",
1294 * pcibr_slot_guest_info_init
1295 * Setup the host/guest relations for a PCI slot.
1298 pcibr_slot_guest_info_init(vertex_hdl_t pcibr_vhdl,
1301 pcibr_soft_t pcibr_soft;
1302 pcibr_info_h pcibr_infoh;
1303 pcibr_info_t pcibr_info;
1304 pcibr_soft_slot_t slotp;
1306 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1311 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1314 slotp = &pcibr_soft->bs_slot[slot];
1316 /* create info and verticies for guest slots;
1317 * for compatibilitiy macros, create info
1318 * for even unpopulated slots (but do not
1319 * build verticies for them).
1321 if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
1322 pcibr_infoh = kmalloc(sizeof (*(pcibr_infoh)), GFP_KERNEL);
1323 if ( !pcibr_infoh ) {
1326 memset(pcibr_infoh, 0, sizeof (*(pcibr_infoh)));
1328 pcibr_soft->bs_slot[slot].bss_ninfo = 1;
1329 pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
1331 pcibr_info = pcibr_device_info_new
1332 (pcibr_soft, slot, PCIIO_FUNC_NONE,
1333 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
1335 if (pcibr_soft->bs_slot[slot].has_host) {
1336 slotp->slot_conn = pciio_device_info_register
1337 (pcibr_vhdl, &pcibr_info->f_c);
1341 /* generate host/guest relations
1343 if (pcibr_soft->bs_slot[slot].has_host) {
1344 int host = pcibr_soft->bs_slot[slot].host_slot;
1345 pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
1347 hwgraph_edge_add(slotp->slot_conn,
1348 host_slotp->slot_conn,
1351 /* XXX- only gives us one guest edge per
1352 * host. If/when we have a host with more than
1353 * one guest, we will need to figure out how
1354 * the host finds all its guests, and sorts
1355 * out which one is which.
1357 hwgraph_edge_add(host_slotp->slot_conn,
1367 * pcibr_slot_call_device_attach
1368 * This calls the associated driver attach routine for the PCI
1369 * card in this slot.
1372 pcibr_slot_call_device_attach(vertex_hdl_t pcibr_vhdl,
1376 pcibr_soft_t pcibr_soft;
1377 pcibr_info_h pcibr_infoh;
1378 pcibr_info_t pcibr_info;
1380 vertex_hdl_t xconn_vhdl, conn_vhdl;
1386 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1391 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1394 if (pcibr_soft->bs_slot[slot].has_host) {
1398 xconn_vhdl = pcibr_soft->bs_conn;
1400 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
1401 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
1403 for (func = 0; func < nfunc; ++func) {
1405 pcibr_info = pcibr_infoh[func];
1410 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
1413 conn_vhdl = pcibr_info->f_vertex;
1415 error_func = pciio_device_attach(conn_vhdl, drv_flags);
1417 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEV_ATTACH, pcibr_vhdl,
1418 "pcibr_slot_call_device_attach: slot=%d, func=%d "
1419 "drv_flags=0x%x, pciio_device_attach returned %d\n",
1420 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func,
1421 drv_flags, error_func));
1422 pcibr_info->f_att_det_error = error_func;
1425 error_slot = error_func;
1431 #ifdef CONFIG_HOTPLUG_PCI_SGI
1433 if ((error != ENODEV) && (error != EUNATCH) && (error != EPERM)) {
1434 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1435 pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
1438 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1439 pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
1441 #endif /* CONFIG_HOTPLUG_PCI_SGI */
1446 * pcibr_slot_call_device_detach
1447 * This calls the associated driver detach routine for the PCI
1448 * card in this slot.
1451 pcibr_slot_call_device_detach(vertex_hdl_t pcibr_vhdl,
1455 pcibr_soft_t pcibr_soft;
1456 pcibr_info_h pcibr_infoh;
1457 pcibr_info_t pcibr_info;
1459 vertex_hdl_t conn_vhdl = GRAPH_VERTEX_NONE;
1465 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1470 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1473 if (pcibr_soft->bs_slot[slot].has_host)
1476 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
1477 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
1479 for (func = 0; func < nfunc; ++func) {
1481 pcibr_info = pcibr_infoh[func];
1486 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
1489 if (IS_PCIX(pcibr_soft) && pcibr_info->f_pcix_cap) {
1492 pcibr_soft->bs_pcix_num_funcs--;
1493 max_out = pcibr_info->f_pcix_cap->pcix_type0_status.max_out_split;
1494 pcibr_soft->bs_pcix_split_tot -= max_splittrans_to_numbuf[max_out];
1497 conn_vhdl = pcibr_info->f_vertex;
1499 error_func = pciio_device_detach(conn_vhdl, drv_flags);
1501 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEV_DETACH, pcibr_vhdl,
1502 "pcibr_slot_call_device_detach: slot=%d, func=%d "
1503 "drv_flags=0x%x, pciio_device_detach returned %d\n",
1504 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func,
1505 drv_flags, error_func));
1507 pcibr_info->f_att_det_error = error_func;
1510 error_slot = error_func;
1516 #ifdef CONFIG_HOTPLUG_PCI_SGI
1518 if ((error != ENODEV) && (error != EUNATCH) && (error != EPERM)) {
1519 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1520 pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
1523 if (conn_vhdl != GRAPH_VERTEX_NONE)
1524 pcibr_device_unregister(conn_vhdl);
1525 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1526 pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
1528 #endif /* CONFIG_HOTPLUG_PCI_SGI */
1536 * This is a place holder routine to keep track of all the
1537 * slot-specific freeing that needs to be done.
1540 pcibr_slot_detach(vertex_hdl_t pcibr_vhdl,
1546 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1549 /* Call the device detach function */
1550 error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
1553 *sub_errorp = error;
1556 return PCI_SLOT_DRV_DETACH_ERR;
1559 /* Recalculate the RBARs for all the devices on the bus since we've
1560 * just freed some up and some of the devices could use them.
1562 if (IS_PCIX(pcibr_soft)) {
1565 pcibr_soft->bs_pcix_rbar_inuse = 0;
1566 pcibr_soft->bs_pcix_rbar_avail = NUM_RBAR;
1567 pcibr_soft->bs_pcix_rbar_percent_allowed =
1568 pcibr_pcix_rbars_calc(pcibr_soft);
1570 for (tmp_slot = pcibr_soft->bs_min_slot;
1571 tmp_slot < PCIBR_NUM_SLOTS(pcibr_soft); ++tmp_slot)
1572 (void)pcibr_slot_pcix_rbar_init(pcibr_soft, tmp_slot);
1580 * pcibr_probe_slot_pic: read a config space word
1581 * while trapping any errors; return zero if
1582 * all went OK, or nonzero if there was an error.
1583 * The value read, if any, is passed back
1584 * through the valp parameter.
1587 pcibr_probe_slot(pcibr_soft_t pcibr_soft,
1591 return pcibr_probe_work(pcibr_soft, (void *)cfg, 4, (void *)valp);
1595 * Probe an offset within a piomap with errors disabled.
1596 * len must be 1, 2, 4, or 8. The probed address must be a multiple of
1599 * Returns: 0 if the offset was probed and put valid data in valp
1600 * -1 if there was a usage error such as improper alignment
1601 * or out of bounds offset/len combination. In this
1602 * case, the map was not probed
1603 * 1 if the offset was probed but resulted in an error
1604 * such as device not responding, bus error, etc.
1608 pcibr_piomap_probe(pcibr_piomap_t piomap, off_t offset, int len, void *valp)
1610 if (offset + len > piomap->bp_mapsz) {
1614 return pcibr_probe_work(piomap->bp_soft,
1615 piomap->bp_kvaddr + offset, len, valp);
1619 pcibr_disable_mst_timeout(pcibr_soft_t pcibr_soft)
1621 uint64_t old_enable;
1622 uint64_t new_enable;
1625 intr_bits = PIC_ISR_PCI_MST_TIMEOUT
1626 | PIC_ISR_PCIX_MTOUT | PIC_ISR_PCIX_SPLIT_EMSG;
1627 old_enable = pcireg_intr_enable_get(pcibr_soft);
1628 pcireg_intr_enable_bit_clr(pcibr_soft, intr_bits);
1629 new_enable = pcireg_intr_enable_get(pcibr_soft);
1631 if (old_enable == new_enable) {
1632 return 0; /* was already disabled */
1639 pcibr_enable_mst_timeout(pcibr_soft_t pcibr_soft)
1641 uint64_t old_enable;
1642 uint64_t new_enable;
1645 intr_bits = PIC_ISR_PCI_MST_TIMEOUT
1646 | PIC_ISR_PCIX_MTOUT | PIC_ISR_PCIX_SPLIT_EMSG;
1647 old_enable = pcireg_intr_enable_get(pcibr_soft);
1648 pcireg_intr_enable_bit_set(pcibr_soft, intr_bits);
1649 new_enable = pcireg_intr_enable_get(pcibr_soft);
1651 if (old_enable == new_enable) {
1652 return 0; /* was alread enabled */
1659 * pcibr_probe_slot: read a config space word
1660 * while trapping any errors; return zero if
1661 * all went OK, or nonzero if there was an error.
1662 * The value read, if any, is passed back
1663 * through the valp parameter.
1666 pcibr_probe_work(pcibr_soft_t pcibr_soft,
1677 if (len != 1 && len != 2 && len != 4 && len != 8) {
1678 return -1; /* invalid len */
1681 if ((uint64_t)addr & (len-1)) {
1682 return -1; /* invalid alignment */
1685 changed = pcibr_disable_mst_timeout(pcibr_soft);
1687 rv = snia_badaddr_val((void *)addr, len, valp);
1689 /* Clear the int_view register incase it was set */
1690 pcireg_intr_reset_set(pcibr_soft, BRIDGE_IRR_MULTI_CLR);
1693 pcibr_enable_mst_timeout(pcibr_soft);
1695 return (rv ? 1 : 0); /* return 1 for snia_badaddr_val error, 0 if ok */
1699 pcibr_device_info_free(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot)
1701 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1702 pcibr_info_t pcibr_info;
1703 pciio_function_t func;
1704 pcibr_soft_slot_t slotp = &pcibr_soft->bs_slot[slot];
1706 int nfunc = slotp->bss_ninfo;
1713 for (func = 0; func < nfunc; func++) {
1714 pcibr_info = slotp->bss_infos[func];
1719 s = pcibr_lock(pcibr_soft);
1721 /* Disable memory and I/O BARs */
1722 cfgw = pcibr_func_config_addr(pcibr_soft, 0, slot, func, 0);
1723 cmd_reg = do_pcibr_config_get(cfgw, PCI_CFG_COMMAND, 4);
1724 cmd_reg &= (PCI_CMD_MEM_SPACE | PCI_CMD_IO_SPACE);
1725 do_pcibr_config_set(cfgw, PCI_CFG_COMMAND, 4, cmd_reg);
1727 for (bar = 0; bar < PCI_CFG_BASE_ADDRS; bar++) {
1728 if (pcibr_info->f_window[bar].w_space == PCIIO_SPACE_NONE)
1731 /* Free the PCI bus space */
1732 pcibr_bus_addr_free(&pcibr_info->f_window[bar]);
1734 /* Get index of the DevIO(x) register used to access this BAR */
1735 devio_index = pcibr_info->f_window[bar].w_devio_index;
1738 /* On last use, clear the DevIO(x) used to access this BAR */
1739 if (! --pcibr_soft->bs_slot[devio_index].bss_devio.bssd_ref_cnt) {
1740 pcibr_soft->bs_slot[devio_index].bss_devio.bssd_space =
1742 pcibr_soft->bs_slot[devio_index].bss_devio.bssd_base =
1743 PCIBR_D32_BASE_UNSET;
1744 pcibr_soft->bs_slot[devio_index].bss_device = 0;
1748 /* Free the Expansion ROM PCI bus space */
1749 if(pcibr_info->f_rbase && pcibr_info->f_rsize) {
1750 pcibr_bus_addr_free(&pcibr_info->f_rwindow);
1753 pcibr_unlock(pcibr_soft, s);
1755 slotp->bss_infos[func] = 0;
1756 pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
1757 pciio_device_info_free(&pcibr_info->f_c);
1762 /* Reset the mapping usage counters */
1763 slotp->bss_pmu_uctr = 0;
1764 slotp->bss_d32_uctr = 0;
1765 slotp->bss_d64_uctr = 0;
1767 /* Clear the Direct translation info */
1768 slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
1769 slotp->bss_d64_flags = 0;
1770 slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
1771 slotp->bss_d32_flags = 0;
1776 pcibr_bus_addr_alloc(pcibr_soft_t pcibr_soft, pciio_win_info_t win_info_p,
1777 pciio_space_t space, int start, int size, int align)
1779 pciio_win_map_t win_map_p;
1780 struct resource *root_resource = NULL;
1781 iopaddr_t iopaddr = 0;
1785 case PCIIO_SPACE_IO:
1786 win_map_p = &pcibr_soft->bs_io_win_map;
1787 root_resource = &pcibr_soft->bs_io_win_root_resource;
1790 case PCIIO_SPACE_MEM:
1791 win_map_p = &pcibr_soft->bs_swin_map;
1792 root_resource = &pcibr_soft->bs_swin_root_resource;
1795 case PCIIO_SPACE_MEM32:
1796 win_map_p = &pcibr_soft->bs_mem_win_map;
1797 root_resource = &pcibr_soft->bs_mem_win_root_resource;
1804 iopaddr = pciio_device_win_alloc(root_resource,
1806 ? &win_info_p->w_win_alloc
1808 start, size, align);
1814 pcibr_bus_addr_free(pciio_win_info_t win_info_p)
1816 pciio_device_win_free(&win_info_p->w_win_alloc);
1820 * given a vertex_hdl to the pcibr_vhdl, return the brick's bus number
1821 * associated with that vertex_hdl. The true mapping happens from the
1822 * io_brick_tab[] array defined in ml/SN/iograph.c
1825 pcibr_widget_to_bus(vertex_hdl_t pcibr_vhdl)
1827 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1828 xwidgetnum_t widget = pcibr_soft->bs_xid;
1829 int bricktype = pcibr_soft->bs_bricktype;
1832 if ((bus = io_brick_map_widget(bricktype, widget)) <= 0) {
1833 printk(KERN_WARNING "pcibr_widget_to_bus() bad bricktype %d\n", bricktype);
1837 /* For PIC there are 2 busses per widget and pcibr_soft->bs_busnum
1838 * will be 0 or 1. Add in the correct PIC bus offset.
1840 bus += pcibr_soft->bs_busnum;