2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved.
9 #include <asm/sn/sn2/shub_mmr.h>
11 #define ZEROVAL 0x3f // "zero" value for outstanding PIO requests
12 #define DEADLOCKBIT SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT
13 #define WRITECOUNT SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT
14 #define ALIAS_OFFSET (SH_PIO_WRITE_STATUS_0_ALIAS-SH_PIO_WRITE_STATUS_0)
17 .global sn2_ptc_deadlock_recovery_core
18 .proc sn2_ptc_deadlock_recovery_core
20 sn2_ptc_deadlock_recovery_core:
35 extr.u piowcphy=piowc,0,61;; // Convert piowc to uncached physical address
36 dep piowcphy=-1,piowcphy,63,1
38 mov zeroval=ZEROVAL // "zero" value for PIO write count
41 add scr2=ALIAS_OFFSET,piowc // Address of WRITE_STATUS alias register
42 mov scr1=7;; // Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR
45 5: ld8.acq scr1=[piowc];; // Wait for PIOs to complete.
46 extr.u scr2=scr1,WRITECOUNT,7;;// PIO count
47 cmp.ne p6,p0=zeroval,scr2
52 ////////////// BEGIN PHYSICAL MODE ////////////////////
53 mov psrsave=psr // Disable IC (no PMIs)
54 rsm psr.i | psr.dt | psr.ic;;
57 st8.rel [ptc0]=data0 // Write PTC0 & wait for completion.
59 5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
60 extr.u scr2=scr1,WRITECOUNT,7;;// PIO count
61 cmp.ne p6,p0=zeroval,scr2
62 (p6) br.cond.sptk 5b;;
64 tbit.nz p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
66 (p7) st8.rel [ptc1]=data1;; // Now write PTC1.
68 5: ld8.acq scr1=[piowcphy];; // Wait for PIOs to complete.
69 extr.u scr2=scr1,WRITECOUNT,7;;// PIO count
70 cmp.ne p6,p0=zeroval,scr2
73 tbit.nz p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK
75 mov psr.l=psrsave;; // Reenable IC
77 ////////////// END PHYSICAL MODE ////////////////////
79 (p8) br.cond.spnt 1b;; // Repeat if DEADLOCK occurred.
82 .endp sn2_ptc_deadlock_recovery_core