2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/tty.h>
20 #include <linux/console.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/major.h>
24 #include <linux/serial_reg.h>
25 #include <linux/rtc.h>
26 #include <linux/vt_kern.h>
30 #include <asm/bootinfo.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
33 #include <asm/setup.h>
35 #include <asm/traps.h>
37 #include <asm/machdep.h>
38 #include <asm/q40_master.h>
40 extern void floppy_setup(char *str, int *ints);
42 extern irqreturn_t q40_process_int (int level, struct pt_regs *regs);
43 extern irqreturn_t (*q40_default_handler[]) (int, void *, struct pt_regs *); /* added just for debugging */
44 extern void q40_init_IRQ (void);
45 extern void q40_free_irq (unsigned int, void *);
46 extern int show_q40_interrupts (struct seq_file *, void *);
47 extern void q40_enable_irq (unsigned int);
48 extern void q40_disable_irq (unsigned int);
49 static void q40_get_model(char *model);
50 static int q40_get_hardware_list(char *buffer);
51 extern int q40_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id);
52 extern void q40_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *));
54 extern unsigned long q40_gettimeoffset (void);
55 extern int q40_hwclk (int, struct rtc_time *);
56 extern unsigned int q40_get_ss (void);
57 extern int q40_set_clock_mmss (unsigned long);
58 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
59 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
60 extern void q40_reset (void);
62 extern void q40_waitbut(void);
63 void q40_set_vectors (void);
65 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ );
67 extern char *saved_command_line;
68 extern char m68k_debug_device[];
69 static void q40_mem_console_write(struct console *co, const char *b,
74 static struct console q40_console_driver = {
76 .flags = CON_PRINTBUFFER,
81 /* early debugging function:*/
82 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
85 static void q40_mem_console_write(struct console *co, const char *s,
98 void printq40(char *str)
101 char *p=q40_mem_cptr;
103 while (l-- >0 && _cpleft-- >0)
114 #ifdef CONFIG_HEARTBEAT
115 static void q40_heartbeat(int on)
129 printk ("\n\n*******************************************\n"
130 "Called q40_reset : press the RESET button!! \n"
131 "*******************************************\n");
138 printk ("\n\n*******************\n"
140 "*******************\n");
145 static void q40_get_model(char *model)
147 sprintf(model, "Q40");
150 /* No hardware options on Q40? */
152 static int q40_get_hardware_list(char *buffer)
158 static unsigned int serports[]={0x3f8,0x2f8,0x3e8,0x2e8,0};
159 void q40_disable_irqs(void)
164 while((i=serports[j++])) outb(0,i+UART_IER);
165 master_outb(0,EXT_ENABLE_REG);
166 master_outb(0,KEY_IRQ_ENABLE_REG);
169 void __init config_q40(void)
171 mach_sched_init = q40_sched_init;
173 mach_init_IRQ = q40_init_IRQ;
174 mach_gettimeoffset = q40_gettimeoffset;
175 mach_hwclk = q40_hwclk;
176 mach_get_ss = q40_get_ss;
177 mach_get_rtc_pll = q40_get_rtc_pll;
178 mach_set_rtc_pll = q40_set_rtc_pll;
179 mach_set_clock_mmss = q40_set_clock_mmss;
181 mach_reset = q40_reset;
182 mach_free_irq = q40_free_irq;
183 mach_process_int = q40_process_int;
184 mach_get_irq_list = show_q40_interrupts;
185 mach_request_irq = q40_request_irq;
186 enable_irq = q40_enable_irq;
187 disable_irq = q40_disable_irq;
188 mach_default_handler = &q40_default_handler;
189 mach_get_model = q40_get_model;
190 mach_get_hardware_list = q40_get_hardware_list;
192 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
193 mach_beep = q40_mksound;
195 #ifdef CONFIG_HEARTBEAT
196 mach_heartbeat = q40_heartbeat;
198 mach_halt = q40_halt;
199 #ifdef CONFIG_DUMMY_CONSOLE
200 conswitchp = &dummy_con;
203 /* disable a few things that SMSQ might have left enabled */
206 /* no DMA at all, but ide-scsi requires it.. make sure
207 * all physical RAM fits into the boundary - otherwise
208 * allocator may play costly and useless tricks */
209 mach_max_dma_address = 1024*1024*1024;
211 /* useful for early debugging stages - writes kernel messages into SRAM */
212 if (!strncmp( m68k_debug_device,"mem",3 ))
214 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
215 _cpleft=2000-((long)q40_mem_cptr-0xff020000)/4;
216 q40_console_driver.write = q40_mem_console_write;
217 register_console(&q40_console_driver);
222 int q40_parse_bootinfo(const struct bi_record *rec)
228 static inline unsigned char bcd2bin (unsigned char b)
230 return ((b>>4)*10 + (b&15));
233 static inline unsigned char bin2bcd (unsigned char b)
235 return (((b/10)*16) + (b%10));
239 unsigned long q40_gettimeoffset (void)
241 return 5000*(ql_ticks!=0);
246 * Looks like op is non-zero for setting the clock, and zero for
249 * struct hwclk_time {
250 * unsigned sec; 0..59
251 * unsigned min; 0..59
252 * unsigned hour; 0..23
253 * unsigned day; 1..31
254 * unsigned mon; 0..11
255 * unsigned year; 00...
256 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
260 int q40_hwclk(int op, struct rtc_time *t)
264 Q40_RTC_CTRL |= Q40_RTC_WRITE;
266 Q40_RTC_SECS = bin2bcd(t->tm_sec);
267 Q40_RTC_MINS = bin2bcd(t->tm_min);
268 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
269 Q40_RTC_DATE = bin2bcd(t->tm_mday);
270 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
271 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
273 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
275 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
279 Q40_RTC_CTRL |= Q40_RTC_READ;
281 t->tm_year = bcd2bin (Q40_RTC_YEAR);
282 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
283 t->tm_mday = bcd2bin (Q40_RTC_DATE);
284 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
285 t->tm_min = bcd2bin (Q40_RTC_MINS);
286 t->tm_sec = bcd2bin (Q40_RTC_SECS);
288 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
292 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
299 unsigned int q40_get_ss()
301 return bcd2bin(Q40_RTC_SECS);
305 * Set the minutes and seconds from seconds value 'nowtime'. Fail if
306 * clock is out by > 30 minutes. Logic lifted from atari code.
309 int q40_set_clock_mmss (unsigned long nowtime)
312 short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
317 rtc_minutes = bcd2bin (Q40_RTC_MINS);
319 if ((rtc_minutes < real_minutes
320 ? real_minutes - rtc_minutes
321 : rtc_minutes - real_minutes) < 30)
323 Q40_RTC_CTRL |= Q40_RTC_WRITE;
324 Q40_RTC_MINS = bin2bcd(real_minutes);
325 Q40_RTC_SECS = bin2bcd(real_seconds);
326 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
336 /* get and set PLL calibration of RTC clock */
337 #define Q40_RTC_PLL_MASK ((1<<5)-1)
338 #define Q40_RTC_PLL_SIGN (1<<5)
340 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
342 int tmp=Q40_RTC_CTRL;
343 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
344 if (tmp & Q40_RTC_PLL_SIGN)
345 pll->pll_value = -pll->pll_value;
348 pll->pll_posmult=512;
349 pll->pll_negmult=256;
350 pll->pll_clock=125829120;
354 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
357 /* the docs are a bit unclear so I am doublesetting */
358 /* RTC_WRITE here ... */
359 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
361 Q40_RTC_CTRL |= Q40_RTC_WRITE;
363 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);