1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF5206e ColdFire based CADRE3 boards.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
8 * 1999/02/24 Modified for the 5307 processor David W. Miller
11 /*****************************************************************************/
13 #include "linux/autoconf.h"
14 #include "asm/coldfire.h"
15 #include "asm/mcfsim.h"
17 /*****************************************************************************/
20 * Cadre-III M5206e ColdFire eval board, chip select and memory setup.
23 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
24 #define VBR_BASE MEM_BASE /* Vector address */
26 /*****************************************************************************/
34 /*****************************************************************************/
39 * Set up the usable of RAM stuff. Size of RAM is determined then
40 * an initial stack set up at the end.
51 /*****************************************************************************/
56 * This is the codes first entry point. This is where it all
62 move.w #0x2700, %sr /* No interrupts */
65 * Setup VBR here, otherwise buserror remap will not work.
66 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
70 * Note: this is because dBUG points VBR to ROM, making vectors read
71 * only, so the bus trap can't be changed. (RS)
73 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
75 move.l %a7, _ramvec /* Set up vector addr */
76 move.l %a7, _rambase /* Set up base RAM addr */
80 * SDRAM size for the Cadre III board (m5206e).
82 #if defined(CONFIG_RAMAUTO)
83 movea.l #0x00000000,%a0
84 move.l MCF_MBAR+MCFSIM_DCMR0,%d0
85 and.l #0x00fe0000, %d0
90 move.l MCF_MBAR+MCFSIM_DCMR1,%d0
91 and.l #0x00fe0000, %d0
99 #if defined(CONFIG_RAM32MB)
100 #define MEM_SIZE 0x02000000 /* Memory size 32Mb */
101 #elif defined(CONFIG_RAM16MB)
102 #define MEM_SIZE 0x01000000 /* Memory size 16Mb */
103 #elif defined(CONFIG_RAM8MB)
104 #define MEM_SIZE 0x00800000 /* Memory size 8Mb */
106 #define MEM_SIZE 0x00400000 /* Memory size 4Mb */
108 move.l #MEM_SIZE, %a0
111 move.l %a0, %d0 /* Mem end addr is in a0 */
112 move.l %d0, %sp /* Set up initial stack ptr */
113 move.l %d0, _ramend /* Set end ram addr */
117 * Enable CPU internal cache.
119 move.l #0x01000000, %d0 /* Invalidate cache cmd */
120 movec %d0, %CACR /* Invalidate cache */
121 move.l #0x80000100, %d0 /* Setup cache mask */
122 movec %d0, %CACR /* Enable cache */
125 #ifdef CONFIG_ROMFS_FS
127 * Move ROM filesystem above bss :-)
129 lea.l _sbss, %a0 /* Get start of bss */
130 lea.l _ebss, %a1 /* Set up destination */
131 move.l %a0, %a2 /* Copy of bss start */
133 move.l 8(%a0), %d0 /* Get size of ROMFS */
134 addq.l #8, %d0 /* Allow for rounding */
135 and.l #0xfffffffc, %d0 /* Whole words */
137 add.l %d0, %a0 /* Copy from end */
138 add.l %d0, %a1 /* Copy from end */
139 move.l %a1, _ramstart /* Set start of ram */
142 move.l -(%a0), %d0 /* Copy dword */
144 cmp.l %a0, %a2 /* Check if at end */
147 #else /* CONFIG_ROMFS_FS */
149 move.l %a1, _ramstart
150 #endif /* CONFIG_ROMFS_FS */
154 * Zero out the bss region.
156 lea.l _sbss, %a0 /* Get start of bss */
157 lea.l _ebss, %a1 /* Get end of bss */
158 clr.l %d0 /* Set value */
160 move.l %d0, (%a0)+ /* Clear each word */
161 cmp.l %a0, %a1 /* Check if at end */
165 * Load the current task pointer and stack.
167 lea init_thread_union, %a0
171 * Assember start up done, start code proper.
173 jsr start_kernel /* Start Linux kernel */
176 jmp _exit /* Should never get here */
178 /*****************************************************************************/