1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF5307 ColdFire based MP3.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
7 * Copyright (C) 2000-2001 Lineo Inc. (www.lineo.com)
9 * 1999/02/24 Modified for the 5307 processor David W. Miller
12 /*****************************************************************************/
14 #include "linux/autoconf.h"
15 #include "asm/coldfire.h"
16 #include "asm/mcfsim.h"
17 #include "asm/nettel.h"
19 /*****************************************************************************/
22 * SnapGear/NETtel board memory setup.
24 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
25 #define VBR_BASE MEM_BASE /* Vector address */
27 #if defined(CONFIG_RAM16MB)
28 #define MEM_SIZE 0x01000000 /* Memory size 16Mb */
30 #define MEM_SIZE 0x00800000 /* Memory size 8Mb */
33 /*****************************************************************************/
41 /*****************************************************************************/
46 * Set up the usable of RAM stuff. Size of RAM is determined then
47 * an initial stack set up at the end.
58 /*****************************************************************************/
63 * This is the codes first entry point. This is where it all
69 move.w #0x2700, %sr /* No interrupts */
72 * Disable watchdog timer.
74 move.l #MCF_MBAR, %a0 /* Get MBAR address */
75 clr.l %d0 /* Disable SWT */
76 move.b %d0, MCFSIM_SYPCR(%a0)
77 move.b #0x55, %d0 /* Clear SWT as well */
78 move.b %d0, MCFSIM_SWSR(%a0)
80 move.b %d0, MCFSIM_SWSR(%a0)
81 move.l #0xffffffff, %d0 /* Mask out all interrupts */
82 move.l %d0, MCFSIM_IMR(%a0)
85 * Setup VBR here, otherwise buserror remap will not work.
86 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
90 * Note: this is because dBUG points VBR to ROM, making vectors read
91 * only, so the bus trap can't be changed. (RS)
93 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
95 move.l %a7, _ramvec /* Set up vector addr */
96 move.l %a7, _rambase /* Set up base RAM addr */
100 * Determine size of RAM, then set up initial stack.
102 move.l #MEM_SIZE, %a0
104 move.l %a0, %d0 /* Mem end addr is in a0 */
105 move.l %d0, %sp /* Set up initial stack ptr */
106 move.l %d0, _ramend /* Set end ram addr */
109 * Enable CPU internal cache.
111 move.l #0x01000000, %d0 /* invalidate whole cache */
115 /* MUST be write-through for DMA to work... */
116 /* This also makes this debugger safe */
117 move.l #0x0000c000, %d0 /* Set SDRAM cached only */
119 move.l #0x00000000, %d0 /* No other regions cached */
123 move.l #0xa0000200, %d0
128 #ifdef CONFIG_ROMFS_FS
130 * Move ROM filesystem above bss :-)
132 lea.l _sbss, %a0 /* Get start of bss */
133 lea.l _ebss, %a1 /* Set up destination */
134 move.l %a0, %a2 /* Copy of bss start */
136 move.l 8(%a0), %d0 /* Get size of ROMFS */
137 addq.l #8, %d0 /* Allow for rounding */
138 and.l #0xfffffffc, %d0 /* Whole words */
140 add.l %d0, %a0 /* Copy from end */
141 add.l %d0, %a1 /* Copy from end */
142 move.l %a1, _ramstart /* Set start of ram */
145 move.l -(%a0), %d0 /* Copy dword */
147 cmp.l %a0, %a2 /* Check if at end */
150 #else /* CONFIG_ROMFS_FS */
152 move.l %a1, _ramstart
153 #endif /* CONFIG_ROMFS_FS */
157 * Zero out the bss region.
159 lea.l _sbss, %a0 /* Get start of bss */
160 lea.l _ebss, %a1 /* Get end of bss */
161 clr.l %d0 /* Set value */
163 move.l %d0, (%a0)+ /* Clear each word */
164 cmp.l %a0, %a1 /* Check if at end */
168 * load the current task pointer and stack
170 lea init_thread_union, %a0
174 * Assember start up done, start code proper.
176 jsr start_kernel /* Start Linux kernel */
179 jmp _exit /* Should never get here */
181 /*****************************************************************************/