1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for Feith Cleopatra 2 board.
6 * (C) Copyright 2001, Roman Wagner.
8 * 1999/02/24 Modified for the 5307 processor David W. Miller
11 /*****************************************************************************/
13 #include "linux/autoconf.h"
14 #include "asm/coldfire.h"
15 #include "asm/mcfsim.h"
17 /*****************************************************************************/
20 * Feith CLEOPATRA board, chip select and memory setup.
23 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
24 #define VBR_BASE MEM_BASE /* Vector address */
26 #define MEM_SIZE 0x01000000 /* Memory size 16Mb */
28 /*****************************************************************************/
36 /*****************************************************************************/
41 * Set up the usable of RAM stuff. Size of RAM is determined then
42 * an initial stack set up at the end.
53 /*****************************************************************************/
58 * This is the codes first entry point. This is where it all
64 move.w #0x2700, %sr /* No interrupts */
68 * Setup VBR here, otherwise buserror remap will not work.
69 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
73 * Note: this is because dBUG points VBR to ROM, making vectors read
74 * only, so the bus trap can't be changed. (RS)
76 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
78 move.l %a7, _ramvec /* Set up vector addr */
79 move.l %a7, _rambase /* Set up base RAM addr */
82 * Determine size of RAM, then set up initial stack.
85 * The current version of the 5307 processor
86 * SWT does not work. Probing invalid addresses
87 * will hang the system.
89 * For now, set the memory size to 8 meg
93 move.l %a0, %d0 /* Mem end addr is in a0 */
94 move.l %d0, %sp /* Set up initial stack ptr */
95 move.l %d0, _ramend /* Set end ram addr */
99 * Enable CPU internal cache.
101 move.l #0x01040100, %d0 /* Invalidate whole cache */
105 /* make region ROM cachable (turn off for flash programming?) */
106 /* 0xff000000 - 0xffffffff */
107 move.l #(0xff<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_CP+ACR_WPROTECT,%d0
110 /* make region RAM cachable */
111 /* 0x00000000 - 0x00ffffffff */
112 move.l #(0x00<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_CP,%d0
115 move.l #(0xff<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_CP+ACR_WPROTECT,%d0
118 move.l #(0x00<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_CP,%d0
122 move.l #0xa4098400, %d0 /* Write buffer, dflt precise */
127 #ifdef CONFIG_ROMFS_FS
129 * Move ROM filesystem above bss :-)
131 lea.l _sbss, %a0 /* Get start of bss */
132 lea.l _ebss, %a1 /* Set up destination */
133 move.l %a0, %a2 /* Copy of bss start */
135 move.l 8(%a0), %d0 /* Get size of ROMFS */
136 addq.l #8, %d0 /* Allow for rounding */
137 and.l #0xfffffffc, %d0 /* Whole words */
139 add.l %d0, %a0 /* Copy from end */
140 add.l %d0, %a1 /* Copy from end */
141 move.l %a1, _ramstart /* Set start of ram */
144 move.l -(%a0), %d0 /* Copy dword */
146 cmp.l %a0, %a2 /* Check if at end */
149 #else /* CONFIG_ROMFS_FS */
151 move.l %a1, _ramstart
152 #endif /* CONFIG_ROMFS_FS */
156 * Zero out the bss region.
158 lea.l _sbss, %a0 /* Get start of bss */
159 lea.l _ebss, %a1 /* Get end of bss */
160 clr.l %d0 /* Set value */
162 move.l %d0, (%a0)+ /* Clear each word */
163 cmp.l %a0, %a1 /* Check if at end */
167 * Load the current task pointer and stack.
169 lea init_thread_union, %a0
173 * Assember start up done, start code proper.
175 jsr start_kernel /* Start Linux kernel */
178 jmp _exit /* Should never get here */
180 /*****************************************************************************/