3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
4 * Copied and modified Carsten Langgaard's time.c
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
26 * Setting up the clock on the MIPS boards.
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
35 #include <linux/types.h>
36 #include <linux/config.h>
37 #include <linux/init.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/sched.h>
40 #include <linux/spinlock.h>
42 #include <asm/mipsregs.h>
43 #include <asm/ptrace.h>
45 #include <asm/hardirq.h>
46 #include <asm/div64.h>
47 #include <asm/mach-au1x00/au1000.h>
49 #include <linux/mc146818rtc.h>
50 #include <linux/timex.h>
52 extern void startup_match20_interrupt(void);
53 extern void do_softirq(void);
54 extern volatile unsigned long wall_jiffies;
55 unsigned long missed_heart_beats = 0;
57 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
58 static unsigned long r4k_cur; /* What counter should be at next timer irq */
60 void (*au1k_wait_ptr)(void);
62 /* Cycle counter value at the previous timer interrupt.. */
63 static unsigned int timerhi = 0, timerlo = 0;
66 #define MATCH20_INC 328
67 extern void startup_match20_interrupt(void);
68 static unsigned long last_pc0, last_match20;
71 static spinlock_t time_lock = SPIN_LOCK_UNLOCKED;
73 static inline void ack_r4ktimer(unsigned long newval)
75 write_c0_compare(newval);
79 * There are a lot of conceptually broken versions of the MIPS timer interrupt
80 * handler floating around. This one is rather different, but the algorithm
81 * is provably more robust.
84 void mips_timer_interrupt(struct pt_regs *regs)
90 kstat_this_cpu.irqs[irq]++;
96 count = read_c0_count();
97 timerhi += (count < timerlo); /* Wrap around */
100 kstat_this_cpu.irqs[irq]++;
102 r4k_cur += r4k_offset;
103 ack_r4ktimer(r4k_cur);
105 } while (((unsigned long)read_c0_count()
106 - r4k_cur) < 0x7fffffff);
116 void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
120 static int jiffie_drift = 0;
122 kstat.irqs[0][irq]++;
123 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
124 /* should never happen! */
125 printk(KERN_WARNING "counter 0 w status eror\n");
129 pc0 = au_readl(SYS_TOYREAD);
130 if (pc0 < last_match20) {
131 /* counter overflowed */
132 time_elapsed = (0xffffffff - last_match20) + pc0;
135 time_elapsed = pc0 - last_match20;
138 while (time_elapsed > 0) {
140 time_elapsed -= MATCH20_INC;
141 last_match20 += MATCH20_INC;
146 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
149 /* our counter ticks at 10.009765625 ms/tick, we we're running
150 * almost 10uS too slow per tick.
153 if (jiffie_drift >= 999) {
155 do_timer(regs); /* increment jiffies by one */
159 /* When we wakeup from sleep, we have to "catch up" on all of the
160 * timer ticks we have missed.
163 wakeup_counter0_adjust(void)
168 pc0 = au_readl(SYS_TOYREAD);
169 if (pc0 < last_match20) {
170 /* counter overflowed */
171 time_elapsed = (0xffffffff - last_match20) + pc0;
174 time_elapsed = pc0 - last_match20;
177 while (time_elapsed > 0) {
178 time_elapsed -= MATCH20_INC;
179 last_match20 += MATCH20_INC;
183 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
188 /* This is just for debugging to set the timer for a sleep delay.
191 wakeup_counter0_set(int ticks)
195 pc0 = au_readl(SYS_TOYREAD);
197 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
202 /* I haven't found anyone that doesn't use a 12 MHz source clock,
203 * but just in case.....
205 #ifdef CONFIG_AU1000_SRC_CLK
206 #define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
208 #define AU1000_SRC_CLK 12000000
212 * We read the real processor speed from the PLL. This is important
213 * because it is more accurate than computing it from the 32KHz
214 * counter, if it exists. If we don't have an accurate processor
215 * speed, all of the peripherals that derive their clocks based on
216 * this advertised speed will introduce error and sometimes not work
217 * properly. This function is futher convoluted to still allow configurations
218 * to do that in case they have really, really old silicon with a
219 * write-only PLL register, that we need the 32KHz when power management
220 * "wait" is enabled, and we need to detect if the 32KHz isn't present
221 * but requested......got it? :-) -- Dan
223 unsigned long cal_r4koff(void)
226 unsigned long cpu_speed;
228 unsigned long counter;
230 spin_lock_irqsave(&time_lock, flags);
232 /* Power management cares if we don't have a 32KHz counter.
235 counter = au_readl(SYS_COUNTER_CNTRL);
236 if (counter & SYS_CNTRL_E0) {
237 int trim_divide = 16;
239 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
241 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
242 /* RTC now ticks at 32.768/16 kHz */
243 au_writel(trim_divide-1, SYS_RTCTRIM);
244 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
246 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
247 au_writel (0, SYS_TOYWRITE);
248 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
250 #if defined(CONFIG_AU1000_USE32K)
252 unsigned long start, end;
254 start = au_readl(SYS_RTCREAD);
256 /* wait for the beginning of a new tick
258 while (au_readl(SYS_RTCREAD) < start);
260 /* Start r4k counter.
266 end = start + (32768 / trim_divide)/2;
268 while (end > au_readl(SYS_RTCREAD));
270 count = read_c0_count();
271 cpu_speed = count * 2;
274 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
276 count = cpu_speed / 2;
280 /* The 32KHz oscillator isn't running, so assume there
281 * isn't one and grab the processor speed from the PLL.
282 * NOTE: some old silicon doesn't allow reading the PLL.
284 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
285 count = cpu_speed / 2;
288 mips_hpt_frequency = count;
289 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
290 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
291 spin_unlock_irqrestore(&time_lock, flags);
292 return (cpu_speed / HZ);
295 /* This is for machines which generate the exact clock. */
296 #define USECS_PER_JIFFY (1000000/HZ)
297 #define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
301 div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
304 do_div64_32(r0, v1, v2, v3);
308 static unsigned long do_fast_cp0_gettimeoffset(void)
311 unsigned long res, tmp;
314 /* Last jiffy when do_fast_gettimeoffset() was called. */
315 static unsigned long last_jiffies=0;
316 unsigned long quotient;
319 * Cached "1/(clocks per usec)*2^32" value.
320 * It has to be recalculated once each jiffy.
322 static unsigned long cached_quotient=0;
326 quotient = cached_quotient;
328 if (tmp && last_jiffies != tmp) {
330 if (last_jiffies != 0) {
331 r0 = div64_32(timerhi, timerlo, tmp);
332 quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
333 cached_quotient = quotient;
337 /* Get last timer tick in absolute kernel time */
338 count = read_c0_count();
340 /* .. relative to previous jiffy (32 bits is enough) */
343 __asm__("multu\t%1,%2\n\t"
350 * Due to possible jiffies inconsistencies, we need to check
351 * the result so that we'll get a timer that is monotonic.
353 if (res >= USECS_PER_JIFFY)
354 res = USECS_PER_JIFFY-1;
360 static unsigned long do_fast_pm_gettimeoffset(void)
363 unsigned long offset;
365 pc0 = au_readl(SYS_TOYREAD);
367 offset = pc0 - last_pc0;
368 if (offset > 2*MATCH20_INC) {
369 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
370 (unsigned)offset, (unsigned)last_pc0,
371 (unsigned)last_match20, (unsigned)pc0);
373 offset = (unsigned long)((offset * 305) / 10);
378 void au1xxx_timer_setup(struct irqaction *irq)
380 unsigned int est_freq;
381 extern unsigned long (*do_gettimeoffset)(void);
382 extern void au1k_wait(void);
384 printk("calculating r4koff... ");
385 r4k_offset = cal_r4koff();
386 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
388 //est_freq = 2*r4k_offset*HZ;
389 est_freq = r4k_offset*HZ;
390 est_freq += 5000; /* round */
391 est_freq -= est_freq%10000;
392 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
393 (est_freq%1000000)*100/1000000);
394 set_au1x00_speed(est_freq);
395 set_au1x00_lcd_clock(); // program the LCD clock
397 r4k_cur = (read_c0_count() + r4k_offset);
398 write_c0_compare(r4k_cur);
400 /* no RTC on the pb1000 */
406 * setup counter 0, since it keeps ticking after a
407 * 'wait' instruction has been executed. The CP0 timer and
408 * counter 1 do NOT continue running after 'wait'
410 * It's too early to call request_irq() here, so we handle
411 * counter 0 interrupt as a special irq and it doesn't show
412 * up under /proc/interrupts.
414 * Check to ensure we really have a 32KHz oscillator before
417 if (no_au1xxx_32khz) {
418 unsigned int c0_status;
420 printk("WARNING: no 32KHz clock found.\n");
421 do_gettimeoffset = do_fast_cp0_gettimeoffset;
423 /* Ensure we get CPO_COUNTER interrupts.
425 c0_status = read_c0_status();
426 c0_status |= IE_IRQ5;
427 write_c0_status(c0_status);
430 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
431 au_writel(0, SYS_TOYWRITE);
432 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
434 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
435 au_writel(~0, SYS_WAKESRC);
437 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
439 /* setup match20 to interrupt once every 10ms */
440 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
441 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
443 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
444 startup_match20_interrupt();
446 do_gettimeoffset = do_fast_pm_gettimeoffset;
448 /* We can use the real 'wait' instruction.
450 au1k_wait_ptr = au1k_wait;
454 /* We have to do this here instead of in timer_init because
455 * the generic code in arch/mips/kernel/time.c will write
456 * over our function pointer.
458 do_gettimeoffset = do_fast_cp0_gettimeoffset;
462 void __init au1xxx_time_init(void)