2 * bagetIRQ.S: Interrupt exception dispatch code for Baget/MIPS
4 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
7 #include <asm/mipsregs.h>
8 #include <asm/regdef.h>
9 #include <asm/stackframe.h>
10 #include <asm/addrspace.h>
19 NESTED(bagetIRQ, PT_SIZE, sp)
21 CLI # Important: mark KERNEL mode !
23 la a1, baget_interrupt
34 #define DBE_HANDLER 0x1C
36 NESTED(try_read, PT_SIZE, sp)
37 mfc0 t3, CP0_STATUS # save flags and
38 CLI # disable interrupts
41 sltu t1, t0, a0 # Is it KSEG2 address ?
42 beqz t1, mapped # No - already mapped !
46 xori t0, 0xfff # round address to page
48 ori t1, t0, 0xf00 # prepare EntryLo (N,V,D,G)
50 mfc0 t2, CP0_ENTRYHI # save ASID value
52 mtc0 t0, CP0_ENTRYHI # Load MMU values ...
54 nop # let it understand
56 tlbwi # ... and write ones
62 la t0, exception_handlers
63 lw t1, DBE_HANDLER(t0) # save real handler
65 sw t2, DBE_HANDLER(t0) # set temporary local handler
66 li v0, -1 # default (failure) value
76 1: lbu v0, (a0) # byte
79 2: lhu v0, (a0) # short
85 sw t1, DBE_HANDLER(t0) # restore real handler
86 mtc0 t3, CP0_STATUS # restore CPU flags
90 li v0, -1 # mark our failure
93 b out # "no problems !"
94 rfe # return from trap