3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 * arch/mips/ddb5xxx/ddb5477/setup.c
9 * Setup file for DDB5477.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/pci.h>
22 #include <linux/ide.h>
24 #include <linux/ioport.h>
25 #include <linux/param.h> /* for HZ */
26 #include <linux/major.h>
27 #include <linux/kdev_t.h>
28 #include <linux/root_dev.h>
31 #include <asm/bootinfo.h>
32 #include <asm/addrspace.h>
34 #include <asm/bcache.h>
36 #include <asm/reboot.h>
37 #include <asm/gdb-stub.h>
38 #include <asm/traps.h>
39 #include <asm/debug.h>
41 #include <asm/ddb5xxx/ddb5xxx.h>
46 #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
48 #define SP_TIMER_BASE DDB_SPT1CTRL_L
49 #define SP_TIMER_IRQ VRC5477_IRQ_SPT1
51 static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
53 static void ddb_machine_restart(char *command)
55 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
63 t = ddb_in32(DDB_CPUSTAT);
65 ddb_out32(DDB_CPUSTAT, t);
71 static void ddb_machine_halt(void)
73 printk("DDB Vrc-5477 halted.\n");
77 static void ddb_machine_power_off(void)
79 printk("DDB Vrc-5477 halted. Please turn off the power.\n");
83 extern void rtc_ds1386_init(unsigned long base);
85 static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
92 ddb_out32(SP_TIMER_BASE, 0xffffffff);
93 ddb_out32(SP_TIMER_BASE+4, 0x1);
94 ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
96 /* check if rtc is running */
97 c= *(volatile unsigned char*)rtc_base;
98 for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
99 if (c == *(volatile unsigned char*)rtc_base) {
100 printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
104 c= *(volatile unsigned char*)rtc_base;
105 while (c == *(volatile unsigned char*)rtc_base);
106 /* we are now at the turn of 1/100th second, if no error. */
107 t1 = ddb_in32(SP_TIMER_BASE+8);
109 for (i=0; i< 10; i++) {
110 c= *(volatile unsigned char*)rtc_base;
111 while (c == *(volatile unsigned char*)rtc_base);
112 /* we are now at the turn of another 1/100th second */
113 t2 = ddb_in32(SP_TIMER_BASE+8);
116 ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
119 printk("DDB bus frequency detection : %u \n", freq);
123 static void __init ddb_time_init(void)
125 unsigned long rtc_base;
128 /* we have ds1396 RTC chip */
129 if (mips_machtype == MACH_NEC_ROCKHOPPER
130 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
131 rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
133 rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
135 rtc_ds1386_init(rtc_base);
137 /* do we need to do run-time detection of bus speed? */
138 if (bus_frequency == 0) {
139 bus_frequency = detect_bus_frequency(rtc_base);
142 /* mips_hpt_frequency is 1/2 of the cpu core freq */
143 i = (read_c0_config() >> 28 ) & 7;
144 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
146 mips_hpt_frequency = bus_frequency*(i+4)/4;
149 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
151 static void __init ddb_timer_setup(struct irqaction *irq)
153 #if defined(USE_CPU_COUNTER_TIMER)
155 /* we are using the cpu counter for timer interrupts */
156 setup_irq(CPU_IRQ_BASE + 7, irq);
160 /* if we use Special purpose timer 1 */
161 ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
162 ddb_out32(SP_TIMER_BASE+4, 0x1);
163 setup_irq(SP_TIMER_IRQ, irq);
168 static void ddb5477_board_init(void);
170 extern struct pci_controller ddb5477_ext_controller;
171 extern struct pci_controller ddb5477_io_controller;
173 static int ddb5477_setup(void)
175 extern int panic_timeout;
177 /* initialize board - we don't trust the loader */
178 ddb5477_board_init();
180 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
182 board_time_init = ddb_time_init;
183 board_timer_setup = ddb_timer_setup;
185 _machine_restart = ddb_machine_restart;
186 _machine_halt = ddb_machine_halt;
187 _machine_power_off = ddb_machine_power_off;
189 /* setup resource limits */
190 ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
191 iomem_resource.end = 0xffffffff;
193 /* Reboot on panic */
196 register_pci_controller (&ddb5477_ext_controller);
197 register_pci_controller (&ddb5477_io_controller);
202 early_initcall(ddb5477_setup);
204 static void __init ddb5477_board_init(void)
206 /* ----------- setup PDARs ------------ */
208 /* SDRAM should have been set */
209 db_assert(ddb_in32(DDB_SDRAM0) ==
210 ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
212 /* SDRAM1 should be turned off. What is this for anyway ? */
213 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
215 /* Setup local bus. */
217 /* Flash U12 PDAR and timing. */
218 ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
219 ddb_out32(DDB_LCST0, 0x00090842);
221 /* We need to setup LCS1 and LCS2 differently based on the
223 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
224 /* Flash U13 PDAR and timing. */
225 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
226 ddb_out32(DDB_LCST1, 0x00090842);
228 /* EPLD (NVRAM, switch, LCD, and mezzanie). */
229 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
232 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
234 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
237 /* verify VRC5477 base addr */
238 db_assert(ddb_in32(DDB_VRC5477) ==
239 ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
241 /* verify BOOT ROM addr */
242 db_assert(ddb_in32(DDB_BOOTCS) ==
243 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
245 /* setup PCI windows - window0 for MEM/config, window1 for IO */
246 ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
247 ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
248 ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
249 ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
251 /* ------------ reset PCI bus and BARs ----------------- */
254 ddb_out32(DDB_BARM010, 0x00000008);
255 ddb_out32(DDB_BARM011, 0x00000008);
257 ddb_out32(DDB_BARC0, 0xffffffff);
258 ddb_out32(DDB_BARM230, 0xffffffff);
259 ddb_out32(DDB_BAR00, 0xffffffff);
260 ddb_out32(DDB_BAR10, 0xffffffff);
261 ddb_out32(DDB_BAR20, 0xffffffff);
262 ddb_out32(DDB_BAR30, 0xffffffff);
263 ddb_out32(DDB_BAR40, 0xffffffff);
264 ddb_out32(DDB_BAR50, 0xffffffff);
265 ddb_out32(DDB_BARB0, 0xffffffff);
267 ddb_out32(DDB_BARC1, 0xffffffff);
268 ddb_out32(DDB_BARM231, 0xffffffff);
269 ddb_out32(DDB_BAR01, 0xffffffff);
270 ddb_out32(DDB_BAR11, 0xffffffff);
271 ddb_out32(DDB_BAR21, 0xffffffff);
272 ddb_out32(DDB_BAR31, 0xffffffff);
273 ddb_out32(DDB_BAR41, 0xffffffff);
274 ddb_out32(DDB_BAR51, 0xffffffff);
275 ddb_out32(DDB_BARB1, 0xffffffff);
278 * We use pci master register 0 for memory space / config space
279 * And we use register 1 for IO space.
280 * Note that for memory space, we bump up the pci base address
281 * so that we have 1:1 mapping between PCI memory and cpu physical.
282 * For PCI IO space, it starts from 0 in PCI IO space but with
283 * DDB_xx_IO_BASE in CPU physical address space.
285 ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
287 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
289 ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
291 ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
295 /* PCI cross window should be set properly */
296 ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
297 ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
298 ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
299 ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
301 if (mips_machtype == MACH_NEC_ROCKHOPPER
302 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
303 /* Disable bus diagnostics. */
304 ddb_out32(DDB_PCICTL0_L, 0);
305 ddb_out32(DDB_PCICTL0_H, 0);
306 ddb_out32(DDB_PCICTL1_L, 0);
307 ddb_out32(DDB_PCICTL1_H, 0);
310 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
313 struct pci_dev dev_m1533;
314 extern struct pci_ops ddb5477_ext_pci_ops;
316 bus.parent = NULL; /* we scan the top level only */
317 bus.ops = &ddb5477_ext_pci_ops;
318 dev_m1533.bus = &bus;
319 dev_m1533.sysdata = NULL;
320 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
321 pci_read_config_word(&dev_m1533, 0, &vid);
322 if (vid == PCI_VENDOR_ID_AL) {
323 printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
324 mips_machtype = MACH_NEC_ROCKHOPPERII;
328 /* enable USB input buffers */
329 ddb_out32(DDB_PIBMISC, 0x00000007);
331 /* For dual-function pins, make them all non-GPIO */
332 ddb_out32(DDB_GIUFUNSEL, 0x0);
333 // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
335 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
337 /* enable IDE controller on Ali chip (south bridge) */
340 struct pci_dev dev_m1533;
341 struct pci_dev dev_m5229;
342 extern struct pci_ops ddb5477_ext_pci_ops;
344 /* Setup M1535 registers */
345 bus.parent = NULL; /* we scan the top level only */
346 bus.ops = &ddb5477_ext_pci_ops;
347 dev_m1533.bus = &bus;
348 dev_m1533.sysdata = NULL;
349 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
351 /* setup IDE controller
352 * enable IDE controller (bit 6 - 1)
353 * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
354 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
355 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
357 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
360 * positive decode (bit6 -0)
361 * enable IDE controler interrupt (bit 4 -1)
362 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
364 pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
366 /* Setup M5229 registers */
367 dev_m5229.bus = &bus;
368 dev_m5229.sysdata = NULL;
369 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
372 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
373 * M5229 IDSEL is addr:15; see above setting
375 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
376 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
379 * enable bus master (bit 2) and IO decoding (bit 0)
381 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
382 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
385 * enable native, copied from arch/ppc/k2boot/head.S
386 * TODO - need volatile, need to be portable
388 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
390 /* Set Primary Channel Command Block Timing */
391 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
394 * Enable primary channel 40-pin cable
395 * M5229 register 0x4a (bit 0)
397 pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
398 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
401 if (mips_machtype == MACH_NEC_ROCKHOPPER
402 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
403 printk("lcd44780: initializing\n");
405 lcd44780_puts("MontaVista Linux");