2 * BRIEF MODULE DESCRIPTION
3 * ITE 8172G interrupt/setup routines.
5 * Copyright 2000,2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
9 * Part of this file was derived from Carsten Langgaard's
10 * arch/mips/mips-boards/atlas/atlas_int.c.
12 * Carsten Langgaard, carstenl@mips.com
13 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/config.h>
36 #include <linux/errno.h>
37 #include <linux/init.h>
38 #include <linux/irq.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/module.h>
41 #include <linux/signal.h>
42 #include <linux/sched.h>
43 #include <linux/types.h>
44 #include <linux/interrupt.h>
45 #include <linux/ioport.h>
46 #include <linux/timex.h>
47 #include <linux/slab.h>
48 #include <linux/random.h>
49 #include <linux/serial_reg.h>
51 #include <asm/bitops.h>
52 #include <asm/bootinfo.h>
54 #include <asm/mipsregs.h>
55 #include <asm/system.h>
56 #include <asm/it8172/it8172.h>
57 #include <asm/it8172/it8172_int.h>
58 #include <asm/it8172/it8172_dbg.h>
62 /* note: prints function name for you */
63 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
65 #define DPRINTK(fmt, args...)
69 extern void breakpoint(void);
73 #define EXT_IRQ0_TO_IP 2 /* IP 2 */
74 #define EXT_IRQ5_TO_IP 7 /* IP 7 */
76 #define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
78 void disable_it8172_irq(unsigned int irq_nr);
79 void enable_it8172_irq(unsigned int irq_nr);
81 extern void set_debug_traps(void);
82 extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
83 extern asmlinkage void it8172_IRQ(void);
85 struct it8172_intc_regs volatile *it8172_hw0_icregs =
86 (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
88 /* Function for careful CP0 interrupt mask access */
89 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
91 unsigned long status = read_c0_status();
92 status &= ~((clr_mask & 0xFF) << 8);
93 status |= (set_mask & 0xFF) << 8;
94 write_c0_status(status);
97 static inline void mask_irq(unsigned int irq_nr)
99 modify_cp0_intmask(irq_nr, 0);
102 static inline void unmask_irq(unsigned int irq_nr)
104 modify_cp0_intmask(0, irq_nr);
107 void local_disable_irq(unsigned int irq_nr)
111 local_irq_save(flags);
112 disable_it8172_irq(irq_nr);
113 local_irq_restore(flags);
116 void local_enable_irq(unsigned int irq_nr)
120 local_irq_save(flags);
121 enable_it8172_irq(irq_nr);
122 local_irq_restore(flags);
126 void disable_it8172_irq(unsigned int irq_nr)
128 DPRINTK("disable_it8172_irq %d\n", irq_nr);
130 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
132 DPRINTK("DB lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
133 it8172_hw0_icregs->lpc_mask |=
134 (1 << (irq_nr - IT8172_LPC_IRQ_BASE));
135 DPRINTK("DA lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
137 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
138 /* Local Bus interrupt */
139 DPRINTK("DB lb_mask %x\n", it8172_hw0_icregs->lb_mask);
140 it8172_hw0_icregs->lb_mask |=
141 (1 << (irq_nr - IT8172_LB_IRQ_BASE));
142 DPRINTK("DA lb_mask %x\n", it8172_hw0_icregs->lb_mask);
144 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
145 /* PCI and other interrupts */
146 DPRINTK("DB pci_mask %x\n", it8172_hw0_icregs->pci_mask);
147 it8172_hw0_icregs->pci_mask |=
148 (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
149 DPRINTK("DA pci_mask %x\n", it8172_hw0_icregs->pci_mask);
151 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
153 DPRINTK("DB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
154 it8172_hw0_icregs->nmi_mask |=
155 (1 << (irq_nr - IT8172_NMI_IRQ_BASE));
156 DPRINTK("DA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
159 panic("disable_it8172_irq: bad irq %d", irq_nr);
163 void enable_it8172_irq(unsigned int irq_nr)
165 DPRINTK("enable_it8172_irq %d\n", irq_nr);
166 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
168 DPRINTK("EB before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
169 it8172_hw0_icregs->lpc_mask &=
170 ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
171 DPRINTK("EA after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
173 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
174 /* Local Bus interrupt */
175 DPRINTK("EB lb_mask %x\n", it8172_hw0_icregs->lb_mask);
176 it8172_hw0_icregs->lb_mask &=
177 ~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
178 DPRINTK("EA lb_mask %x\n", it8172_hw0_icregs->lb_mask);
180 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
181 /* PCI and other interrupts */
182 DPRINTK("EB pci_mask %x\n", it8172_hw0_icregs->pci_mask);
183 it8172_hw0_icregs->pci_mask &=
184 ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
185 DPRINTK("EA pci_mask %x\n", it8172_hw0_icregs->pci_mask);
187 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
189 DPRINTK("EB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
190 it8172_hw0_icregs->nmi_mask &=
191 ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
192 DPRINTK("EA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
195 panic("enable_it8172_irq: bad irq %d", irq_nr);
199 static unsigned int startup_ite_irq(unsigned int irq)
201 enable_it8172_irq(irq);
205 #define shutdown_ite_irq disable_it8172_irq
206 #define mask_and_ack_ite_irq disable_it8172_irq
208 static void end_ite_irq(unsigned int irq)
210 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
211 enable_it8172_irq(irq);
214 static struct hw_interrupt_type it8172_irq_type = {
220 mask_and_ack_ite_irq,
226 static void enable_none(unsigned int irq) { }
227 static unsigned int startup_none(unsigned int irq) { return 0; }
228 static void disable_none(unsigned int irq) { }
229 static void ack_none(unsigned int irq) { }
231 /* startup is the same as "enable", shutdown is same as "disable" */
232 #define shutdown_none disable_none
233 #define end_none enable_none
235 static struct hw_interrupt_type cp0_irq_type = {
245 void enable_cpu_timer(void)
249 local_irq_save(flags);
250 unmask_irq(1<<EXT_IRQ5_TO_IP); /* timer interrupt */
251 local_irq_restore(flags);
254 void __init init_IRQ(void)
259 memset(irq_desc, 0, sizeof(irq_desc));
260 set_except_vector(0, it8172_IRQ);
264 /* mask all interrupts */
265 it8172_hw0_icregs->lb_mask = 0xffff;
266 it8172_hw0_icregs->lpc_mask = 0xffff;
267 it8172_hw0_icregs->pci_mask = 0xffff;
268 it8172_hw0_icregs->nmi_mask = 0xffff;
270 /* make all interrupts level triggered */
271 it8172_hw0_icregs->lb_trigger = 0;
272 it8172_hw0_icregs->lpc_trigger = 0;
273 it8172_hw0_icregs->pci_trigger = 0;
274 it8172_hw0_icregs->nmi_trigger = 0;
276 /* active level setting */
277 /* uart, keyboard, and mouse are active high */
278 it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
279 it8172_hw0_icregs->lb_level |= 0x20;
281 /* keyboard and mouse are edge triggered */
282 it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
286 // Enable this piece of code to make internal USB interrupt
288 it8172_hw0_icregs->pci_trigger |=
289 (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
290 it8172_hw0_icregs->pci_level &=
291 ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
294 for (i = 0; i <= IT8172_LAST_IRQ; i++) {
295 irq_desc[i].handler = &it8172_irq_type;
296 spin_lock_init(&irq_desc[i].lock);
298 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
299 set_c0_status(ALLINTS_NOTIMER);
302 /* If local serial I/O used for debug port, enter kgdb at once */
303 puts("Waiting for kgdb to connect...");
309 void mips_spurious_interrupt(struct pt_regs *regs)
314 unsigned long status, cause;
316 printk("got spurious interrupt\n");
317 status = read_c0_status();
318 cause = read_c0_cause();
319 printk("status %x cause %x\n", status, cause);
320 printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
325 void it8172_hw0_irqdispatch(struct pt_regs *regs)
328 unsigned short intstatus = 0, status = 0;
330 intstatus = it8172_hw0_icregs->intstatus;
331 if (intstatus & 0x8) {
332 panic("Got NMI interrupt");
333 } else if (intstatus & 0x4) {
336 status |= it8172_hw0_icregs->pci_req;
337 while (!(status & 0x1)) {
341 irq += IT8172_PCI_DEV_IRQ_BASE;
342 //printk("pci int %d\n", irq);
344 else if (intstatus & 0x1) {
345 /* Local Bus interrupt */
347 status |= it8172_hw0_icregs->lb_req;
348 while (!(status & 0x1)) {
352 irq += IT8172_LB_IRQ_BASE;
353 //printk("lb int %d\n", irq);
355 else if (intstatus & 0x2) {
357 /* Since some lpc interrupts are edge triggered,
358 * we could lose an interrupt this way because
359 * we acknowledge all ints at onces. Revisit.
361 status |= it8172_hw0_icregs->lpc_req;
362 it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
364 while (!(status & 0x1)) {
368 irq += IT8172_LPC_IRQ_BASE;
369 //printk("LPC int %d\n", irq);
376 void show_pending_irqs(void)
378 fputs("intstatus: ");
379 put32(it8172_hw0_icregs->intstatus);
383 put32(it8172_hw0_icregs->pci_req);
387 put32(it8172_hw0_icregs->lb_req);
391 put32(it8172_hw0_icregs->lpc_req);