1 /***********************************************************************
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
7 * Based on arch/mips/ddb5xxx/ddb5477/setup.c
9 * Setup file for JMR3927.
11 * Copyright (C) 2000-2001 Toshiba Corporation
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 ***********************************************************************
36 #include <linux/config.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
39 #include <linux/kdev_t.h>
40 #include <linux/types.h>
41 #include <linux/sched.h>
42 #include <linux/pci.h>
43 #include <linux/ide.h>
44 #include <linux/ioport.h>
45 #include <linux/param.h> /* for HZ */
46 #include <linux/delay.h>
48 #include <asm/addrspace.h>
50 #include <asm/bcache.h>
52 #include <asm/reboot.h>
53 #include <asm/gdb-stub.h>
54 #include <asm/jmr3927/jmr3927.h>
55 #include <asm/mipsregs.h>
56 #include <asm/traps.h>
58 /* Tick Timer divider */
59 #define JMR3927_TIMER_CCD 0 /* 1/2 */
60 #define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
62 unsigned char led_state = 0xf;
67 struct resource pcimem;
70 struct resource pciio;
71 struct resource jmy1394;
76 } jmr3927_resources = {
77 { "RAM0", 0, 0x01FFFFFF, IORESOURCE_MEM },
78 { "RAM1", 0x02000000, 0x03FFFFFF, IORESOURCE_MEM },
79 { "PCIMEM", 0x08000000, 0x07FFFFFF, IORESOURCE_MEM },
80 { "IOB", 0x10000000, 0x13FFFFFF },
81 { "IOC", 0x14000000, 0x14FFFFFF },
82 { "PCIIO", 0x15000000, 0x15FFFFFF },
83 { "JMY1394", 0x1D000000, 0x1D3FFFFF },
84 { "ROM1", 0x1E000000, 0x1E3FFFFF },
85 { "ROM0", 0x1FC00000, 0x1FFFFFFF },
86 { "SIO0", 0xFFFEF300, 0xFFFEF3FF },
87 { "SIO1", 0xFFFEF400, 0xFFFEF4FF },
90 /* don't enable - see errata */
91 int jmr3927_ccfg_toeon = 0;
93 static inline void do_reset(void)
96 extern void tc35815_killall(void);
99 #if 1 /* Resetting PCI bus */
100 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
101 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
102 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
104 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
106 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
109 static void jmr3927_machine_restart(char *command)
112 puts("Rebooting...");
116 static void jmr3927_machine_halt(void)
118 puts("JMR-TX3927 halted.\n");
122 static void jmr3927_machine_power_off(void)
124 puts("JMR-TX3927 halted. Please turn off the power.\n");
128 #define USE_RTC_DS1742
129 #ifdef USE_RTC_DS1742
130 extern void rtc_ds1742_init(unsigned long base);
132 static void __init jmr3927_time_init(void)
134 #ifdef USE_RTC_DS1742
135 if (jmr3927_have_nvram()) {
136 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
141 unsigned long jmr3927_do_gettimeoffset(void);
142 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
144 static void __init jmr3927_timer_setup(struct irqaction *irq)
146 do_gettimeoffset = jmr3927_do_gettimeoffset;
148 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
149 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
150 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
151 jmr3927_tmrptr->tcr =
152 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
154 setup_irq(JMR3927_IRQ_TICK, irq);
157 #define USECS_PER_JIFFY (1000000/HZ)
159 unsigned long jmr3927_do_gettimeoffset(void)
162 unsigned long res = 0;
164 /* MUST read TRR before TISR. */
165 count = jmr3927_tmrptr->trr;
167 if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
168 /* timer interrupt is pending. use Max value. */
169 res = USECS_PER_JIFFY - 1;
171 /* convert to usec */
172 /* res = count / (JMR3927_TIMER_CLK / 1000000); */
173 res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
176 * Due to possible jiffies inconsistencies, we need to check
177 * the result so that we'll get a timer that is monotonic.
179 if (res >= USECS_PER_JIFFY)
180 res = USECS_PER_JIFFY-1;
187 //#undef DO_WRITE_THROUGH
188 #define DO_WRITE_THROUGH
189 #define DO_ENABLE_CACHE
191 extern char * __init prom_getcmdline(void);
192 static void jmr3927_board_init(void);
193 extern struct resource pci_io_resource;
194 extern struct resource pci_mem_resource;
196 static void __init jmr3927_setup(void)
198 extern int panic_timeout;
201 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
203 board_time_init = jmr3927_time_init;
204 board_timer_setup = jmr3927_timer_setup;
206 _machine_restart = jmr3927_machine_restart;
207 _machine_halt = jmr3927_machine_halt;
208 _machine_power_off = jmr3927_machine_power_off;
213 ioport_resource.start = pci_io_resource.start;
214 ioport_resource.end = pci_io_resource.end;
215 iomem_resource.start = pci_mem_resource.start;
216 iomem_resource.end = pci_mem_resource.end;
218 /* Reboot on panic */
223 conf = read_c0_conf();
230 #ifdef DO_ENABLE_CACHE
231 int mips_ic_disable = 0, mips_dc_disable = 0;
233 int mips_ic_disable = 1, mips_dc_disable = 1;
235 #ifdef DO_WRITE_THROUGH
236 int mips_config_cwfon = 0;
237 int mips_config_wbon = 0;
239 int mips_config_cwfon = 1;
240 int mips_config_wbon = 1;
243 conf = read_c0_conf();
244 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
245 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
246 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
247 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
248 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
255 /* initialize board */
256 jmr3927_board_init();
258 argptr = prom_getcmdline();
260 if ((argptr = strstr(argptr, "toeon")) != NULL) {
261 jmr3927_ccfg_toeon = 1;
263 argptr = prom_getcmdline();
264 if ((argptr = strstr(argptr, "ip=")) == NULL) {
265 argptr = prom_getcmdline();
266 strcat(argptr, " ip=bootp");
269 #ifdef CONFIG_TXX927_SERIAL_CONSOLE
270 argptr = prom_getcmdline();
271 if ((argptr = strstr(argptr, "console=")) == NULL) {
272 argptr = prom_getcmdline();
273 strcat(argptr, " console=ttyS1,115200");
278 early_initcall(jmr3927_setup);
281 static void tx3927_setup(void);
284 unsigned long mips_pci_io_base;
285 unsigned long mips_pci_io_size;
286 unsigned long mips_pci_mem_base;
287 unsigned long mips_pci_mem_size;
288 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
289 unsigned long mips_pci_io_pciaddr = 0;
292 static void __init jmr3927_board_init(void)
297 mips_pci_io_base = JMR3927_PCIIO;
298 mips_pci_io_size = JMR3927_PCIIO_SIZE;
299 mips_pci_mem_base = JMR3927_PCIMEM;
300 mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
305 if (jmr3927_have_isac()) {
307 #ifdef CONFIG_FB_E1355
308 argptr = prom_getcmdline();
309 if ((argptr = strstr(argptr, "video=")) == NULL) {
310 argptr = prom_getcmdline();
311 strcat(argptr, " video=e1355fb:crt16h");
315 #ifdef CONFIG_BLK_DEV_IDE
316 /* overrides PCI-IDE */
321 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
326 if (jmr3927_have_isac())
327 jmr3927_io_led_set(0);
328 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
329 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
330 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
331 jmr3927_dipsw1(), jmr3927_dipsw2(),
332 jmr3927_dipsw3(), jmr3927_dipsw4());
333 if (jmr3927_have_isac())
334 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
335 jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
339 static void __init tx3927_setup(void)
343 /* SDRAMC are configured by PROM */
346 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
347 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
348 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
349 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
352 /* enable Timeout BusError */
353 if (jmr3927_ccfg_toeon)
354 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
356 /* clear BusErrorOnWrite flag */
357 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
358 /* Disable PCI snoop */
359 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
361 #ifdef DO_WRITE_THROUGH
362 /* Enable PCI SNOOP - with write through only */
363 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
367 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
368 tx3927_ccfgptr->pcfg |=
369 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
370 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
372 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
373 tx3927_ccfgptr->crir,
374 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
377 /* disable interrupt control */
378 tx3927_ircptr->cer = 0;
379 /* mask all IRC interrupts */
380 tx3927_ircptr->imr = 0;
381 for (i = 0; i < TX3927_NUM_IR / 2; i++) {
382 tx3927_ircptr->ilr[i] = 0;
384 /* setup IRC interrupt mode (Low Active) */
385 for (i = 0; i < TX3927_NUM_IR / 8; i++) {
386 tx3927_ircptr->cr[i] = 0;
390 /* disable all timers */
391 for (i = 0; i < TX3927_NR_TMR; i++) {
392 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
393 tx3927_tmrptr(i)->tisr = 0;
394 tx3927_tmrptr(i)->cpra = 0xffffffff;
395 tx3927_tmrptr(i)->itmr = 0;
396 tx3927_tmrptr(i)->ccdr = 0;
397 tx3927_tmrptr(i)->pgmr = 0;
401 tx3927_dmaptr->mcr = 0;
402 for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
404 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
405 tx3927_dmaptr->ch[i].ccr = 0;
409 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
411 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
416 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
417 tx3927_pcicptr->did, tx3927_pcicptr->vid,
418 tx3927_pcicptr->rid);
419 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
420 printk("External\n");
423 printk("Internal\n");
426 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
428 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
429 JMR3927_IOC_RESET_ADDR);
431 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
434 /* Disable External PCI Config. Access */
435 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
437 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
438 TX3927_PCIC_LBC_TIBSE |
439 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
441 /* LB->PCI mappings */
442 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
443 tx3927_pcicptr->ilbioma = mips_pci_io_base;
444 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
445 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
446 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
447 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
448 /* PCI->LB mappings */
449 tx3927_pcicptr->iobas = 0xffffffff;
450 tx3927_pcicptr->ioba = 0;
451 tx3927_pcicptr->tlbioma = 0;
452 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
453 tx3927_pcicptr->mba = 0;
454 tx3927_pcicptr->tlbmma = 0;
455 #ifndef JMR3927_INIT_INDIRECT_PCI
456 /* Enable Direct mapping Address Space Decoder */
457 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
460 /* Clear All Local Bus Status */
461 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
462 /* Enable All Local Bus Interrupts */
463 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
464 /* Clear All PCI Status Error */
465 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
466 /* Enable All PCI Status Error Interrupts */
467 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
469 /* PCIC Int => IRC IRQ10 */
470 tx3927_pcicptr->il = TX3927_IR_PCI;
472 /* Target Control (per errata) */
473 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
476 /* Enable Bus Arbiter */
478 tx3927_pcicptr->req_trace = 0x73737373;
480 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
482 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
487 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
489 #endif /* CONFIG_PCI */
492 /* PIO[15:12] connected to LEDs */
493 tx3927_pioptr->dir = 0x0000f000;
494 tx3927_pioptr->maskcpu = 0;
495 tx3927_pioptr->maskext = 0;
499 conf = read_c0_conf();
500 if (!(conf & TX39_CONF_ICE))
501 printk("TX3927 I-Cache disabled.\n");
502 if (!(conf & TX39_CONF_DCE))
503 printk("TX3927 D-Cache disabled.\n");
504 else if (!(conf & TX39_CONF_WBON))
505 printk("TX3927 D-Cache WriteThrough.\n");
506 else if (!(conf & TX39_CONF_CWFON))
507 printk("TX3927 D-Cache WriteBack.\n");
509 printk("TX3927 D-Cache WriteBack (CWF) .\n");