2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
23 #include <asm/mipsregs.h>
24 #include <asm/system.h>
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
33 void (*cpu_wait)(void) = NULL;
35 static void r3081_wait(void)
37 unsigned long cfg = read_c0_conf();
38 write_c0_conf(cfg | R30XX_CONF_HALT);
41 static void r39xx_wait(void)
43 unsigned long cfg = read_c0_conf();
44 write_c0_conf(cfg | TX39_CONF_HALT);
47 static void r4k_wait(void)
49 __asm__(".set\tmips3\n\t"
55 * The Au1xxx wait is available only if we run CONFIG_PM and
56 * the timer setup found we had a 32KHz counter available.
57 * There are still problems with functions that may call au1k_wait
58 * directly, but that will be discovered pretty quickly.
60 extern void (*au1k_wait_ptr)(void);
65 /* using the wait instruction makes CP0 counter unusable */
66 __asm__(".set\tmips3\n\t"
79 static inline void check_wait(void)
81 struct cpuinfo_mips *c = ¤t_cpu_data;
83 printk("Checking for 'wait' instruction... ");
87 cpu_wait = r3081_wait;
88 printk(" available.\n");
91 cpu_wait = r39xx_wait;
92 printk(" available.\n");
112 printk(" available.\n");
118 if (au1k_wait_ptr != NULL) {
119 cpu_wait = au1k_wait_ptr;
120 printk(" available.\n");
123 printk(" unavailable.\n");
128 printk(" unavailable.\n");
133 void __init check_bugs32(void)
139 * Probe whether cpu has config register by trying to play with
140 * alternate cache bit and see whether it matters.
141 * It's used by cpu_probe to distinguish between R3000A and R3081.
143 static inline int cpu_has_confreg(void)
145 #ifdef CONFIG_CPU_R3000
146 extern unsigned long r3k_cache_size(unsigned long);
147 unsigned long size1, size2;
148 unsigned long cfg = read_c0_conf();
150 size1 = r3k_cache_size(ST0_ISC);
151 write_c0_conf(cfg ^ R30XX_CONF_AC);
152 size2 = r3k_cache_size(ST0_ISC);
154 return size1 != size2;
161 * Get the FPU Implementation/Revision.
163 static inline unsigned long cpu_get_fpu_id(void)
165 unsigned long tmp, fpu_id;
167 tmp = read_c0_status();
169 fpu_id = read_32bit_cp1_register(CP1_REVISION);
170 write_c0_status(tmp);
175 * Check the CPU has an FPU the official way.
177 static inline int __cpu_has_fpu(void)
179 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
182 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
185 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
187 switch (c->processor_id & 0xff00) {
189 c->cputype = CPU_R2000;
190 c->isa_level = MIPS_CPU_ISA_I;
191 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
193 c->options |= MIPS_CPU_FPU;
197 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
198 if (cpu_has_confreg())
199 c->cputype = CPU_R3081E;
201 c->cputype = CPU_R3000A;
203 c->cputype = CPU_R3000;
204 c->isa_level = MIPS_CPU_ISA_I;
205 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
207 c->options |= MIPS_CPU_FPU;
211 if (read_c0_config() & CONF_SC) {
212 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
213 c->cputype = CPU_R4400PC;
215 c->cputype = CPU_R4000PC;
217 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
218 c->cputype = CPU_R4400SC;
220 c->cputype = CPU_R4000SC;
223 c->isa_level = MIPS_CPU_ISA_III;
224 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
225 MIPS_CPU_WATCH | MIPS_CPU_VCE |
229 case PRID_IMP_VR41XX:
230 switch (c->processor_id & 0xf0) {
231 #ifndef CONFIG_VR4181
232 case PRID_REV_VR4111:
233 c->cputype = CPU_VR4111;
236 case PRID_REV_VR4181:
237 c->cputype = CPU_VR4181;
240 case PRID_REV_VR4121:
241 c->cputype = CPU_VR4121;
243 case PRID_REV_VR4122:
244 if ((c->processor_id & 0xf) < 0x3)
245 c->cputype = CPU_VR4122;
247 c->cputype = CPU_VR4181A;
249 case PRID_REV_VR4130:
250 if ((c->processor_id & 0xf) < 0x4)
251 c->cputype = CPU_VR4131;
253 c->cputype = CPU_VR4133;
256 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
257 c->cputype = CPU_VR41XX;
260 c->isa_level = MIPS_CPU_ISA_III;
261 c->options = R4K_OPTS;
265 c->cputype = CPU_R4300;
266 c->isa_level = MIPS_CPU_ISA_III;
267 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
272 c->cputype = CPU_R4600;
273 c->isa_level = MIPS_CPU_ISA_III;
274 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
280 * This processor doesn't have an MMU, so it's not
281 * "real easy" to run Linux on it. It is left purely
282 * for documentation. Commented out because it shares
283 * it's c0_prid id number with the TX3900.
285 c->cputype = CPU_R4650;
286 c->isa_level = MIPS_CPU_ISA_III;
287 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
292 c->isa_level = MIPS_CPU_ISA_I;
293 c->options = MIPS_CPU_TLB;
295 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
296 c->cputype = CPU_TX3927;
299 switch (c->processor_id & 0xff) {
300 case PRID_REV_TX3912:
301 c->cputype = CPU_TX3912;
304 case PRID_REV_TX3922:
305 c->cputype = CPU_TX3922;
309 c->cputype = CPU_UNKNOWN;
315 c->cputype = CPU_R4700;
316 c->isa_level = MIPS_CPU_ISA_III;
317 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
322 c->cputype = CPU_TX49XX;
323 c->isa_level = MIPS_CPU_ISA_III;
324 c->options = R4K_OPTS | MIPS_CPU_LLSC;
325 if (!(c->processor_id & 0x08))
326 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
330 c->cputype = CPU_R5000;
331 c->isa_level = MIPS_CPU_ISA_IV;
332 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
337 c->cputype = CPU_R5432;
338 c->isa_level = MIPS_CPU_ISA_IV;
339 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
340 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
344 c->cputype = CPU_R5500;
345 c->isa_level = MIPS_CPU_ISA_IV;
346 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
347 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
350 case PRID_IMP_NEVADA:
351 c->cputype = CPU_NEVADA;
352 c->isa_level = MIPS_CPU_ISA_IV;
353 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
354 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
358 c->cputype = CPU_R6000;
359 c->isa_level = MIPS_CPU_ISA_II;
360 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
364 case PRID_IMP_R6000A:
365 c->cputype = CPU_R6000A;
366 c->isa_level = MIPS_CPU_ISA_II;
367 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
371 case PRID_IMP_RM7000:
372 c->cputype = CPU_RM7000;
373 c->isa_level = MIPS_CPU_ISA_IV;
374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
377 * Undocumented RM7000: Bit 29 in the info register of
378 * the RM7000 v2.0 indicates if the TLB has 48 or 64
381 * 29 1 => 64 entry JTLB
384 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
386 case PRID_IMP_RM9000:
387 c->cputype = CPU_RM9000;
388 c->isa_level = MIPS_CPU_ISA_IV;
389 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
392 * Bit 29 in the info register of the RM9000
393 * indicates if the TLB has 48 or 64 entries.
395 * 29 1 => 64 entry JTLB
398 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
401 c->cputype = CPU_R8000;
402 c->isa_level = MIPS_CPU_ISA_IV;
403 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
404 MIPS_CPU_FPU | MIPS_CPU_32FPR |
406 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
408 case PRID_IMP_R10000:
409 c->cputype = CPU_R10000;
410 c->isa_level = MIPS_CPU_ISA_IV;
411 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
412 MIPS_CPU_FPU | MIPS_CPU_32FPR |
413 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
417 case PRID_IMP_R12000:
418 c->cputype = CPU_R12000;
419 c->isa_level = MIPS_CPU_ISA_IV;
420 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
421 MIPS_CPU_FPU | MIPS_CPU_32FPR |
422 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
429 static inline void decode_config1(struct cpuinfo_mips *c)
431 unsigned long config0 = read_c0_config();
432 unsigned long config1;
434 if ((config0 & (1 << 31)) == 0)
435 return; /* actually wort a panic() */
437 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
438 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
439 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
440 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
441 config1 = read_c0_config1();
442 if (config1 & (1 << 3))
443 c->options |= MIPS_CPU_WATCH;
444 if (config1 & (1 << 2))
445 c->options |= MIPS_CPU_MIPS16;
446 if (config1 & (1 << 1))
447 c->options |= MIPS_CPU_EJTAG;
449 c->options |= MIPS_CPU_FPU;
450 c->options |= MIPS_CPU_32FPR;
452 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
454 c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
457 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
460 switch (c->processor_id & 0xff00) {
462 c->cputype = CPU_4KC;
463 c->isa_level = MIPS_CPU_ISA_M32;
466 c->cputype = CPU_4KEC;
467 c->isa_level = MIPS_CPU_ISA_M32;
470 c->cputype = CPU_4KSC;
471 c->isa_level = MIPS_CPU_ISA_M32;
474 c->cputype = CPU_5KC;
475 c->isa_level = MIPS_CPU_ISA_M64;
478 c->cputype = CPU_20KC;
479 c->isa_level = MIPS_CPU_ISA_M64;
482 c->cputype = CPU_24K;
483 c->isa_level = MIPS_CPU_ISA_M32;
486 c->cputype = CPU_25KF;
487 c->isa_level = MIPS_CPU_ISA_M64;
488 /* Probe for L2 cache */
489 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
494 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
497 switch (c->processor_id & 0xff00) {
498 case PRID_IMP_AU1_REV1:
499 case PRID_IMP_AU1_REV2:
500 switch ((c->processor_id >> 24) & 0xff) {
502 c->cputype = CPU_AU1000;
505 c->cputype = CPU_AU1500;
508 c->cputype = CPU_AU1100;
511 c->cputype = CPU_AU1550;
514 panic("Unknown Au Core!");
517 c->isa_level = MIPS_CPU_ISA_M32;
522 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
525 switch (c->processor_id & 0xff00) {
527 c->cputype = CPU_SB1;
528 c->isa_level = MIPS_CPU_ISA_M64;
529 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
530 MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
531 MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
532 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
533 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
534 /* FPU in pass1 is known to have issues. */
535 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
541 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
544 switch (c->processor_id & 0xff00) {
545 case PRID_IMP_SR71000:
546 c->cputype = CPU_SR71000;
547 c->isa_level = MIPS_CPU_ISA_M64;
548 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
549 MIPS_CPU_4KTLB | MIPS_CPU_FPU |
550 MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
557 __init void cpu_probe(void)
559 struct cpuinfo_mips *c = ¤t_cpu_data;
561 c->processor_id = PRID_IMP_UNKNOWN;
562 c->fpu_id = FPIR_IMP_NONE;
563 c->cputype = CPU_UNKNOWN;
565 c->processor_id = read_c0_prid();
566 switch (c->processor_id & 0xff0000) {
567 case PRID_COMP_LEGACY:
573 case PRID_COMP_ALCHEMY:
574 cpu_probe_alchemy(c);
576 case PRID_COMP_SIBYTE:
580 case PRID_COMP_SANDCRAFT:
581 cpu_probe_sandcraft(c);
584 c->cputype = CPU_UNKNOWN;
586 if (c->options & MIPS_CPU_FPU)
587 c->fpu_id = cpu_get_fpu_id();
590 __init void cpu_report(void)
592 struct cpuinfo_mips *c = ¤t_cpu_data;
594 printk("CPU revision is: %08x\n", c->processor_id);
595 if (c->options & MIPS_CPU_FPU)
596 printk("FPU revision is: %08x\n", c->fpu_id);