2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 #include <linux/config.h>
12 #include <linux/init.h>
15 #include <asm/cacheops.h>
16 #include <asm/regdef.h>
17 #include <asm/fpregdef.h>
18 #include <asm/mipsregs.h>
19 #include <asm/stackframe.h>
24 NESTED(except_vec0_generic, 0, sp)
25 PANIC("Exception vector 0 called")
26 END(except_vec0_generic)
28 NESTED(except_vec1_generic, 0, sp)
29 PANIC("Exception vector 1 called")
30 END(except_vec1_generic)
33 * General exception vector for all other CPUs.
35 * Be careful when changing this, it has to be at most 128 bytes
36 * to fit into space reserved for the exception handler.
38 NESTED(except_vec3_generic, 0, sp)
41 #if R5432_CP0_INTERRUPT_WAR
49 PTR_L k0, exception_handlers(k1)
52 END(except_vec3_generic)
55 * General exception handler for CPUs with virtual coherency exception.
57 * Be careful when changing this, it has to be at most 256 (as a special
58 * exception) bytes to fit into space reserved for the exception handler.
60 NESTED(except_vec3_r4000, 0, sp)
70 beq k1, k0, handle_vced
72 beq k1, k0, handle_vcei
77 PTR_L k0, exception_handlers(k1)
81 * Big shit, we now may have two dirty primary cache lines for the same
82 * physical address. We can savely invalidate the line pointed to by
83 * c0_badvaddr because after return from this exception handler the
84 * load / store will be re-executed.
87 DMFC0 k0, CP0_BADVADDR
88 li k1, -4 # Is this ...
89 and k0, k1 # ... really needed?
91 cache Index_Store_Tag_D,(k0)
92 cache Hit_Writeback_Inv_SD,(k0)
102 MFC0 k0, CP0_BADVADDR
103 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
104 #ifdef CONFIG_PROC_FS
105 PTR_LA k0, vcei_count
112 END(except_vec3_r4000)
115 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
116 * This is a dedicated interrupt exception vector which reduces the
117 * interrupt processing overhead. The jump instruction will be replaced
118 * at the initialization time.
120 * Be careful when changing this, it has to be at most 128 bytes
121 * to fit into space reserved for the exception handler.
123 NESTED(except_vec4, 0, sp)
124 1: j 1b /* Dummy, will be replaced */
128 * EJTAG debug exception handler.
129 * The EJTAG debug exception entry point is 0xbfc00480, which
130 * normally is in the boot PROM, so the boot PROM must do a
131 * unconditional jump to this vector.
133 NESTED(except_vec_ejtag_debug, 0, sp)
134 j ejtag_debug_handler
135 END(except_vec_ejtag_debug)
140 * EJTAG debug exception handler.
142 NESTED(ejtag_debug_handler, PT_SIZE, sp)
149 sll k0, k0, 30 # Check for SDBBP.
150 bgez k0, ejtag_return
153 PTR_LA k0, ejtag_debug_buffer
156 jal ejtag_exception_handler
159 PTR_LA k0, ejtag_debug_buffer
168 END(ejtag_debug_handler)
171 * This buffer is reserved for the use of the EJTAG debug
175 EXPORT(ejtag_debug_buffer)
182 * NMI debug exception handler for MIPS reference boards.
183 * The NMI debug exception entry point is 0xbfc00000, which
184 * normally is in the boot PROM, so the boot PROM must do a
185 * unconditional jump to this vector.
187 NESTED(except_vec_nmi, 0, sp)
193 NESTED(nmi_handler, PT_SIZE, sp)
199 jal nmi_exception_handler
205 .macro __build_clear_none
208 .macro __build_clear_sti
212 .macro __build_clear_cli
216 .macro __build_clear_fpe
224 .macro __build_clear_ade
225 MFC0 t0, CP0_BADVADDR
226 PTR_S t0, PT_BVADDR(sp)
230 .macro __BUILD_silent exception
233 /* Gas tries to parse the PRINT argument as a string containing
234 string escapes and emits bogus warnings if it believes to
235 recognize an unknown escape code. So make the arguments
236 start with an n and gas will believe \n is ok ... */
237 .macro __BUILD_verbose nexception
238 LONG_L a1, PT_EPC(sp)
240 PRINT("Got \nexception at %08lx\012")
243 PRINT("Got \nexception at %016lx\012")
247 .macro __BUILD_count exception
248 LONG_L t0,exception_count_\exception
250 LONG_S t0,exception_count_\exception
251 .comm exception_count\exception, 8, 8
254 .macro __BUILD_HANDLER exception handler clear verbose ext
256 NESTED(handle_\exception, PT_SIZE, sp)
259 FEXPORT(handle_\exception\ext)
262 __BUILD_\verbose \exception
266 END(handle_\exception)
269 .macro BUILD_HANDLER exception handler clear verbose
270 __BUILD_HANDLER \exception \handler \clear \verbose _int
273 BUILD_HANDLER adel ade ade silent /* #4 */
274 BUILD_HANDLER ades ade ade silent /* #5 */
275 BUILD_HANDLER ibe be cli silent /* #6 */
276 BUILD_HANDLER dbe be cli silent /* #7 */
277 BUILD_HANDLER bp bp sti silent /* #9 */
278 BUILD_HANDLER ri ri sti silent /* #10 */
279 BUILD_HANDLER cpu cpu sti silent /* #11 */
280 BUILD_HANDLER ov ov sti silent /* #12 */
281 BUILD_HANDLER tr tr sti silent /* #13 */
282 BUILD_HANDLER fpe fpe fpe silent /* #15 */
283 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
284 BUILD_HANDLER watch watch sti verbose /* #23 */
285 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
286 BUILD_HANDLER reserved reserved sti verbose /* others */
289 /* A temporary overflow handler used by check_daddi(). */
293 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */