2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
26 #include <asm/break.h>
29 #include <asm/module.h>
30 #include <asm/pgtable.h>
31 #include <asm/ptrace.h>
32 #include <asm/sections.h>
33 #include <asm/system.h>
34 #include <asm/tlbdebug.h>
35 #include <asm/traps.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/watch.h>
39 #include <asm/types.h>
41 extern asmlinkage void handle_mod(void);
42 extern asmlinkage void handle_tlbl(void);
43 extern asmlinkage void handle_tlbs(void);
44 extern asmlinkage void __xtlb_mod(void);
45 extern asmlinkage void __xtlb_tlbl(void);
46 extern asmlinkage void __xtlb_tlbs(void);
47 extern asmlinkage void handle_adel(void);
48 extern asmlinkage void handle_ades(void);
49 extern asmlinkage void handle_ibe(void);
50 extern asmlinkage void handle_dbe(void);
51 extern asmlinkage void handle_sys(void);
52 extern asmlinkage void handle_bp(void);
53 extern asmlinkage void handle_ri(void);
54 extern asmlinkage void handle_cpu(void);
55 extern asmlinkage void handle_ov(void);
56 extern asmlinkage void handle_tr(void);
57 extern asmlinkage void handle_fpe(void);
58 extern asmlinkage void handle_mdmx(void);
59 extern asmlinkage void handle_watch(void);
60 extern asmlinkage void handle_mcheck(void);
61 extern asmlinkage void handle_reserved(void);
63 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
64 struct mips_fpu_soft_struct *ctx);
66 void (*board_be_init)(void);
67 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
70 * These constant is for searching for possible module text segments.
71 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
73 #define MODULE_RANGE (8*1024*1024)
76 * This routine abuses get_user()/put_user() to reference pointers
77 * with at least a bit of error checking ...
79 void show_stack(struct task_struct *task, unsigned long *sp)
81 const int field = 2 * sizeof(unsigned long);
85 sp = sp ? sp : (unsigned long *) &sp;
89 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
90 if (i && ((i % (64 / field)) == 0))
97 if (__get_user(stackdata, sp++)) {
98 printk(" (Bad stack address)");
102 printk(" %0*lx", field, stackdata);
108 void show_trace(struct task_struct *task, unsigned long *stack)
110 const int field = 2 * sizeof(unsigned long);
114 stack = (unsigned long*)&stack;
116 printk("Call Trace:");
117 #ifdef CONFIG_KALLSYMS
120 while (!kstack_end(stack)) {
122 if (__kernel_text_address(addr)) {
123 printk(" [<%0*lx>] ", field, addr);
124 print_symbol("%s\n", addr);
131 * The architecture-independent dump_stack generator
133 void dump_stack(void)
137 show_trace(current, &stack);
140 EXPORT_SYMBOL(dump_stack);
142 void show_code(unsigned int *pc)
148 for(i = -3 ; i < 6 ; i++) {
150 if (__get_user(insn, pc + i)) {
151 printk(" (Bad address in epc)\n");
154 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
158 void show_regs(struct pt_regs *regs)
160 const int field = 2 * sizeof(unsigned long);
161 unsigned int cause = regs->cp0_cause;
164 printk("Cpu %d\n", smp_processor_id());
167 * Saved main processor registers
169 for (i = 0; i < 32; ) {
173 printk(" %0*lx", field, 0UL);
174 else if (i == 26 || i == 27)
175 printk(" %*s", field, "");
177 printk(" %0*lx", field, regs->regs[i]);
184 printk("Hi : %0*lx\n", field, regs->hi);
185 printk("Lo : %0*lx\n", field, regs->lo);
188 * Saved cp0 registers
190 printk("epc : %0*lx ", field, regs->cp0_epc);
191 print_symbol("%s ", regs->cp0_epc);
192 printk(" %s\n", print_tainted());
193 printk("ra : %0*lx ", field, regs->regs[31]);
194 print_symbol("%s\n", regs->regs[31]);
196 printk("Status: %08x ", (uint32_t) regs->cp0_status);
198 if (regs->cp0_status & ST0_KX)
200 if (regs->cp0_status & ST0_SX)
202 if (regs->cp0_status & ST0_UX)
204 switch (regs->cp0_status & ST0_KSU) {
209 printk("SUPERVISOR ");
218 if (regs->cp0_status & ST0_ERL)
220 if (regs->cp0_status & ST0_EXL)
222 if (regs->cp0_status & ST0_IE)
226 printk("Cause : %08x\n", cause);
228 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
229 if (1 <= cause && cause <= 5)
230 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
232 printk("PrId : %08x\n", read_c0_prid());
235 void show_registers(struct pt_regs *regs)
239 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
240 current->comm, current->pid, current_thread_info(), current);
241 show_stack(current, (long *) regs->regs[29]);
242 show_trace(current, (long *) regs->regs[29]);
243 show_code((unsigned int *) regs->cp0_epc);
247 static spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
249 NORET_TYPE void __die(const char * str, struct pt_regs * regs,
250 const char * file, const char * func, unsigned long line)
252 static int die_counter;
255 spin_lock_irq(&die_lock);
258 printk(" in %s:%s, line %ld", file, func, line);
259 printk("[#%d]:\n", ++die_counter);
260 show_registers(regs);
261 spin_unlock_irq(&die_lock);
265 void __die_if_kernel(const char * str, struct pt_regs * regs,
266 const char * file, const char * func, unsigned long line)
268 if (!user_mode(regs))
269 __die(str, regs, file, func, line);
272 extern const struct exception_table_entry __start___dbe_table[];
273 extern const struct exception_table_entry __stop___dbe_table[];
275 void __declare_dbe_table(void)
277 __asm__ __volatile__(
278 ".section\t__dbe_table,\"a\"\n\t"
283 /* Given an address, look for it in the exception tables. */
284 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
286 const struct exception_table_entry *e;
288 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
290 e = search_module_dbetables(addr);
294 asmlinkage void do_be(struct pt_regs *regs)
296 const int field = 2 * sizeof(unsigned long);
297 const struct exception_table_entry *fixup = NULL;
298 int data = regs->cp0_cause & 4;
299 int action = MIPS_BE_FATAL;
301 /* XXX For now. Fixme, this searches the wrong table ... */
302 if (data && !user_mode(regs))
303 fixup = search_dbe_tables(exception_epc(regs));
306 action = MIPS_BE_FIXUP;
308 if (board_be_handler)
309 action = board_be_handler(regs, fixup != 0);
312 case MIPS_BE_DISCARD:
316 regs->cp0_epc = fixup->nextinsn;
325 * Assume it would be too dangerous to continue ...
327 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
328 data ? "Data" : "Instruction",
329 field, regs->cp0_epc, field, regs->regs[31]);
330 die_if_kernel("Oops", regs);
331 force_sig(SIGBUS, current);
334 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
338 epc = (unsigned int *) regs->cp0_epc +
339 ((regs->cp0_cause & CAUSEF_BD) != 0);
340 if (!get_user(*opcode, epc))
343 force_sig(SIGSEGV, current);
351 #define OPCODE 0xfc000000
352 #define BASE 0x03e00000
353 #define RT 0x001f0000
354 #define OFFSET 0x0000ffff
355 #define LL 0xc0000000
356 #define SC 0xe0000000
359 * The ll_bit is cleared by r*_switch.S
362 unsigned long ll_bit;
364 static struct task_struct *ll_task = NULL;
366 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
368 unsigned long value, *vaddr;
373 * analyse the ll instruction that just caused a ri exception
374 * and put the referenced address to addr.
377 /* sign extend offset */
378 offset = opcode & OFFSET;
382 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
384 if ((unsigned long)vaddr & 3) {
388 if (get_user(value, vaddr)) {
395 if (ll_task == NULL || ll_task == current) {
404 regs->regs[(opcode & RT) >> 16] = value;
406 compute_return_epc(regs);
410 force_sig(signal, current);
413 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
415 unsigned long *vaddr, reg;
420 * analyse the sc instruction that just caused a ri exception
421 * and put the referenced address to addr.
424 /* sign extend offset */
425 offset = opcode & OFFSET;
429 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
430 reg = (opcode & RT) >> 16;
432 if ((unsigned long)vaddr & 3) {
439 if (ll_bit == 0 || ll_task != current) {
442 compute_return_epc(regs);
448 if (put_user(regs->regs[reg], vaddr)) {
455 compute_return_epc(regs);
459 force_sig(signal, current);
463 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
464 * opcodes are supposed to result in coprocessor unusable exceptions if
465 * executed on ll/sc-less processors. That's the theory. In practice a
466 * few processors such as NEC's VR4100 throw reserved instruction exceptions
467 * instead, so we're doing the emulation thing in both exception handlers.
469 static inline int simulate_llsc(struct pt_regs *regs)
473 if (unlikely(get_insn_opcode(regs, &opcode)))
476 if ((opcode & OPCODE) == LL) {
477 simulate_ll(regs, opcode);
480 if ((opcode & OPCODE) == SC) {
481 simulate_sc(regs, opcode);
485 return -EFAULT; /* Strange things going on ... */
488 asmlinkage void do_ov(struct pt_regs *regs)
492 info.si_code = FPE_INTOVF;
493 info.si_signo = SIGFPE;
495 info.si_addr = (void *)regs->cp0_epc;
496 force_sig_info(SIGFPE, &info, current);
500 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
502 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
504 if (fcr31 & FPU_CSR_UNI_X) {
510 * Unimplemented operation exception. If we've got the full
511 * software emulator on-board, let's use it...
513 * Force FPU to dump state into task/thread context. We're
514 * moving a lot of data here for what is probably a single
515 * instruction, but the alternative is to pre-decode the FP
516 * register operands before invoking the emulator, which seems
517 * a bit extreme for what should be an infrequent event.
521 /* Run the emulator */
522 sig = fpu_emulator_cop1Handler (0, regs,
523 ¤t->thread.fpu.soft);
526 * We can't allow the emulated instruction to leave any of
527 * the cause bit set in $fcr31.
529 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
531 /* Restore the hardware register state */
536 /* If something went wrong, signal */
538 force_sig(sig, current);
543 force_sig(SIGFPE, current);
546 asmlinkage void do_bp(struct pt_regs *regs)
548 unsigned int opcode, bcode;
551 die_if_kernel("Break instruction in kernel code", regs);
553 if (get_insn_opcode(regs, &opcode))
557 * There is the ancient bug in the MIPS assemblers that the break
558 * code starts left to bit 16 instead to bit 6 in the opcode.
559 * Gas is bug-compatible, but not always, grrr...
560 * We handle both cases with a simple heuristics. --macro
562 bcode = ((opcode >> 6) & ((1 << 20) - 1));
563 if (bcode < (1 << 10))
567 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
568 * insns, even for break codes that indicate arithmetic failures.
570 * But should we continue the brokenness??? --macro
573 case BRK_OVERFLOW << 10:
574 case BRK_DIVZERO << 10:
575 if (bcode == (BRK_DIVZERO << 10))
576 info.si_code = FPE_INTDIV;
578 info.si_code = FPE_INTOVF;
579 info.si_signo = SIGFPE;
581 info.si_addr = (void *)regs->cp0_epc;
582 force_sig_info(SIGFPE, &info, current);
585 force_sig(SIGTRAP, current);
589 asmlinkage void do_tr(struct pt_regs *regs)
591 unsigned int opcode, tcode = 0;
594 die_if_kernel("Trap instruction in kernel code", regs);
596 if (get_insn_opcode(regs, &opcode))
599 /* Immediate versions don't provide a code. */
600 if (!(opcode & OPCODE))
601 tcode = ((opcode >> 6) & ((1 << 10) - 1));
604 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
605 * insns, even for trap codes that indicate arithmetic failures.
607 * But should we continue the brokenness??? --macro
612 if (tcode == BRK_DIVZERO)
613 info.si_code = FPE_INTDIV;
615 info.si_code = FPE_INTOVF;
616 info.si_signo = SIGFPE;
618 info.si_addr = (void *)regs->cp0_epc;
619 force_sig_info(SIGFPE, &info, current);
622 force_sig(SIGTRAP, current);
626 asmlinkage void do_ri(struct pt_regs *regs)
628 die_if_kernel("Reserved instruction in kernel code", regs);
631 if (!simulate_llsc(regs))
634 force_sig(SIGILL, current);
637 asmlinkage void do_cpu(struct pt_regs *regs)
641 die_if_kernel("do_cpu invoked from kernel context!", regs);
643 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
650 if (!simulate_llsc(regs))
658 if (current->used_math) { /* Using the FPU again. */
660 } else { /* First time FPU user. */
662 current->used_math = 1;
666 int sig = fpu_emulator_cop1Handler(0, regs,
667 ¤t->thread.fpu.soft);
669 force_sig(sig, current);
681 force_sig(SIGILL, current);
684 asmlinkage void do_mdmx(struct pt_regs *regs)
686 force_sig(SIGILL, current);
689 asmlinkage void do_watch(struct pt_regs *regs)
692 * We use the watch exception where available to detect stack
697 panic("Caught WATCH exception - probably caused by stack overflow.");
700 asmlinkage void do_mcheck(struct pt_regs *regs)
705 * Some chips may have other causes of machine check (e.g. SB1
708 panic("Caught Machine Check exception - %scaused by multiple "
709 "matching entries in the TLB.",
710 (regs->cp0_status & ST0_TS) ? "" : "not ");
713 asmlinkage void do_reserved(struct pt_regs *regs)
716 * Game over - no way to handle this if it ever occurs. Most probably
717 * caused by a new unknown cpu type or after another deadly
718 * hard/software error.
721 panic("Caught reserved exception %ld - should not happen.",
722 (regs->cp0_cause & 0x7f) >> 2);
726 * Some MIPS CPUs can enable/disable for cache parity detection, but do
729 static inline void parity_protection_init(void)
731 switch (current_cpu_data.cputype) {
733 /* 24K cache parity not currently implemented in FPGA */
734 printk(KERN_INFO "Disable cache parity protection for "
736 write_c0_ecc(read_c0_ecc() & ~0x80000000);
739 /* Set the PE bit (bit 31) in the c0_ecc register. */
740 printk(KERN_INFO "Enable cache parity protection for "
741 "MIPS 5KC/24K CPUs.\n");
742 write_c0_ecc(read_c0_ecc() | 0x80000000);
746 /* Clear the DE bit (bit 16) in the c0_status register. */
747 printk(KERN_INFO "Enable cache parity protection for "
748 "MIPS 20KC/25KF CPUs.\n");
749 clear_c0_status(ST0_DE);
756 asmlinkage void cache_parity_error(void)
758 const int field = 2 * sizeof(unsigned long);
759 unsigned int reg_val;
761 /* For the moment, report the problem and hang. */
762 printk("Cache error exception:\n");
763 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
764 reg_val = read_c0_cacheerr();
765 printk("c0_cacheerr == %08x\n", reg_val);
767 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
768 reg_val & (1<<30) ? "secondary" : "primary",
769 reg_val & (1<<31) ? "data" : "insn");
770 printk("Error bits: %s%s%s%s%s%s%s\n",
771 reg_val & (1<<29) ? "ED " : "",
772 reg_val & (1<<28) ? "ET " : "",
773 reg_val & (1<<26) ? "EE " : "",
774 reg_val & (1<<25) ? "EB " : "",
775 reg_val & (1<<24) ? "EI " : "",
776 reg_val & (1<<23) ? "E1 " : "",
777 reg_val & (1<<22) ? "E0 " : "");
778 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
780 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
781 if (reg_val & (1<<22))
782 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
784 if (reg_val & (1<<23))
785 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
788 panic("Can't handle the cache error!");
792 * SDBBP EJTAG debug exception handler.
793 * We skip the instruction and return to the next instruction.
795 void ejtag_exception_handler(struct pt_regs *regs)
797 const int field = 2 * sizeof(unsigned long);
798 unsigned long depc, old_epc;
801 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
802 depc = read_c0_depc();
803 debug = read_c0_debug();
804 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
805 if (debug & 0x80000000) {
807 * In branch delay slot.
808 * We cheat a little bit here and use EPC to calculate the
809 * debug return address (DEPC). EPC is restored after the
812 old_epc = regs->cp0_epc;
813 regs->cp0_epc = depc;
814 __compute_return_epc(regs);
815 depc = regs->cp0_epc;
816 regs->cp0_epc = old_epc;
822 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
823 write_c0_debug(debug | 0x100);
828 * NMI exception handler.
830 void nmi_exception_handler(struct pt_regs *regs)
832 printk("NMI taken!!!!\n");
837 unsigned long exception_handlers[32];
840 * As a side effect of the way this is implemented we're limited
841 * to interrupt handlers in the address range from
842 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
844 void *set_except_vector(int n, void *addr)
846 unsigned long handler = (unsigned long) addr;
847 unsigned long old_handler = exception_handlers[n];
849 exception_handlers[n] = handler;
850 if (n == 0 && cpu_has_divec) {
851 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 |
852 (0x03ffffff & (handler >> 2));
853 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204);
855 return (void *)old_handler;
859 * This is used by native signal handling
861 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
862 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
864 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
865 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
867 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
868 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
870 static inline void signal_init(void)
873 save_fp_context = _save_fp_context;
874 restore_fp_context = _restore_fp_context;
876 save_fp_context = fpu_emulator_save_context;
877 restore_fp_context = fpu_emulator_restore_context;
881 #ifdef CONFIG_MIPS32_COMPAT
884 * This is used by 32-bit signal stuff on the 64-bit kernel
886 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
887 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
889 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
890 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
892 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
893 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
895 static inline void signal32_init(void)
898 save_fp_context32 = _save_fp_context32;
899 restore_fp_context32 = _restore_fp_context32;
901 save_fp_context32 = fpu_emulator_save_context32;
902 restore_fp_context32 = fpu_emulator_restore_context32;
907 extern void cpu_cache_init(void);
908 extern void tlb_init(void);
910 void __init per_cpu_trap_init(void)
912 unsigned int cpu = smp_processor_id();
913 unsigned int status_set = ST0_CU0;
916 * Disable coprocessors and select 32-bit or 64-bit addressing
917 * and the 16/32 or 32/32 FPR register model. Reset the BEV
918 * flag that some firmware may have left set and the TS bit (for
919 * IP27). Set XX for ISA IV code to work.
922 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
924 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
925 status_set |= ST0_XX;
926 change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
930 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
931 * interrupt processing overhead. Use it where available.
934 set_c0_cause(CAUSEF_IV);
936 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
937 TLBMISS_HANDLER_SETUP();
939 atomic_inc(&init_mm.mm_count);
940 current->active_mm = &init_mm;
942 enter_lazy_tlb(&init_mm, current);
948 void __init trap_init(void)
950 extern char except_vec3_generic, except_vec3_r4000;
951 extern char except_vec_ejtag_debug;
952 extern char except_vec4;
958 * Copy the generic exception handlers to their final destination.
959 * This will be overriden later as suitable for a particular
962 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
965 * Setup default vectors
967 for (i = 0; i <= 31; i++)
968 set_except_vector(i, handle_reserved);
971 * Copy the EJTAG debug exception vector handler code to it's final
975 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80);
978 * Only some CPUs have the watch exceptions.
981 set_except_vector(23, handle_watch);
984 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
985 * interrupt processing overhead. Use it where available.
988 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8);
991 * Some CPUs can enable/disable for cache parity detection, but does
994 parity_protection_init();
997 * The Data Bus Errors / Instruction Bus Errors are signaled
998 * by external hardware. Therefore these two exceptions
999 * may have board specific handlers.
1004 #ifdef CONFIG_MIPS32
1005 set_except_vector(1, handle_mod);
1006 set_except_vector(2, handle_tlbl);
1007 set_except_vector(3, handle_tlbs);
1009 #ifdef CONFIG_MIPS64
1010 set_except_vector(1, __xtlb_mod);
1011 set_except_vector(2, __xtlb_tlbl);
1012 set_except_vector(3, __xtlb_tlbs);
1014 set_except_vector(4, handle_adel);
1015 set_except_vector(5, handle_ades);
1017 set_except_vector(6, handle_ibe);
1018 set_except_vector(7, handle_dbe);
1020 set_except_vector(8, handle_sys);
1021 set_except_vector(9, handle_bp);
1022 set_except_vector(10, handle_ri);
1023 set_except_vector(11, handle_cpu);
1024 set_except_vector(12, handle_ov);
1025 set_except_vector(13, handle_tr);
1026 set_except_vector(22, handle_mdmx);
1028 if (cpu_has_fpu && !cpu_has_nofpuex)
1029 set_except_vector(15, handle_fpe);
1032 set_except_vector(24, handle_mcheck);
1035 /* Special exception: R4[04]00 uses also the divec space. */
1036 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1037 else if (cpu_has_4kex)
1038 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1040 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1042 if (current_cpu_data.cputype == CPU_R6000 ||
1043 current_cpu_data.cputype == CPU_R6000A) {
1045 * The R6000 is the only R-series CPU that features a machine
1046 * check exception (similar to the R4000 cache error) and
1047 * unaligned ldc1/sdc1 exception. The handlers have not been
1048 * written yet. Well, anyway there is no R6000 machine on the
1049 * current list of targets for Linux/MIPS.
1050 * (Duh, crap, there is someone with a tripple R6k machine)
1052 //set_except_vector(14, handle_mc);
1053 //set_except_vector(15, handle_ndc);
1057 #ifdef CONFIG_MIPS32_COMPAT
1061 flush_icache_range(CAC_BASE, CAC_BASE + 0x400);