2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
44 #include <asm/stacktrace.h>
46 extern asmlinkage void handle_int(void);
47 extern asmlinkage void handle_tlbm(void);
48 extern asmlinkage void handle_tlbl(void);
49 extern asmlinkage void handle_tlbs(void);
50 extern asmlinkage void handle_adel(void);
51 extern asmlinkage void handle_ades(void);
52 extern asmlinkage void handle_ibe(void);
53 extern asmlinkage void handle_dbe(void);
54 extern asmlinkage void handle_sys(void);
55 extern asmlinkage void handle_bp(void);
56 extern asmlinkage void handle_ri(void);
57 extern asmlinkage void handle_ri_rdhwr_vivt(void);
58 extern asmlinkage void handle_ri_rdhwr(void);
59 extern asmlinkage void handle_cpu(void);
60 extern asmlinkage void handle_ov(void);
61 extern asmlinkage void handle_tr(void);
62 extern asmlinkage void handle_fpe(void);
63 extern asmlinkage void handle_mdmx(void);
64 extern asmlinkage void handle_watch(void);
65 extern asmlinkage void handle_mt(void);
66 extern asmlinkage void handle_dsp(void);
67 extern asmlinkage void handle_mcheck(void);
68 extern asmlinkage void handle_reserved(void);
70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
71 struct mips_fpu_struct *ctx, int has_fpu);
73 void (*board_be_init)(void);
74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
75 void (*board_nmi_handler_setup)(void);
76 void (*board_ejtag_handler_setup)(void);
77 void (*board_bind_eic_interrupt)(int irq, int regset);
80 static void show_raw_backtrace(unsigned long reg29)
82 unsigned long *sp = (unsigned long *)reg29;
85 printk("Call Trace:");
86 #ifdef CONFIG_KALLSYMS
89 while (!kstack_end(sp)) {
91 if (__kernel_text_address(addr))
97 #ifdef CONFIG_KALLSYMS
99 static int __init set_raw_show_trace(char *str)
104 __setup("raw_show_trace", set_raw_show_trace);
107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
109 unsigned long sp = regs->regs[29];
110 unsigned long ra = regs->regs[31];
111 unsigned long pc = regs->cp0_epc;
113 if (raw_show_trace || !__kernel_text_address(pc)) {
114 show_raw_backtrace(sp);
117 printk("Call Trace:\n");
120 pc = unwind_stack(task, &sp, pc, &ra);
126 * This routine abuses get_user()/put_user() to reference pointers
127 * with at least a bit of error checking ...
129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
131 const int field = 2 * sizeof(unsigned long);
134 unsigned long *sp = (unsigned long *)regs->regs[29];
138 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
139 if (i && ((i % (64 / field)) == 0))
146 if (__get_user(stackdata, sp++)) {
147 printk(" (Bad stack address)");
151 printk(" %0*lx", field, stackdata);
155 show_backtrace(task, regs);
158 void show_stack(struct task_struct *task, unsigned long *sp)
162 regs.regs[29] = (unsigned long)sp;
166 if (task && task != current) {
167 regs.regs[29] = task->thread.reg29;
169 regs.cp0_epc = task->thread.reg31;
171 prepare_frametrace(®s);
174 show_stacktrace(task, ®s);
178 * The architecture-independent dump_stack generator
180 void dump_stack(void)
184 prepare_frametrace(®s);
185 show_backtrace(current, ®s);
188 EXPORT_SYMBOL(dump_stack);
190 void show_code(unsigned int *pc)
196 for(i = -3 ; i < 6 ; i++) {
198 if (__get_user(insn, pc + i)) {
199 printk(" (Bad address in epc)\n");
202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
206 void show_regs(struct pt_regs *regs)
208 const int field = 2 * sizeof(unsigned long);
209 unsigned int cause = regs->cp0_cause;
212 printk("Cpu %d\n", smp_processor_id());
215 * Saved main processor registers
217 for (i = 0; i < 32; ) {
221 printk(" %0*lx", field, 0UL);
222 else if (i == 26 || i == 27)
223 printk(" %*s", field, "");
225 printk(" %0*lx", field, regs->regs[i]);
232 printk("Hi : %0*lx\n", field, regs->hi);
233 printk("Lo : %0*lx\n", field, regs->lo);
236 * Saved cp0 registers
238 printk("epc : %0*lx ", field, regs->cp0_epc);
239 print_symbol("%s ", regs->cp0_epc);
240 printk(" %s\n", print_tainted());
241 printk("ra : %0*lx ", field, regs->regs[31]);
242 print_symbol("%s\n", regs->regs[31]);
244 printk("Status: %08x ", (uint32_t) regs->cp0_status);
246 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
247 if (regs->cp0_status & ST0_KUO)
249 if (regs->cp0_status & ST0_IEO)
251 if (regs->cp0_status & ST0_KUP)
253 if (regs->cp0_status & ST0_IEP)
255 if (regs->cp0_status & ST0_KUC)
257 if (regs->cp0_status & ST0_IEC)
260 if (regs->cp0_status & ST0_KX)
262 if (regs->cp0_status & ST0_SX)
264 if (regs->cp0_status & ST0_UX)
266 switch (regs->cp0_status & ST0_KSU) {
271 printk("SUPERVISOR ");
280 if (regs->cp0_status & ST0_ERL)
282 if (regs->cp0_status & ST0_EXL)
284 if (regs->cp0_status & ST0_IE)
289 printk("Cause : %08x\n", cause);
291 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
292 if (1 <= cause && cause <= 5)
293 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
295 printk("PrId : %08x\n", read_c0_prid());
298 void show_registers(struct pt_regs *regs)
302 printk("Process %s (pid: %d:#%u, threadinfo=%p, task=%p)\n",
303 current->comm, current->pid, current->xid,
304 current_thread_info(), current);
305 show_stacktrace(current, regs);
306 show_code((unsigned int *) regs->cp0_epc);
310 static DEFINE_SPINLOCK(die_lock);
312 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
314 static int die_counter;
315 #ifdef CONFIG_MIPS_MT_SMTC
316 unsigned long dvpret = dvpe();
317 #endif /* CONFIG_MIPS_MT_SMTC */
320 spin_lock_irq(&die_lock);
322 #ifdef CONFIG_MIPS_MT_SMTC
323 mips_mt_regdump(dvpret);
324 #endif /* CONFIG_MIPS_MT_SMTC */
325 printk("%s[#%d]:\n", str, ++die_counter);
326 show_registers(regs);
327 spin_unlock_irq(&die_lock);
330 panic("Fatal exception in interrupt");
333 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
335 panic("Fatal exception");
341 extern const struct exception_table_entry __start___dbe_table[];
342 extern const struct exception_table_entry __stop___dbe_table[];
344 void __declare_dbe_table(void)
346 __asm__ __volatile__(
347 ".section\t__dbe_table,\"a\"\n\t"
352 /* Given an address, look for it in the exception tables. */
353 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
355 const struct exception_table_entry *e;
357 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
359 e = search_module_dbetables(addr);
363 asmlinkage void do_be(struct pt_regs *regs)
365 const int field = 2 * sizeof(unsigned long);
366 const struct exception_table_entry *fixup = NULL;
367 int data = regs->cp0_cause & 4;
368 int action = MIPS_BE_FATAL;
370 /* XXX For now. Fixme, this searches the wrong table ... */
371 if (data && !user_mode(regs))
372 fixup = search_dbe_tables(exception_epc(regs));
375 action = MIPS_BE_FIXUP;
377 if (board_be_handler)
378 action = board_be_handler(regs, fixup != 0);
381 case MIPS_BE_DISCARD:
385 regs->cp0_epc = fixup->nextinsn;
394 * Assume it would be too dangerous to continue ...
396 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
397 data ? "Data" : "Instruction",
398 field, regs->cp0_epc, field, regs->regs[31]);
399 die_if_kernel("Oops", regs);
400 force_sig(SIGBUS, current);
407 #define OPCODE 0xfc000000
408 #define BASE 0x03e00000
409 #define RT 0x001f0000
410 #define OFFSET 0x0000ffff
411 #define LL 0xc0000000
412 #define SC 0xe0000000
413 #define SPEC3 0x7c000000
414 #define RD 0x0000f800
415 #define FUNC 0x0000003f
416 #define RDHWR 0x0000003b
419 * The ll_bit is cleared by r*_switch.S
422 unsigned long ll_bit;
424 static struct task_struct *ll_task = NULL;
426 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
428 unsigned long value, __user *vaddr;
433 * analyse the ll instruction that just caused a ri exception
434 * and put the referenced address to addr.
437 /* sign extend offset */
438 offset = opcode & OFFSET;
442 vaddr = (unsigned long __user *)
443 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
445 if ((unsigned long)vaddr & 3) {
449 if (get_user(value, vaddr)) {
456 if (ll_task == NULL || ll_task == current) {
465 compute_return_epc(regs);
467 regs->regs[(opcode & RT) >> 16] = value;
472 force_sig(signal, current);
475 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
477 unsigned long __user *vaddr;
483 * analyse the sc instruction that just caused a ri exception
484 * and put the referenced address to addr.
487 /* sign extend offset */
488 offset = opcode & OFFSET;
492 vaddr = (unsigned long __user *)
493 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
494 reg = (opcode & RT) >> 16;
496 if ((unsigned long)vaddr & 3) {
503 if (ll_bit == 0 || ll_task != current) {
504 compute_return_epc(regs);
512 if (put_user(regs->regs[reg], vaddr)) {
517 compute_return_epc(regs);
523 force_sig(signal, current);
527 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
528 * opcodes are supposed to result in coprocessor unusable exceptions if
529 * executed on ll/sc-less processors. That's the theory. In practice a
530 * few processors such as NEC's VR4100 throw reserved instruction exceptions
531 * instead, so we're doing the emulation thing in both exception handlers.
533 static inline int simulate_llsc(struct pt_regs *regs)
537 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
540 if ((opcode & OPCODE) == LL) {
541 simulate_ll(regs, opcode);
544 if ((opcode & OPCODE) == SC) {
545 simulate_sc(regs, opcode);
549 return -EFAULT; /* Strange things going on ... */
552 force_sig(SIGSEGV, current);
557 * Simulate trapping 'rdhwr' instructions to provide user accessible
558 * registers not implemented in hardware. The only current use of this
559 * is the thread area pointer.
561 static inline int simulate_rdhwr(struct pt_regs *regs)
563 struct thread_info *ti = task_thread_info(current);
566 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
569 if (unlikely(compute_return_epc(regs)))
572 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
573 int rd = (opcode & RD) >> 11;
574 int rt = (opcode & RT) >> 16;
577 regs->regs[rt] = ti->tp_value;
588 force_sig(SIGSEGV, current);
592 asmlinkage void do_ov(struct pt_regs *regs)
596 die_if_kernel("Integer overflow", regs);
598 info.si_code = FPE_INTOVF;
599 info.si_signo = SIGFPE;
601 info.si_addr = (void __user *) regs->cp0_epc;
602 force_sig_info(SIGFPE, &info, current);
606 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
608 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
610 die_if_kernel("FP exception in kernel code", regs);
612 if (fcr31 & FPU_CSR_UNI_X) {
617 #ifdef CONFIG_PREEMPT
618 if (!is_fpu_owner()) {
619 /* We might lose fpu before disabling preempt... */
621 BUG_ON(!used_math());
626 * Unimplemented operation exception. If we've got the full
627 * software emulator on-board, let's use it...
629 * Force FPU to dump state into task/thread context. We're
630 * moving a lot of data here for what is probably a single
631 * instruction, but the alternative is to pre-decode the FP
632 * register operands before invoking the emulator, which seems
633 * a bit extreme for what should be an infrequent event.
636 /* Ensure 'resume' not overwrite saved fp context again. */
641 /* Run the emulator */
642 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1);
646 own_fpu(); /* Using the FPU again. */
648 * We can't allow the emulated instruction to leave any of
649 * the cause bit set in $fcr31.
651 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
653 /* Restore the hardware register state */
658 /* If something went wrong, signal */
660 force_sig(sig, current);
665 force_sig(SIGFPE, current);
668 asmlinkage void do_bp(struct pt_regs *regs)
670 unsigned int opcode, bcode;
673 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
677 * There is the ancient bug in the MIPS assemblers that the break
678 * code starts left to bit 16 instead to bit 6 in the opcode.
679 * Gas is bug-compatible, but not always, grrr...
680 * We handle both cases with a simple heuristics. --macro
682 bcode = ((opcode >> 6) & ((1 << 20) - 1));
683 if (bcode < (1 << 10))
687 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
688 * insns, even for break codes that indicate arithmetic failures.
690 * But should we continue the brokenness??? --macro
693 case BRK_OVERFLOW << 10:
694 case BRK_DIVZERO << 10:
695 die_if_kernel("Break instruction in kernel code", regs);
696 if (bcode == (BRK_DIVZERO << 10))
697 info.si_code = FPE_INTDIV;
699 info.si_code = FPE_INTOVF;
700 info.si_signo = SIGFPE;
702 info.si_addr = (void __user *) regs->cp0_epc;
703 force_sig_info(SIGFPE, &info, current);
706 die("Kernel bug detected", regs);
709 die_if_kernel("Break instruction in kernel code", regs);
710 force_sig(SIGTRAP, current);
714 force_sig(SIGSEGV, current);
717 asmlinkage void do_tr(struct pt_regs *regs)
719 unsigned int opcode, tcode = 0;
722 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
725 /* Immediate versions don't provide a code. */
726 if (!(opcode & OPCODE))
727 tcode = ((opcode >> 6) & ((1 << 10) - 1));
730 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
731 * insns, even for trap codes that indicate arithmetic failures.
733 * But should we continue the brokenness??? --macro
738 die_if_kernel("Trap instruction in kernel code", regs);
739 if (tcode == BRK_DIVZERO)
740 info.si_code = FPE_INTDIV;
742 info.si_code = FPE_INTOVF;
743 info.si_signo = SIGFPE;
745 info.si_addr = (void __user *) regs->cp0_epc;
746 force_sig_info(SIGFPE, &info, current);
749 die("Kernel bug detected", regs);
752 die_if_kernel("Trap instruction in kernel code", regs);
753 force_sig(SIGTRAP, current);
757 force_sig(SIGSEGV, current);
760 asmlinkage void do_ri(struct pt_regs *regs)
762 die_if_kernel("Reserved instruction in kernel code", regs);
765 if (!simulate_llsc(regs))
768 if (!simulate_rdhwr(regs))
771 force_sig(SIGILL, current);
774 asmlinkage void do_cpu(struct pt_regs *regs)
778 die_if_kernel("do_cpu invoked from kernel context!", regs);
780 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
785 if (!simulate_llsc(regs))
788 if (!simulate_rdhwr(regs))
797 if (used_math()) { /* Using the FPU again. */
799 } else { /* First time FPU user. */
809 sig = fpu_emulator_cop1Handler(regs,
810 ¤t->thread.fpu, 0);
812 force_sig(sig, current);
813 #ifdef CONFIG_MIPS_MT_FPAFF
816 * MIPS MT processors may have fewer FPU contexts
817 * than CPU threads. If we've emulated more than
818 * some threshold number of instructions, force
819 * migration to a "CPU" that has FP support.
821 if(mt_fpemul_threshold > 0
822 && ((current->thread.emulated_fp++
823 > mt_fpemul_threshold))) {
825 * If there's no FPU present, or if the
826 * application has already restricted
827 * the allowed set to exclude any CPUs
828 * with FPUs, we'll skip the procedure.
830 if (cpus_intersects(current->cpus_allowed,
835 current->thread.user_cpus_allowed,
837 set_cpus_allowed(current, tmask);
838 current->thread.mflags |= MF_FPUBOUND;
842 #endif /* CONFIG_MIPS_MT_FPAFF */
849 die_if_kernel("do_cpu invoked from kernel context!", regs);
853 force_sig(SIGILL, current);
856 asmlinkage void do_mdmx(struct pt_regs *regs)
858 force_sig(SIGILL, current);
861 asmlinkage void do_watch(struct pt_regs *regs)
864 * We use the watch exception where available to detect stack
869 panic("Caught WATCH exception - probably caused by stack overflow.");
872 asmlinkage void do_mcheck(struct pt_regs *regs)
874 const int field = 2 * sizeof(unsigned long);
875 int multi_match = regs->cp0_status & ST0_TS;
880 printk("Index : %0x\n", read_c0_index());
881 printk("Pagemask: %0x\n", read_c0_pagemask());
882 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
883 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
884 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
889 show_code((unsigned int *) regs->cp0_epc);
892 * Some chips may have other causes of machine check (e.g. SB1
895 panic("Caught Machine Check exception - %scaused by multiple "
896 "matching entries in the TLB.",
897 (multi_match) ? "" : "not ");
900 asmlinkage void do_mt(struct pt_regs *regs)
904 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
905 >> VPECONTROL_EXCPT_SHIFT;
908 printk(KERN_DEBUG "Thread Underflow\n");
911 printk(KERN_DEBUG "Thread Overflow\n");
914 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
917 printk(KERN_DEBUG "Gating Storage Exception\n");
920 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
923 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
926 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
930 die_if_kernel("MIPS MT Thread exception in kernel", regs);
932 force_sig(SIGILL, current);
936 asmlinkage void do_dsp(struct pt_regs *regs)
939 panic("Unexpected DSP exception\n");
941 force_sig(SIGILL, current);
944 asmlinkage void do_reserved(struct pt_regs *regs)
947 * Game over - no way to handle this if it ever occurs. Most probably
948 * caused by a new unknown cpu type or after another deadly
949 * hard/software error.
952 panic("Caught reserved exception %ld - should not happen.",
953 (regs->cp0_cause & 0x7f) >> 2);
956 asmlinkage void do_default_vi(struct pt_regs *regs)
959 panic("Caught unexpected vectored interrupt.");
963 * Some MIPS CPUs can enable/disable for cache parity detection, but do
966 static inline void parity_protection_init(void)
968 switch (current_cpu_data.cputype) {
972 write_c0_ecc(0x80000000);
973 back_to_back_c0_hazard();
974 /* Set the PE bit (bit 31) in the c0_errctl register. */
975 printk(KERN_INFO "Cache parity protection %sabled\n",
976 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
980 /* Clear the DE bit (bit 16) in the c0_status register. */
981 printk(KERN_INFO "Enable cache parity protection for "
982 "MIPS 20KC/25KF CPUs.\n");
983 clear_c0_status(ST0_DE);
990 asmlinkage void cache_parity_error(void)
992 const int field = 2 * sizeof(unsigned long);
993 unsigned int reg_val;
995 /* For the moment, report the problem and hang. */
996 printk("Cache error exception:\n");
997 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
998 reg_val = read_c0_cacheerr();
999 printk("c0_cacheerr == %08x\n", reg_val);
1001 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1002 reg_val & (1<<30) ? "secondary" : "primary",
1003 reg_val & (1<<31) ? "data" : "insn");
1004 printk("Error bits: %s%s%s%s%s%s%s\n",
1005 reg_val & (1<<29) ? "ED " : "",
1006 reg_val & (1<<28) ? "ET " : "",
1007 reg_val & (1<<26) ? "EE " : "",
1008 reg_val & (1<<25) ? "EB " : "",
1009 reg_val & (1<<24) ? "EI " : "",
1010 reg_val & (1<<23) ? "E1 " : "",
1011 reg_val & (1<<22) ? "E0 " : "");
1012 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1014 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1015 if (reg_val & (1<<22))
1016 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1018 if (reg_val & (1<<23))
1019 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1022 panic("Can't handle the cache error!");
1026 * SDBBP EJTAG debug exception handler.
1027 * We skip the instruction and return to the next instruction.
1029 void ejtag_exception_handler(struct pt_regs *regs)
1031 const int field = 2 * sizeof(unsigned long);
1032 unsigned long depc, old_epc;
1035 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1036 depc = read_c0_depc();
1037 debug = read_c0_debug();
1038 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1039 if (debug & 0x80000000) {
1041 * In branch delay slot.
1042 * We cheat a little bit here and use EPC to calculate the
1043 * debug return address (DEPC). EPC is restored after the
1046 old_epc = regs->cp0_epc;
1047 regs->cp0_epc = depc;
1048 __compute_return_epc(regs);
1049 depc = regs->cp0_epc;
1050 regs->cp0_epc = old_epc;
1053 write_c0_depc(depc);
1056 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1057 write_c0_debug(debug | 0x100);
1062 * NMI exception handler.
1064 void nmi_exception_handler(struct pt_regs *regs)
1066 #ifdef CONFIG_MIPS_MT_SMTC
1067 unsigned long dvpret = dvpe();
1069 printk("NMI taken!!!!\n");
1070 mips_mt_regdump(dvpret);
1073 printk("NMI taken!!!!\n");
1074 #endif /* CONFIG_MIPS_MT_SMTC */
1079 #define VECTORSPACING 0x100 /* for EI/VI mode */
1081 unsigned long ebase;
1082 unsigned long exception_handlers[32];
1083 unsigned long vi_handlers[64];
1086 * As a side effect of the way this is implemented we're limited
1087 * to interrupt handlers in the address range from
1088 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1090 void *set_except_vector(int n, void *addr)
1092 unsigned long handler = (unsigned long) addr;
1093 unsigned long old_handler = exception_handlers[n];
1095 exception_handlers[n] = handler;
1096 if (n == 0 && cpu_has_divec) {
1097 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1098 (0x03ffffff & (handler >> 2));
1099 flush_icache_range(ebase + 0x200, ebase + 0x204);
1101 return (void *)old_handler;
1104 #ifdef CONFIG_CPU_MIPSR2_SRS
1106 * MIPSR2 shadow register set allocation
1110 static struct shadow_registers {
1112 * Number of shadow register sets supported
1114 unsigned long sr_supported;
1116 * Bitmap of allocated shadow registers
1118 unsigned long sr_allocated;
1121 static void mips_srs_init(void)
1123 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1124 printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1125 shadow_registers.sr_supported);
1126 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1129 int mips_srs_max(void)
1131 return shadow_registers.sr_supported;
1134 int mips_srs_alloc(void)
1136 struct shadow_registers *sr = &shadow_registers;
1140 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1141 if (set >= sr->sr_supported)
1144 if (test_and_set_bit(set, &sr->sr_allocated))
1150 void mips_srs_free(int set)
1152 struct shadow_registers *sr = &shadow_registers;
1154 clear_bit(set, &sr->sr_allocated);
1157 static void *set_vi_srs_handler(int n, void *addr, int srs)
1159 unsigned long handler;
1160 unsigned long old_handler = vi_handlers[n];
1164 if (!cpu_has_veic && !cpu_has_vint)
1168 handler = (unsigned long) do_default_vi;
1171 handler = (unsigned long) addr;
1172 vi_handlers[n] = (unsigned long) addr;
1174 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1176 if (srs >= mips_srs_max())
1177 panic("Shadow register set %d not supported", srs);
1180 if (board_bind_eic_interrupt)
1181 board_bind_eic_interrupt (n, srs);
1182 } else if (cpu_has_vint) {
1183 /* SRSMap is only defined if shadow sets are implemented */
1184 if (mips_srs_max() > 1)
1185 change_c0_srsmap (0xf << n*4, srs << n*4);
1190 * If no shadow set is selected then use the default handler
1191 * that does normal register saving and a standard interrupt exit
1194 extern char except_vec_vi, except_vec_vi_lui;
1195 extern char except_vec_vi_ori, except_vec_vi_end;
1196 #ifdef CONFIG_MIPS_MT_SMTC
1198 * We need to provide the SMTC vectored interrupt handler
1199 * not only with the address of the handler, but with the
1200 * Status.IM bit to be masked before going there.
1202 extern char except_vec_vi_mori;
1203 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1204 #endif /* CONFIG_MIPS_MT_SMTC */
1205 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1206 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1207 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1209 if (handler_len > VECTORSPACING) {
1211 * Sigh... panicing won't help as the console
1212 * is probably not configured :(
1214 panic ("VECTORSPACING too small");
1217 memcpy (b, &except_vec_vi, handler_len);
1218 #ifdef CONFIG_MIPS_MT_SMTC
1220 printk("Vector index %d exceeds SMTC maximum\n", n);
1221 w = (u32 *)(b + mori_offset);
1222 *w = (*w & 0xffff0000) | (0x100 << n);
1223 #endif /* CONFIG_MIPS_MT_SMTC */
1224 w = (u32 *)(b + lui_offset);
1225 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1226 w = (u32 *)(b + ori_offset);
1227 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1228 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1232 * In other cases jump directly to the interrupt handler
1234 * It is the handlers responsibility to save registers if required
1235 * (eg hi/lo) and return from the exception using "eret"
1238 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1240 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1243 return (void *)old_handler;
1246 void *set_vi_handler(int n, void *addr)
1248 return set_vi_srs_handler(n, addr, 0);
1253 static inline void mips_srs_init(void)
1257 #endif /* CONFIG_CPU_MIPSR2_SRS */
1260 * This is used by native signal handling
1262 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1263 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1265 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1266 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1268 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1269 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1272 static int smp_save_fp_context(struct sigcontext *sc)
1275 ? _save_fp_context(sc)
1276 : fpu_emulator_save_context(sc);
1279 static int smp_restore_fp_context(struct sigcontext *sc)
1282 ? _restore_fp_context(sc)
1283 : fpu_emulator_restore_context(sc);
1287 static inline void signal_init(void)
1290 /* For now just do the cpu_has_fpu check when the functions are invoked */
1291 save_fp_context = smp_save_fp_context;
1292 restore_fp_context = smp_restore_fp_context;
1295 save_fp_context = _save_fp_context;
1296 restore_fp_context = _restore_fp_context;
1298 save_fp_context = fpu_emulator_save_context;
1299 restore_fp_context = fpu_emulator_restore_context;
1304 #ifdef CONFIG_MIPS32_COMPAT
1307 * This is used by 32-bit signal stuff on the 64-bit kernel
1309 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1310 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1312 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1313 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1315 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1316 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1318 static inline void signal32_init(void)
1321 save_fp_context32 = _save_fp_context32;
1322 restore_fp_context32 = _restore_fp_context32;
1324 save_fp_context32 = fpu_emulator_save_context32;
1325 restore_fp_context32 = fpu_emulator_restore_context32;
1330 extern void cpu_cache_init(void);
1331 extern void tlb_init(void);
1332 extern void flush_tlb_handlers(void);
1334 void __init per_cpu_trap_init(void)
1336 unsigned int cpu = smp_processor_id();
1337 unsigned int status_set = ST0_CU0;
1338 #ifdef CONFIG_MIPS_MT_SMTC
1339 int secondaryTC = 0;
1340 int bootTC = (cpu == 0);
1343 * Only do per_cpu_trap_init() for first TC of Each VPE.
1344 * Note that this hack assumes that the SMTC init code
1345 * assigns TCs consecutively and in ascending order.
1348 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1349 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1351 #endif /* CONFIG_MIPS_MT_SMTC */
1354 * Disable coprocessors and select 32-bit or 64-bit addressing
1355 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1356 * flag that some firmware may have left set and the TS bit (for
1357 * IP27). Set XX for ISA IV code to work.
1360 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1362 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1363 status_set |= ST0_XX;
1364 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1368 set_c0_status(ST0_MX);
1370 #ifdef CONFIG_CPU_MIPSR2
1371 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1374 #ifdef CONFIG_MIPS_MT_SMTC
1376 #endif /* CONFIG_MIPS_MT_SMTC */
1379 * Interrupt handling.
1381 if (cpu_has_veic || cpu_has_vint) {
1382 write_c0_ebase (ebase);
1383 /* Setting vector spacing enables EI/VI mode */
1384 change_c0_intctl (0x3e0, VECTORSPACING);
1386 if (cpu_has_divec) {
1387 if (cpu_has_mipsmt) {
1388 unsigned int vpflags = dvpe();
1389 set_c0_cause(CAUSEF_IV);
1392 set_c0_cause(CAUSEF_IV);
1394 #ifdef CONFIG_MIPS_MT_SMTC
1396 #endif /* CONFIG_MIPS_MT_SMTC */
1398 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1399 TLBMISS_HANDLER_SETUP();
1401 atomic_inc(&init_mm.mm_count);
1402 current->active_mm = &init_mm;
1403 BUG_ON(current->mm);
1404 enter_lazy_tlb(&init_mm, current);
1406 #ifdef CONFIG_MIPS_MT_SMTC
1408 #endif /* CONFIG_MIPS_MT_SMTC */
1411 #ifdef CONFIG_MIPS_MT_SMTC
1413 #endif /* CONFIG_MIPS_MT_SMTC */
1416 /* Install CPU exception handler */
1417 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1419 memcpy((void *)(ebase + offset), addr, size);
1420 flush_icache_range(ebase + offset, ebase + offset + size);
1423 /* Install uncached CPU exception handler */
1424 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1427 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1430 unsigned long uncached_ebase = TO_UNCAC(ebase);
1433 memcpy((void *)(uncached_ebase + offset), addr, size);
1436 static int __initdata rdhwr_noopt;
1437 static int __init set_rdhwr_noopt(char *str)
1443 __setup("rdhwr_noopt", set_rdhwr_noopt);
1445 void __init trap_init(void)
1447 extern char except_vec3_generic, except_vec3_r4000;
1448 extern char except_vec4;
1451 if (cpu_has_veic || cpu_has_vint)
1452 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1458 per_cpu_trap_init();
1461 * Copy the generic exception handlers to their final destination.
1462 * This will be overriden later as suitable for a particular
1465 set_handler(0x180, &except_vec3_generic, 0x80);
1468 * Setup default vectors
1470 for (i = 0; i <= 31; i++)
1471 set_except_vector(i, handle_reserved);
1474 * Copy the EJTAG debug exception vector handler code to it's final
1477 if (cpu_has_ejtag && board_ejtag_handler_setup)
1478 board_ejtag_handler_setup ();
1481 * Only some CPUs have the watch exceptions.
1484 set_except_vector(23, handle_watch);
1487 * Initialise interrupt handlers
1489 if (cpu_has_veic || cpu_has_vint) {
1490 int nvec = cpu_has_veic ? 64 : 8;
1491 for (i = 0; i < nvec; i++)
1492 set_vi_handler(i, NULL);
1494 else if (cpu_has_divec)
1495 set_handler(0x200, &except_vec4, 0x8);
1498 * Some CPUs can enable/disable for cache parity detection, but does
1499 * it different ways.
1501 parity_protection_init();
1504 * The Data Bus Errors / Instruction Bus Errors are signaled
1505 * by external hardware. Therefore these two exceptions
1506 * may have board specific handlers.
1511 set_except_vector(0, handle_int);
1512 set_except_vector(1, handle_tlbm);
1513 set_except_vector(2, handle_tlbl);
1514 set_except_vector(3, handle_tlbs);
1516 set_except_vector(4, handle_adel);
1517 set_except_vector(5, handle_ades);
1519 set_except_vector(6, handle_ibe);
1520 set_except_vector(7, handle_dbe);
1522 set_except_vector(8, handle_sys);
1523 set_except_vector(9, handle_bp);
1524 set_except_vector(10, rdhwr_noopt ? handle_ri :
1525 (cpu_has_vtag_icache ?
1526 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1527 set_except_vector(11, handle_cpu);
1528 set_except_vector(12, handle_ov);
1529 set_except_vector(13, handle_tr);
1531 if (current_cpu_data.cputype == CPU_R6000 ||
1532 current_cpu_data.cputype == CPU_R6000A) {
1534 * The R6000 is the only R-series CPU that features a machine
1535 * check exception (similar to the R4000 cache error) and
1536 * unaligned ldc1/sdc1 exception. The handlers have not been
1537 * written yet. Well, anyway there is no R6000 machine on the
1538 * current list of targets for Linux/MIPS.
1539 * (Duh, crap, there is someone with a triple R6k machine)
1541 //set_except_vector(14, handle_mc);
1542 //set_except_vector(15, handle_ndc);
1546 if (board_nmi_handler_setup)
1547 board_nmi_handler_setup();
1549 if (cpu_has_fpu && !cpu_has_nofpuex)
1550 set_except_vector(15, handle_fpe);
1552 set_except_vector(22, handle_mdmx);
1555 set_except_vector(24, handle_mcheck);
1558 set_except_vector(25, handle_mt);
1561 set_except_vector(26, handle_dsp);
1564 /* Special exception: R4[04]00 uses also the divec space. */
1565 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1566 else if (cpu_has_4kex)
1567 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1569 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1572 #ifdef CONFIG_MIPS32_COMPAT
1576 flush_icache_range(ebase, ebase + 0x400);
1577 flush_tlb_handlers();