2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
28 #include <asm/module.h>
29 #include <asm/pgtable.h>
30 #include <asm/ptrace.h>
31 #include <asm/sections.h>
32 #include <asm/system.h>
33 #include <asm/tlbdebug.h>
34 #include <asm/traps.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/watch.h>
38 #include <asm/types.h>
40 extern asmlinkage void handle_mod(void);
41 extern asmlinkage void handle_tlbl(void);
42 extern asmlinkage void handle_tlbs(void);
43 extern asmlinkage void __xtlb_mod(void);
44 extern asmlinkage void __xtlb_tlbl(void);
45 extern asmlinkage void __xtlb_tlbs(void);
46 extern asmlinkage void handle_adel(void);
47 extern asmlinkage void handle_ades(void);
48 extern asmlinkage void handle_ibe(void);
49 extern asmlinkage void handle_dbe(void);
50 extern asmlinkage void handle_sys(void);
51 extern asmlinkage void handle_bp(void);
52 extern asmlinkage void handle_ri(void);
53 extern asmlinkage void handle_cpu(void);
54 extern asmlinkage void handle_ov(void);
55 extern asmlinkage void handle_tr(void);
56 extern asmlinkage void handle_fpe(void);
57 extern asmlinkage void handle_mdmx(void);
58 extern asmlinkage void handle_watch(void);
59 extern asmlinkage void handle_mcheck(void);
60 extern asmlinkage void handle_reserved(void);
62 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
63 struct mips_fpu_soft_struct *ctx);
65 void (*board_be_init)(void);
66 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
69 * These constant is for searching for possible module text segments.
70 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
72 #define MODULE_RANGE (8*1024*1024)
75 * This routine abuses get_user()/put_user() to reference pointers
76 * with at least a bit of error checking ...
78 void show_stack(struct task_struct *task, unsigned long *sp)
80 const int field = 2 * sizeof(unsigned long);
84 sp = sp ? sp : (unsigned long *) &sp;
88 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
89 if (i && ((i % (64 / field)) == 0))
96 if (__get_user(stackdata, sp++)) {
97 printk(" (Bad stack address)");
101 printk(" %0*lx", field, stackdata);
107 void show_trace(struct task_struct *task, unsigned long *stack)
109 const int field = 2 * sizeof(unsigned long);
113 stack = (unsigned long*)&stack;
115 printk("Call Trace:");
116 #ifdef CONFIG_KALLSYMS
119 while (!kstack_end(stack)) {
121 if (kernel_text_address(addr)) {
122 printk(" [<%0*lx>] ", field, addr);
123 print_symbol("%s\n", addr);
130 * The architecture-independent dump_stack generator
132 void dump_stack(void)
136 show_trace(current, &stack);
139 EXPORT_SYMBOL(dump_stack);
141 void show_code(unsigned int *pc)
147 for(i = -3 ; i < 6 ; i++) {
149 if (__get_user(insn, pc + i)) {
150 printk(" (Bad address in epc)\n");
153 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
157 void show_regs(struct pt_regs *regs)
159 const int field = 2 * sizeof(unsigned long);
160 unsigned int cause = regs->cp0_cause;
163 printk("Cpu %d\n", smp_processor_id());
166 * Saved main processor registers
168 for (i = 0; i < 32; ) {
172 printk(" %0*lx", field, 0UL);
173 else if (i == 26 || i == 27)
174 printk(" %*s", field, "");
176 printk(" %0*lx", field, regs->regs[i]);
183 printk("Hi : %0*lx\n", field, regs->hi);
184 printk("Lo : %0*lx\n", field, regs->lo);
187 * Saved cp0 registers
189 printk("epc : %0*lx ", field, regs->cp0_epc);
190 print_symbol("%s ", regs->cp0_epc);
191 printk(" %s\n", print_tainted());
192 printk("ra : %0*lx ", field, regs->regs[31]);
193 print_symbol("%s\n", regs->regs[31]);
195 printk("Status: %08x ", (uint32_t) regs->cp0_status);
197 if (regs->cp0_status & ST0_KX)
199 if (regs->cp0_status & ST0_SX)
201 if (regs->cp0_status & ST0_UX)
203 switch (regs->cp0_status & ST0_KSU) {
208 printk("SUPERVISOR ");
217 if (regs->cp0_status & ST0_ERL)
219 if (regs->cp0_status & ST0_EXL)
221 if (regs->cp0_status & ST0_IE)
225 printk("Cause : %08x\n", cause);
227 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
228 if (1 <= cause && cause <= 5)
229 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
231 printk("PrId : %08x\n", read_c0_prid());
234 void show_registers(struct pt_regs *regs)
237 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
238 current->comm, current->pid, current_thread_info(), current);
239 show_stack(current, (long *) regs->regs[29]);
240 show_trace(current, (long *) regs->regs[29]);
241 show_code((unsigned int *) regs->cp0_epc);
245 static spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
247 NORET_TYPE void __die(const char * str, struct pt_regs * regs,
248 const char * file, const char * func, unsigned long line)
250 static int die_counter;
253 spin_lock_irq(&die_lock);
256 printk(" in %s:%s, line %ld", file, func, line);
257 printk("[#%d]:\n", ++die_counter);
258 show_registers(regs);
259 spin_unlock_irq(&die_lock);
263 void __die_if_kernel(const char * str, struct pt_regs * regs,
264 const char * file, const char * func, unsigned long line)
266 if (!user_mode(regs))
267 __die(str, regs, file, func, line);
270 extern const struct exception_table_entry __start___dbe_table[];
271 extern const struct exception_table_entry __stop___dbe_table[];
273 void __declare_dbe_table(void)
275 __asm__ __volatile__(
276 ".section\t__dbe_table,\"a\"\n\t"
283 /* Given an address, look for it in the module exception tables. */
284 const struct exception_table_entry *search_module_dbetables(unsigned long addr)
287 const struct exception_table_entry *e = NULL;
290 spin_lock_irqsave(&modlist_lock, flags);
291 list_for_each_entry(mod, &modules, list) {
292 if (mod->arch.num_dbeentries == 0)
295 e = search_extable(mod->arch.dbe_table_start,
296 mod->arch.dbe_table_end +
297 mod->arch.num_dbeentries - 1,
302 spin_unlock_irqrestore(&modlist_lock, flags);
304 /* Now, if we found one, we are running inside it now, hence
305 we cannot unload the module, hence no refcnt needed. */
311 /* Given an address, look for it in the exception tables. */
312 static inline const struct exception_table_entry *
313 search_module_dbetables(unsigned long addr)
320 /* Given an address, look for it in the exception tables. */
321 const struct exception_table_entry *search_dbe_tables(unsigned long addr)
323 const struct exception_table_entry *e;
325 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
327 e = search_module_dbetables(addr);
331 asmlinkage void do_be(struct pt_regs *regs)
333 const int field = 2 * sizeof(unsigned long);
334 const struct exception_table_entry *fixup = NULL;
335 int data = regs->cp0_cause & 4;
336 int action = MIPS_BE_FATAL;
338 /* XXX For now. Fixme, this searches the wrong table ... */
339 if (data && !user_mode(regs))
340 fixup = search_dbe_tables(exception_epc(regs));
343 action = MIPS_BE_FIXUP;
345 if (board_be_handler)
346 action = board_be_handler(regs, fixup != 0);
349 case MIPS_BE_DISCARD:
353 regs->cp0_epc = fixup->nextinsn;
362 * Assume it would be too dangerous to continue ...
364 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
365 data ? "Data" : "Instruction",
366 field, regs->cp0_epc, field, regs->regs[31]);
367 die_if_kernel("Oops", regs);
368 force_sig(SIGBUS, current);
371 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
375 epc = (unsigned int *) regs->cp0_epc +
376 ((regs->cp0_cause & CAUSEF_BD) != 0);
377 if (!get_user(*opcode, epc))
380 force_sig(SIGSEGV, current);
388 #define OPCODE 0xfc000000
389 #define BASE 0x03e00000
390 #define RT 0x001f0000
391 #define OFFSET 0x0000ffff
392 #define LL 0xc0000000
393 #define SC 0xe0000000
396 * The ll_bit is cleared by r*_switch.S
399 unsigned long ll_bit;
401 static struct task_struct *ll_task = NULL;
403 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
405 unsigned long value, *vaddr;
410 * analyse the ll instruction that just caused a ri exception
411 * and put the referenced address to addr.
414 /* sign extend offset */
415 offset = opcode & OFFSET;
419 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
421 if ((unsigned long)vaddr & 3) {
425 if (get_user(value, vaddr)) {
430 if (ll_task == NULL || ll_task == current) {
437 regs->regs[(opcode & RT) >> 16] = value;
439 compute_return_epc(regs);
443 force_sig(signal, current);
446 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
448 unsigned long *vaddr, reg;
453 * analyse the sc instruction that just caused a ri exception
454 * and put the referenced address to addr.
457 /* sign extend offset */
458 offset = opcode & OFFSET;
462 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
463 reg = (opcode & RT) >> 16;
465 if ((unsigned long)vaddr & 3) {
469 if (ll_bit == 0 || ll_task != current) {
471 compute_return_epc(regs);
475 if (put_user(regs->regs[reg], vaddr)) {
482 compute_return_epc(regs);
486 force_sig(signal, current);
490 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
491 * opcodes are supposed to result in coprocessor unusable exceptions if
492 * executed on ll/sc-less processors. That's the theory. In practice a
493 * few processors such as NEC's VR4100 throw reserved instruction exceptions
494 * instead, so we're doing the emulation thing in both exception handlers.
496 static inline int simulate_llsc(struct pt_regs *regs)
500 if (unlikely(get_insn_opcode(regs, &opcode)))
503 if ((opcode & OPCODE) == LL) {
504 simulate_ll(regs, opcode);
507 if ((opcode & OPCODE) == SC) {
508 simulate_sc(regs, opcode);
512 return -EFAULT; /* Strange things going on ... */
515 asmlinkage void do_ov(struct pt_regs *regs)
519 info.si_code = FPE_INTOVF;
520 info.si_signo = SIGFPE;
522 info.si_addr = (void *)regs->cp0_epc;
523 force_sig_info(SIGFPE, &info, current);
527 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
529 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
531 if (fcr31 & FPU_CSR_UNI_X) {
535 * Unimplemented operation exception. If we've got the full
536 * software emulator on-board, let's use it...
538 * Force FPU to dump state into task/thread context. We're
539 * moving a lot of data here for what is probably a single
540 * instruction, but the alternative is to pre-decode the FP
541 * register operands before invoking the emulator, which seems
542 * a bit extreme for what should be an infrequent event.
546 /* Run the emulator */
547 sig = fpu_emulator_cop1Handler (0, regs,
548 ¤t->thread.fpu.soft);
551 * We can't allow the emulated instruction to leave any of
552 * the cause bit set in $fcr31.
554 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
556 /* Restore the hardware register state */
559 /* If something went wrong, signal */
561 force_sig(sig, current);
566 force_sig(SIGFPE, current);
569 asmlinkage void do_bp(struct pt_regs *regs)
571 unsigned int opcode, bcode;
574 die_if_kernel("Break instruction in kernel code", regs);
576 if (get_insn_opcode(regs, &opcode))
580 * There is the ancient bug in the MIPS assemblers that the break
581 * code starts left to bit 16 instead to bit 6 in the opcode.
582 * Gas is bug-compatible ...
584 bcode = ((opcode >> 16) & ((1 << 20) - 1));
587 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
588 * insns, even for break codes that indicate arithmetic failures.
590 * But should we continue the brokenness??? --macro
596 info.si_code = FPE_INTDIV;
598 info.si_code = FPE_INTOVF;
599 info.si_signo = SIGFPE;
601 info.si_addr = (void *)regs->cp0_epc;
602 force_sig_info(SIGFPE, &info, current);
605 force_sig(SIGTRAP, current);
609 asmlinkage void do_tr(struct pt_regs *regs)
611 unsigned int opcode, tcode = 0;
614 die_if_kernel("Trap instruction in kernel code", regs);
616 if (get_insn_opcode(regs, &opcode))
619 /* Immediate versions don't provide a code. */
620 if (!(opcode & OPCODE))
621 tcode = ((opcode >> 6) & ((1 << 20) - 1));
624 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
625 * insns, even for trap codes that indicate arithmetic failures.
627 * But should we continue the brokenness??? --macro
633 info.si_code = FPE_INTDIV;
635 info.si_code = FPE_INTOVF;
636 info.si_signo = SIGFPE;
638 info.si_addr = (void *)regs->cp0_epc;
639 force_sig_info(SIGFPE, &info, current);
642 force_sig(SIGTRAP, current);
646 asmlinkage void do_ri(struct pt_regs *regs)
648 die_if_kernel("Reserved instruction in kernel code", regs);
651 if (!simulate_llsc(regs))
654 force_sig(SIGILL, current);
657 asmlinkage void do_cpu(struct pt_regs *regs)
661 die_if_kernel("do_cpu invoked from kernel context!", regs);
663 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
670 if (!simulate_llsc(regs))
676 if (current->used_math) { /* Using the FPU again. */
678 } else { /* First time FPU user. */
680 current->used_math = 1;
684 int sig = fpu_emulator_cop1Handler(0, regs,
685 ¤t->thread.fpu.soft);
687 force_sig(sig, current);
697 force_sig(SIGILL, current);
700 asmlinkage void do_mdmx(struct pt_regs *regs)
702 force_sig(SIGILL, current);
705 asmlinkage void do_watch(struct pt_regs *regs)
708 * We use the watch exception where available to detect stack
713 panic("Caught WATCH exception - probably caused by stack overflow.");
716 asmlinkage void do_mcheck(struct pt_regs *regs)
721 * Some chips may have other causes of machine check (e.g. SB1
724 panic("Caught Machine Check exception - %scaused by multiple "
725 "matching entries in the TLB.",
726 (regs->cp0_status & ST0_TS) ? "" : "not ");
729 asmlinkage void do_reserved(struct pt_regs *regs)
732 * Game over - no way to handle this if it ever occurs. Most probably
733 * caused by a new unknown cpu type or after another deadly
734 * hard/software error.
737 panic("Caught reserved exception %ld - should not happen.",
738 (regs->cp0_cause & 0x7f) >> 2);
742 * Some MIPS CPUs can enable/disable for cache parity detection, but do
745 static inline void parity_protection_init(void)
747 switch (current_cpu_data.cputype) {
749 /* Set the PE bit (bit 31) in the c0_ecc register. */
750 printk(KERN_INFO "Enable the cache parity protection for "
752 write_c0_ecc(read_c0_ecc() | 0x80000000);
759 asmlinkage void cache_parity_error(void)
761 const int field = 2 * sizeof(unsigned long);
762 unsigned int reg_val;
764 /* For the moment, report the problem and hang. */
765 printk("Cache error exception:\n");
766 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
767 reg_val = read_c0_cacheerr();
768 printk("c0_cacheerr == %08x\n", reg_val);
770 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
771 reg_val & (1<<30) ? "secondary" : "primary",
772 reg_val & (1<<31) ? "data" : "insn");
773 printk("Error bits: %s%s%s%s%s%s%s\n",
774 reg_val & (1<<29) ? "ED " : "",
775 reg_val & (1<<28) ? "ET " : "",
776 reg_val & (1<<26) ? "EE " : "",
777 reg_val & (1<<25) ? "EB " : "",
778 reg_val & (1<<24) ? "EI " : "",
779 reg_val & (1<<23) ? "E1 " : "",
780 reg_val & (1<<22) ? "E0 " : "");
781 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
783 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
784 if (reg_val & (1<<22))
785 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
787 if (reg_val & (1<<23))
788 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
791 panic("Can't handle the cache error!");
795 * SDBBP EJTAG debug exception handler.
796 * We skip the instruction and return to the next instruction.
798 void ejtag_exception_handler(struct pt_regs *regs)
800 const int field = 2 * sizeof(unsigned long);
801 unsigned long depc, old_epc;
804 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
805 depc = read_c0_depc();
806 debug = read_c0_debug();
807 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
808 if (debug & 0x80000000) {
810 * In branch delay slot.
811 * We cheat a little bit here and use EPC to calculate the
812 * debug return address (DEPC). EPC is restored after the
815 old_epc = regs->cp0_epc;
816 regs->cp0_epc = depc;
817 __compute_return_epc(regs);
818 depc = regs->cp0_epc;
819 regs->cp0_epc = old_epc;
825 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
826 write_c0_debug(debug | 0x100);
831 * NMI exception handler.
833 void nmi_exception_handler(struct pt_regs *regs)
835 printk("NMI taken!!!!\n");
840 unsigned long exception_handlers[32];
843 * As a side effect of the way this is implemented we're limited
844 * to interrupt handlers in the address range from
845 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
847 void *set_except_vector(int n, void *addr)
849 unsigned long handler = (unsigned long) addr;
850 unsigned long old_handler = exception_handlers[n];
852 exception_handlers[n] = handler;
853 if (n == 0 && cpu_has_divec) {
854 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 |
855 (0x03ffffff & (handler >> 2));
856 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204);
858 return (void *)old_handler;
862 * This is used by native signal handling
864 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
865 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
867 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
868 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
870 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
871 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
873 static inline void signal_init(void)
876 save_fp_context = _save_fp_context;
877 restore_fp_context = _restore_fp_context;
879 save_fp_context = fpu_emulator_save_context;
880 restore_fp_context = fpu_emulator_restore_context;
884 #ifdef CONFIG_MIPS32_COMPAT
887 * This is used by 32-bit signal stuff on the 64-bit kernel
889 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
890 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
892 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
893 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
895 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
896 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
898 static inline void signal32_init(void)
901 save_fp_context32 = _save_fp_context32;
902 restore_fp_context32 = _restore_fp_context32;
904 save_fp_context32 = fpu_emulator_save_context32;
905 restore_fp_context32 = fpu_emulator_restore_context32;
910 extern void cpu_cache_init(void);
911 extern void tlb_init(void);
913 void __init per_cpu_trap_init(void)
915 unsigned int cpu = smp_processor_id();
917 /* Some firmware leaves the BEV flag set, clear it. */
918 clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV);
920 set_c0_status(ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX);
923 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
924 set_c0_status(ST0_XX);
927 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
928 * interrupt processing overhead. Use it where available.
931 set_c0_cause(CAUSEF_IV);
933 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
934 TLBMISS_HANDLER_SETUP();
936 atomic_inc(&init_mm.mm_count);
937 current->active_mm = &init_mm;
939 enter_lazy_tlb(&init_mm, current);
945 void __init trap_init(void)
947 extern char except_vec3_generic, except_vec3_r4000;
948 extern char except_vec_ejtag_debug;
949 extern char except_vec4;
955 * Copy the generic exception handlers to their final destination.
956 * This will be overriden later as suitable for a particular
959 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
962 * Setup default vectors
964 for (i = 0; i <= 31; i++)
965 set_except_vector(i, handle_reserved);
968 * Copy the EJTAG debug exception vector handler code to it's final
972 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80);
975 * Only some CPUs have the watch exceptions.
978 set_except_vector(23, handle_watch);
981 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
982 * interrupt processing overhead. Use it where available.
985 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8);
988 * Some CPUs can enable/disable for cache parity detection, but does
991 parity_protection_init();
994 * The Data Bus Errors / Instruction Bus Errors are signaled
995 * by external hardware. Therefore these two exceptions
996 * may have board specific handlers.
1001 #ifdef CONFIG_MIPS32
1002 set_except_vector(1, handle_mod);
1003 set_except_vector(2, handle_tlbl);
1004 set_except_vector(3, handle_tlbs);
1006 #ifdef CONFIG_MIPS64
1007 set_except_vector(1, __xtlb_mod);
1008 set_except_vector(2, __xtlb_tlbl);
1009 set_except_vector(3, __xtlb_tlbs);
1011 set_except_vector(4, handle_adel);
1012 set_except_vector(5, handle_ades);
1014 set_except_vector(6, handle_ibe);
1015 set_except_vector(7, handle_dbe);
1017 set_except_vector(8, handle_sys);
1018 set_except_vector(9, handle_bp);
1019 set_except_vector(10, handle_ri);
1020 set_except_vector(11, handle_cpu);
1021 set_except_vector(12, handle_ov);
1022 set_except_vector(13, handle_tr);
1023 set_except_vector(22, handle_mdmx);
1025 if (cpu_has_fpu && !cpu_has_nofpuex)
1026 set_except_vector(15, handle_fpe);
1029 set_except_vector(24, handle_mcheck);
1032 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x80);
1033 else if (cpu_has_4kex)
1034 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1036 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1038 if (current_cpu_data.cputype == CPU_R6000 ||
1039 current_cpu_data.cputype == CPU_R6000A) {
1041 * The R6000 is the only R-series CPU that features a machine
1042 * check exception (similar to the R4000 cache error) and
1043 * unaligned ldc1/sdc1 exception. The handlers have not been
1044 * written yet. Well, anyway there is no R6000 machine on the
1045 * current list of targets for Linux/MIPS.
1046 * (Duh, crap, there is someone with a tripple R6k machine)
1048 //set_except_vector(14, handle_mc);
1049 //set_except_vector(15, handle_ndc);
1053 #ifdef CONFIG_MIPS32_COMPAT
1057 flush_icache_range(CAC_BASE, CAC_BASE + 0x400);