2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 * Routines for generic manipulation of the interrupts found on the MIPS
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
24 #include <linux/config.h>
25 #include <linux/init.h>
26 #include <linux/irq.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/random.h>
33 #include <asm/i8259.h>
35 #include <asm/mips-boards/malta.h>
36 #include <asm/mips-boards/maltaint.h>
37 #include <asm/mips-boards/piix4.h>
38 #include <asm/gt64120.h>
39 #include <asm/mips-boards/generic.h>
40 #include <asm/mips-boards/msc01_pci.h>
42 extern asmlinkage void mipsIRQ(void);
44 static spinlock_t mips_irq_lock = SPIN_LOCK_UNLOCKED;
46 static inline int mips_pcibios_iack(void)
52 * Determine highest priority pending interrupt by performing
53 * a PCI Interrupt Acknowledge cycle.
55 switch(mips_revision_corid) {
56 case MIPS_REVISION_CORID_CORE_MSC:
57 case MIPS_REVISION_CORID_CORE_FPGA2:
58 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
59 MSC_READ(MSC01_PCI_IACK, irq);
62 case MIPS_REVISION_CORID_QED_RM5261:
63 case MIPS_REVISION_CORID_CORE_LV:
64 case MIPS_REVISION_CORID_CORE_FPGA:
65 case MIPS_REVISION_CORID_CORE_FPGAR2:
66 irq = GT_READ(GT_PCI0_IACK_OFS);
69 case MIPS_REVISION_CORID_BONITO64:
70 case MIPS_REVISION_CORID_CORE_20K:
71 case MIPS_REVISION_CORID_CORE_EMUL_BON:
72 /* The following will generate a PCI IACK cycle on the
73 * Bonito controller. It's a little bit kludgy, but it
74 * was the easiest way to implement it in hardware at
77 BONITO_PCIMAP_CFG = 0x20000;
79 /* Flush Bonito register block */
80 dummy = BONITO_PCIMAP_CFG;
83 irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
86 BONITO_PCIMAP_CFG = 0;
89 printk("Unknown Core card, don't know the system controller.\n");
95 static inline int get_int(int *irq)
99 spin_lock_irqsave(&mips_irq_lock, flags);
101 *irq = mips_pcibios_iack();
104 * IRQ7 is used to detect spurious interrupts.
105 * The interrupt acknowledge cycle returns IRQ7, if no
106 * interrupts is requested.
107 * We can differentiate between this situation and a
108 * "Normal" IRQ7 by reading the ISR.
112 outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
114 if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
115 spin_unlock_irqrestore(&mips_irq_lock, flags);
116 printk("We got a spurious interrupt from PIIX4.\n");
117 atomic_inc(&irq_err_count);
118 return -1; /* Spurious interrupt. */
122 spin_unlock_irqrestore(&mips_irq_lock, flags);
127 void malta_hw0_irqdispatch(struct pt_regs *regs)
132 return; /* interrupt has already been cleared */
137 void corehi_irqdispatch(struct pt_regs *regs)
139 unsigned int data,datahi;
141 /* Mask out corehi interrupt. */
142 clear_c0_status(IE_IRQ3);
144 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
145 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
146 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
147 switch(mips_revision_corid) {
148 case MIPS_REVISION_CORID_CORE_MSC:
149 case MIPS_REVISION_CORID_CORE_FPGA2:
150 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
152 case MIPS_REVISION_CORID_QED_RM5261:
153 case MIPS_REVISION_CORID_CORE_LV:
154 case MIPS_REVISION_CORID_CORE_FPGA:
155 case MIPS_REVISION_CORID_CORE_FPGAR2:
156 data = GT_READ(GT_INTRCAUSE_OFS);
157 printk("GT_INTRCAUSE = %08x\n", data);
158 data = GT_READ(0x70);
159 datahi = GT_READ(0x78);
160 printk("GT_CPU_ERR_ADDR = %02x%08x\n", datahi, data);
162 case MIPS_REVISION_CORID_BONITO64:
163 case MIPS_REVISION_CORID_CORE_20K:
164 case MIPS_REVISION_CORID_CORE_EMUL_BON:
165 data = BONITO_INTISR;
166 printk("BONITO_INTISR = %08x\n", data);
168 printk("BONITO_INTEN = %08x\n", data);
169 data = BONITO_INTPOL;
170 printk("BONITO_INTPOL = %08x\n", data);
171 data = BONITO_INTEDGE;
172 printk("BONITO_INTEDGE = %08x\n", data);
173 data = BONITO_INTSTEER;
174 printk("BONITO_INTSTEER = %08x\n", data);
175 data = BONITO_PCICMD;
176 printk("BONITO_PCICMD = %08x\n", data);
181 die("CoreHi interrupt", regs);
184 void __init arch_init_irq(void)
186 set_except_vector(0, mipsIRQ);