2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 * Routines for generic manipulation of the interrupts found on the MIPS
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
24 #include <linux/config.h>
25 #include <linux/init.h>
26 #include <linux/irq.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/random.h>
33 #include <asm/i8259.h>
35 #include <asm/mips-boards/malta.h>
36 #include <asm/mips-boards/maltaint.h>
37 #include <asm/mips-boards/piix4.h>
38 #include <asm/gt64120.h>
39 #include <asm/mips-boards/generic.h>
40 #include <asm/mips-boards/msc01_pci.h>
42 extern asmlinkage void mipsIRQ(void);
45 extern void breakpoint(void);
46 extern void set_debug_traps(void);
47 extern int remote_debug;
50 static spinlock_t mips_irq_lock = SPIN_LOCK_UNLOCKED;
52 static inline int mips_pcibios_iack(void)
58 * Determine highest priority pending interrupt by performing
59 * a PCI Interrupt Acknowledge cycle.
61 switch(mips_revision_corid) {
62 case MIPS_REVISION_CORID_CORE_MSC:
63 case MIPS_REVISION_CORID_CORE_FPGA2:
64 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
65 MSC_READ(MSC01_PCI_IACK, irq);
68 case MIPS_REVISION_CORID_QED_RM5261:
69 case MIPS_REVISION_CORID_CORE_LV:
70 case MIPS_REVISION_CORID_CORE_FPGA:
71 case MIPS_REVISION_CORID_CORE_FPGAR2:
72 irq = GT_READ(GT_PCI0_IACK_OFS);
75 case MIPS_REVISION_CORID_BONITO64:
76 case MIPS_REVISION_CORID_CORE_20K:
77 case MIPS_REVISION_CORID_CORE_EMUL_BON:
78 /* The following will generate a PCI IACK cycle on the
79 * Bonito controller. It's a little bit kludgy, but it
80 * was the easiest way to implement it in hardware at
83 BONITO_PCIMAP_CFG = 0x20000;
85 /* Flush Bonito register block */
86 dummy = BONITO_PCIMAP_CFG;
89 irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
92 BONITO_PCIMAP_CFG = 0;
95 printk("Unknown Core card, don't know the system controller.\n");
101 static inline int get_int(int *irq)
105 spin_lock_irqsave(&mips_irq_lock, flags);
107 *irq = mips_pcibios_iack();
110 * IRQ7 is used to detect spurious interrupts.
111 * The interrupt acknowledge cycle returns IRQ7, if no
112 * interrupts is requested.
113 * We can differentiate between this situation and a
114 * "Normal" IRQ7 by reading the ISR.
118 outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
120 if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
121 spin_unlock_irqrestore(&mips_irq_lock, flags);
122 printk("We got a spurious interrupt from PIIX4.\n");
123 atomic_inc(&irq_err_count);
124 return -1; /* Spurious interrupt. */
128 spin_unlock_irqrestore(&mips_irq_lock, flags);
133 void malta_hw0_irqdispatch(struct pt_regs *regs)
138 return; /* interrupt has already been cleared */
143 void corehi_irqdispatch(struct pt_regs *regs)
145 unsigned int data,datahi;
147 /* Mask out corehi interrupt. */
148 clear_c0_status(IE_IRQ3);
150 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
151 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
152 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
153 switch(mips_revision_corid) {
154 case MIPS_REVISION_CORID_CORE_MSC:
155 case MIPS_REVISION_CORID_CORE_FPGA2:
156 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
158 case MIPS_REVISION_CORID_QED_RM5261:
159 case MIPS_REVISION_CORID_CORE_LV:
160 case MIPS_REVISION_CORID_CORE_FPGA:
161 case MIPS_REVISION_CORID_CORE_FPGAR2:
162 data = GT_READ(GT_INTRCAUSE_OFS);
163 printk("GT_INTRCAUSE = %08x\n", data);
164 data = GT_READ(0x70);
165 datahi = GT_READ(0x78);
166 printk("GT_CPU_ERR_ADDR = %02x%08x\n", datahi, data);
168 case MIPS_REVISION_CORID_BONITO64:
169 case MIPS_REVISION_CORID_CORE_20K:
170 case MIPS_REVISION_CORID_CORE_EMUL_BON:
171 data = BONITO_INTISR;
172 printk("BONITO_INTISR = %08x\n", data);
174 printk("BONITO_INTEN = %08x\n", data);
175 data = BONITO_INTPOL;
176 printk("BONITO_INTPOL = %08x\n", data);
177 data = BONITO_INTEDGE;
178 printk("BONITO_INTEDGE = %08x\n", data);
179 data = BONITO_INTSTEER;
180 printk("BONITO_INTSTEER = %08x\n", data);
181 data = BONITO_PCICMD;
182 printk("BONITO_PCICMD = %08x\n", data);
187 die("CoreHi interrupt", regs);
190 void __init init_IRQ(void)
192 set_except_vector(0, mipsIRQ);