2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
8 #include <linux/config.h>
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
13 #include <linux/module.h>
14 #include <linux/proc_fs.h>
16 #include <asm/cacheops.h>
20 #include <asm/pgtable.h>
21 #include <asm/prefetch.h>
22 #include <asm/system.h>
23 #include <asm/bootinfo.h>
24 #include <asm/mipsregs.h>
25 #include <asm/mmu_context.h>
29 #define half_scache_line_size() (cpu_scache_line_size() >> 1)
34 * R4000 128 bytes S-cache: 0x58 bytes
35 * R4600 v1.7: 0x5c bytes
36 * R4600 v2.0: 0x60 bytes
37 * With prefetching, 16 byte strides 0xa0 bytes
40 static unsigned int clear_page_array[0x130 / 4];
42 void clear_page(void * page) __attribute__((alias("clear_page_array")));
44 EXPORT_SYMBOL(clear_page);
49 * R4000 128 bytes S-cache: 0x11c bytes
50 * R4600 v1.7: 0x080 bytes
51 * R4600 v2.0: 0x07c bytes
52 * With prefetching, 16 byte strides 0x0b8 bytes
54 static unsigned int copy_page_array[0x148 / 4];
56 void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
58 EXPORT_SYMBOL(copy_page);
61 * An address fits into a single register so it's safe to use 64-bit registers
62 * if we have 64-bit adresses.
64 #define cpu_has_64bit_registers cpu_has_64bit_addresses
67 * This is suboptimal for 32-bit kernels; we assume that R10000 is only used
68 * with 64-bit kernels. The prefetch offsets have been experimentally tuned
71 static int pref_offset_clear __initdata = 512;
72 static int pref_offset_copy __initdata = 256;
74 static unsigned int pref_src_mode __initdata;
75 static unsigned int pref_dst_mode __initdata;
77 static int load_offset __initdata;
78 static int store_offset __initdata;
80 static unsigned int __initdata *dest, *epc;
82 static unsigned int instruction_pending;
83 static union mips_instruction delayed_mi;
85 static void __init emit_instruction(union mips_instruction mi)
87 if (instruction_pending)
88 *epc++ = delayed_mi.word;
90 instruction_pending = 1;
94 static inline void flush_delay_slot_or_nop(void)
96 if (instruction_pending) {
97 *epc++ = delayed_mi.word;
98 instruction_pending = 0;
105 static inline unsigned int *label(void)
107 if (instruction_pending) {
108 *epc++ = delayed_mi.word;
109 instruction_pending = 0;
115 static inline void build_insn_word(unsigned int word)
117 union mips_instruction mi;
121 emit_instruction(mi);
124 static inline void build_nop(void)
126 build_insn_word(0); /* nop */
129 static inline void build_src_pref(int advance)
131 if (!(load_offset & (cpu_dcache_line_size() - 1))) {
132 union mips_instruction mi;
134 mi.i_format.opcode = pref_op;
135 mi.i_format.rs = 5; /* $a1 */
136 mi.i_format.rt = pref_src_mode;
137 mi.i_format.simmediate = load_offset + advance;
139 emit_instruction(mi);
143 static inline void __build_load_reg(int reg)
145 union mips_instruction mi;
148 if (cpu_has_64bit_registers) {
149 mi.i_format.opcode = ld_op;
152 mi.i_format.opcode = lw_op;
155 mi.i_format.rs = 5; /* $a1 */
156 mi.i_format.rt = reg; /* $reg */
157 mi.i_format.simmediate = load_offset;
159 load_offset += width;
160 emit_instruction(mi);
163 static inline void build_load_reg(int reg)
165 if (cpu_has_prefetch)
166 build_src_pref(pref_offset_copy);
168 __build_load_reg(reg);
171 static inline void build_dst_pref(int advance)
173 if (!(store_offset & (cpu_dcache_line_size() - 1))) {
174 union mips_instruction mi;
176 mi.i_format.opcode = pref_op;
177 mi.i_format.rs = 4; /* $a0 */
178 mi.i_format.rt = pref_dst_mode;
179 mi.i_format.simmediate = store_offset + advance;
181 emit_instruction(mi);
185 static inline void build_cdex_s(void)
187 union mips_instruction mi;
189 if ((store_offset & (cpu_scache_line_size() - 1)))
192 mi.c_format.opcode = cache_op;
193 mi.c_format.rs = 4; /* $a0 */
194 mi.c_format.c_op = 3; /* Create Dirty Exclusive */
195 mi.c_format.cache = 3; /* Secondary Data Cache */
196 mi.c_format.simmediate = store_offset;
198 emit_instruction(mi);
201 static inline void build_cdex_p(void)
203 union mips_instruction mi;
205 if (store_offset & (cpu_dcache_line_size() - 1))
208 if (R4600_V1_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2010)) {
215 if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
216 build_insn_word(0x8c200000); /* lw $zero, ($at) */
218 mi.c_format.opcode = cache_op;
219 mi.c_format.rs = 4; /* $a0 */
220 mi.c_format.c_op = 3; /* Create Dirty Exclusive */
221 mi.c_format.cache = 1; /* Data Cache */
222 mi.c_format.simmediate = store_offset;
224 emit_instruction(mi);
227 static void __init __build_store_reg(int reg)
229 union mips_instruction mi;
232 if (cpu_has_64bit_gp_regs ||
233 (cpu_has_64bit_zero_reg && reg == 0)) {
234 mi.i_format.opcode = sd_op;
237 mi.i_format.opcode = sw_op;
240 mi.i_format.rs = 4; /* $a0 */
241 mi.i_format.rt = reg; /* $reg */
242 mi.i_format.simmediate = store_offset;
244 store_offset += width;
245 emit_instruction(mi);
248 static inline void build_store_reg(int reg)
250 if (cpu_has_prefetch)
252 build_dst_pref(pref_offset_copy);
254 build_dst_pref(pref_offset_clear);
255 else if (cpu_has_cache_cdex_s)
257 else if (cpu_has_cache_cdex_p)
260 __build_store_reg(reg);
263 static inline void build_addiu_a2_a0(unsigned long offset)
265 union mips_instruction mi;
267 BUG_ON(offset > 0x7fff);
269 mi.i_format.opcode = cpu_has_64bit_addresses ? daddiu_op : addiu_op;
270 mi.i_format.rs = 4; /* $a0 */
271 mi.i_format.rt = 6; /* $a2 */
272 mi.i_format.simmediate = offset;
274 emit_instruction(mi);
277 static inline void build_addiu_a1(unsigned long offset)
279 union mips_instruction mi;
281 BUG_ON(offset > 0x7fff);
283 mi.i_format.opcode = cpu_has_64bit_addresses ? daddiu_op : addiu_op;
284 mi.i_format.rs = 5; /* $a1 */
285 mi.i_format.rt = 5; /* $a1 */
286 mi.i_format.simmediate = offset;
288 load_offset -= offset;
290 emit_instruction(mi);
293 static inline void build_addiu_a0(unsigned long offset)
295 union mips_instruction mi;
297 BUG_ON(offset > 0x7fff);
299 mi.i_format.opcode = cpu_has_64bit_addresses ? daddiu_op : addiu_op;
300 mi.i_format.rs = 4; /* $a0 */
301 mi.i_format.rt = 4; /* $a0 */
302 mi.i_format.simmediate = offset;
304 store_offset -= offset;
306 emit_instruction(mi);
309 static inline void build_bne(unsigned int *dest)
311 union mips_instruction mi;
313 mi.i_format.opcode = bne_op;
314 mi.i_format.rs = 6; /* $a2 */
315 mi.i_format.rt = 4; /* $a0 */
316 mi.i_format.simmediate = dest - epc - 1;
319 flush_delay_slot_or_nop();
322 static inline void build_jr_ra(void)
324 union mips_instruction mi;
326 mi.r_format.opcode = spec_op;
331 mi.r_format.func = jr_op;
334 flush_delay_slot_or_nop();
337 void __init build_clear_page(void)
339 unsigned int loop_start;
341 epc = (unsigned int *) &clear_page_array;
342 instruction_pending = 0;
345 if (cpu_has_prefetch) {
346 switch (current_cpu_data.cputype) {
349 * As a workaround for erratum G105 which make the
350 * PrepareForStore hint unusable we fall back to
351 * StoreRetained on the RM9000. Once it is known which
352 * versions of the RM9000 we'll be able to condition-
358 pref_src_mode = Pref_LoadStreamed;
359 pref_dst_mode = Pref_StoreStreamed;
363 pref_src_mode = Pref_LoadStreamed;
364 pref_dst_mode = Pref_PrepareForStore;
369 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0));
371 if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
372 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
380 } while (store_offset < half_scache_line_size());
381 build_addiu_a0(2 * store_offset);
382 loop_start = store_offset;
388 } while ((store_offset - loop_start) < half_scache_line_size());
391 if (cpu_has_prefetch && pref_offset_clear) {
392 build_addiu_a2_a0(pref_offset_clear);
394 loop_start = store_offset;
396 __build_store_reg(0);
397 __build_store_reg(0);
398 __build_store_reg(0);
399 __build_store_reg(0);
400 } while ((store_offset - loop_start) < half_scache_line_size());
401 build_addiu_a0(2 * store_offset);
402 loop_start = store_offset;
404 __build_store_reg(0);
405 __build_store_reg(0);
406 __build_store_reg(0);
407 __build_store_reg(0);
408 } while ((store_offset - loop_start) < half_scache_line_size());
414 flush_icache_range((unsigned long)&clear_page_array,
415 (unsigned long) epc);
417 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
420 void __init build_copy_page(void)
422 unsigned int loop_start;
424 epc = (unsigned int *) ©_page_array;
425 store_offset = load_offset = 0;
426 instruction_pending = 0;
428 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0));
430 if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
431 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
434 loop_start = store_offset;
444 } while ((store_offset - loop_start) < half_scache_line_size());
445 build_addiu_a0(2 * store_offset);
446 build_addiu_a1(2 * load_offset);
447 loop_start = store_offset;
457 } while ((store_offset - loop_start) < half_scache_line_size());
460 if (cpu_has_prefetch && pref_offset_copy) {
461 build_addiu_a2_a0(pref_offset_copy);
463 loop_start = store_offset;
465 __build_load_reg( 8);
466 __build_load_reg( 9);
467 __build_load_reg(10);
468 __build_load_reg(11);
469 __build_store_reg( 8);
470 __build_store_reg( 9);
471 __build_store_reg(10);
472 __build_store_reg(11);
473 } while ((store_offset - loop_start) < half_scache_line_size());
474 build_addiu_a0(2 * store_offset);
475 build_addiu_a1(2 * load_offset);
476 loop_start = store_offset;
478 __build_load_reg( 8);
479 __build_load_reg( 9);
480 __build_load_reg(10);
481 __build_load_reg(11);
482 __build_store_reg( 8);
483 __build_store_reg( 9);
484 __build_store_reg(10);
485 __build_store_reg(11);
486 } while ((store_offset - loop_start) < half_scache_line_size());
492 flush_icache_range((unsigned long)©_page_array,
493 (unsigned long) epc);
495 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));