2 * TLB exception handling code for R2000/R3000.
4 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse
6 * Multi-CPU abstraction reworking:
7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
9 * Further modifications to make this work:
10 * Copyright (c) 1998 Harald Koerfgen
11 * Copyright (c) 1998, 1999 Gleb Raiko & Vladimir Roganov
12 * Copyright (c) 2001 Ralf Baechle
13 * Copyright (c) 2001 MIPS Technologies, Inc.
15 #include <linux/init.h>
17 #include <asm/cachectl.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
21 #include <asm/pgtable-bits.h>
22 #include <asm/regdef.h>
23 #include <asm/stackframe.h>
25 #define TLB_OPTIMIZE /* If you are paranoid, disable this. */
33 /* TLB refill, R[23]00 version */
34 LEAF(except_vec0_r2300)
38 lw k1, pgd_current # get pgd pointer
53 END(except_vec0_r2300)
57 /* ABUSE of CPP macros 101. */
59 /* After this macro runs, the pte faulted on is
60 * in register PTE, a ptr into the table in which
61 * the pte belongs is in PTR.
63 #define LOAD_PTE(pte, ptr) \
64 mfc0 pte, CP0_BADVADDR; \
65 lw ptr, pgd_current; \
69 mfc0 pte, CP0_CONTEXT; \
71 andi pte, pte, 0xffc; \
76 /* This places the even/odd pte pair in the page
77 * table at PTR into ENTRYLO0 and ENTRYLO1 using
78 * TMP as a scratch register.
80 #define PTE_RELOAD(ptr) \
83 mtc0 ptr, CP0_ENTRYLO0; \
86 #define DO_FAULT(write) \
90 mfc0 a2, CP0_BADVADDR; \
96 j ret_from_exception; \
101 /* Check is PTE is present, if not then jump to LABEL.
102 * PTR points to the page table where this PTE is located,
103 * when the macro is done executing PTE will be restored
104 * with it's original value.
106 #define PTE_PRESENT(pte, ptr, label) \
107 andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
108 xori pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
115 /* Make PTE valid, store result in PTR. */
116 #define PTE_MAKEVALID(pte, ptr) \
117 ori pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \
120 /* Check if PTE can be written to, if not branch to LABEL.
121 * Regardless restore PTE with value from PTR when done.
123 #define PTE_WRITABLE(pte, ptr, label) \
124 andi pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
125 xori pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
133 /* Make PTE writable, update software status bits as well,
136 #define PTE_MAKEWRITE(pte, ptr) \
137 ori pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \
138 _PAGE_VALID | _PAGE_DIRTY); \
142 * The index register may have the probe fail bit set,
143 * because we would trap on access kseg2, i.e. without refill.
145 #define TLB_WRITE(reg) \
146 mfc0 reg, CP0_INDEX; \
165 NESTED(handle_tlbl, PT_SIZE, sp)
169 /* Test present bit in entry. */
172 PTE_PRESENT(k0, k1, nopage_tlbl)
173 PTE_MAKEVALID(k0, k1)
183 NESTED(handle_tlbs, PT_SIZE, sp)
188 tlbp # find faulting entry
189 PTE_WRITABLE(k0, k1, nopage_tlbs)
190 PTE_MAKEWRITE(k0, k1)
201 NESTED(handle_mod, PT_SIZE, sp)
205 tlbp # find faulting entry
206 andi k0, k0, _PAGE_WRITE
213 /* Present and writable bits set, set accessed and dirty bits. */
214 PTE_MAKEWRITE(k0, k1)
216 /* Now reload the entry into the tlb. */