2 * TLB exception handling code for MIPS32 CPUs.
4 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse
6 * Multi-cpu abstraction and reworking:
7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
9 * Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
12 * Pete Popov, ppopov@pacbell.net
13 * Added 36 bit phys address support.
14 * Copyright (C) 2002 MontaVista Software, Inc.
16 #include <linux/init.h>
18 #include <asm/cachectl.h>
19 #include <asm/fpregdef.h>
20 #include <asm/mipsregs.h>
22 #include <asm/pgtable-bits.h>
23 #include <asm/regdef.h>
24 #include <asm/stackframe.h>
26 #define TLB_OPTIMIZE /* If you are paranoid, disable this. */
28 #ifdef CONFIG_64BIT_PHYS_ADDR
30 /* We really only support 36 bit physical addresses on MIPS32 */
35 #define PTE_HALF 4 /* pte_high contains pre-shifted, ready to go entry */
37 #define PTEP_INDX_MSK 0xff0
38 #define PTE_INDX_MSK 0xff8
39 #define PTE_INDX_SHIFT 9
40 #define CONVERT_PTE(pte)
41 #define PTE_MAKEWRITE_HIGH(pte, ptr) \
42 lw pte, PTE_HALF(ptr); \
43 ori pte, (_PAGE_VALID | _PAGE_DIRTY); \
44 sw pte, PTE_HALF(ptr); \
47 #define PTE_MAKEVALID_HIGH(pte, ptr) \
48 lw pte, PTE_HALF(ptr); \
49 ori pte, pte, _PAGE_VALID; \
50 sw pte, PTE_HALF(ptr); \
61 #define PTEP_INDX_MSK 0xff8
62 #define PTE_INDX_MSK 0xffc
63 #define PTE_INDX_SHIFT 10
64 #define CONVERT_PTE(pte) srl pte, pte, 6
65 #define PTE_MAKEWRITE_HIGH(pte, ptr)
66 #define PTE_MAKEVALID_HIGH(pte, ptr)
68 #endif /* CONFIG_64BIT_PHYS_ADDR */
70 #ifdef CONFIG_64BIT_PHYS_ADDR
71 #define GET_PTE_OFF(reg)
73 #define GET_PTE_OFF(reg) srl reg, reg, 1
77 * ABUSE of CPP macros 101.
79 * After this macro runs, the pte faulted on is
80 * in register PTE, a ptr into the table in which
81 * the pte belongs is in PTR.
85 #define GET_PGD(scratch, ptr) \
86 mfc0 ptr, CP0_CONTEXT; \
87 la scratch, pgd_current;\
90 addu ptr, scratch, ptr; \
93 #define GET_PGD(scratch, ptr) \
97 #define LOAD_PTE(pte, ptr) \
99 mfc0 pte, CP0_BADVADDR; \
100 srl pte, pte, _PGDIR_SHIFT; \
102 addu ptr, ptr, pte; \
103 mfc0 pte, CP0_BADVADDR; \
105 srl pte, pte, PTE_INDX_SHIFT; \
106 and pte, pte, PTE_INDX_MSK; \
107 addu ptr, ptr, pte; \
110 /* This places the even/odd pte pair in the page
111 * table at PTR into ENTRYLO0 and ENTRYLO1 using
112 * TMP as a scratch register.
114 #define PTE_RELOAD(ptr, tmp) \
115 ori ptr, ptr, PTE_SIZE; \
116 xori ptr, ptr, PTE_SIZE; \
117 PTE_L tmp, (PTE_HALF+PTE_SIZE)(ptr); \
119 P_MTC0 tmp, CP0_ENTRYLO1; \
120 PTE_L ptr, PTE_HALF(ptr); \
122 P_MTC0 ptr, CP0_ENTRYLO0;
124 #define DO_FAULT(write) \
127 mfc0 a2, CP0_BADVADDR; \
133 j ret_from_exception; \
137 /* Check is PTE is present, if not then jump to LABEL.
138 * PTR points to the page table where this PTE is located,
139 * when the macro is done executing PTE will be restored
140 * with it's original value.
142 #define PTE_PRESENT(pte, ptr, label) \
143 andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
144 xori pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
148 /* Make PTE valid, store result in PTR. */
149 #define PTE_MAKEVALID(pte, ptr) \
150 ori pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \
153 /* Check if PTE can be written to, if not branch to LABEL.
154 * Regardless restore PTE with value from PTR when done.
156 #define PTE_WRITABLE(pte, ptr, label) \
157 andi pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
158 xori pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
162 /* Make PTE writable, update software status bits as well,
165 #define PTE_MAKEWRITE(pte, ptr) \
166 ori pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \
167 _PAGE_VALID | _PAGE_DIRTY); \
173 NESTED(handle_tlbl, PT_SIZE, sp)
177 /* Test present bit in entry. */
180 PTE_PRESENT(k0, k1, nopage_tlbl)
181 PTE_MAKEVALID_HIGH(k0, k1)
182 PTE_MAKEVALID(k0, k1)
199 NESTED(handle_tlbs, PT_SIZE, sp)
205 tlbp # find faulting entry
206 PTE_WRITABLE(k0, k1, nopage_tlbs)
207 PTE_MAKEWRITE(k0, k1)
208 PTE_MAKEWRITE_HIGH(k0, k1)
225 NESTED(handle_mod, PT_SIZE, sp)
230 tlbp # find faulting entry
231 andi k0, k0, _PAGE_WRITE
235 /* Present and writable bits set, set accessed and dirty bits. */
236 PTE_MAKEWRITE(k0, k1)
237 PTE_MAKEWRITE_HIGH(k0, k1)
238 /* Now reload the entry into the tlb. */