2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Jaguar-ATX board dependent boot routines
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
10 * Author: Matthew Dharm, Momentum Computer
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
42 #include <linux/config.h>
43 #include <linux/bcd.h>
44 #include <linux/init.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
48 #include <linux/bootmem.h>
49 #include <linux/module.h>
50 #include <linux/pci.h>
51 #include <linux/swap.h>
52 #include <linux/ioport.h>
53 #include <linux/sched.h>
54 #include <linux/interrupt.h>
55 #include <linux/timex.h>
56 #include <linux/vmalloc.h>
58 #include <asm/bootinfo.h>
62 #include <asm/pci_channel.h>
63 #include <asm/processor.h>
64 #include <asm/ptrace.h>
65 #include <asm/reboot.h>
66 #include <asm/tlbflush.h>
67 #include <asm/mv64340.h>
69 #include "jaguar_atx_fpga.h"
71 extern unsigned long mv64340_sram_base;
72 unsigned long cpu_clock;
74 /* These functions are used for rebooting or halting the machine*/
75 extern void momenco_jaguar_restart(char *command);
76 extern void momenco_jaguar_halt(void);
77 extern void momenco_jaguar_power_off(void);
79 void momenco_time_init(void);
81 static char reset_reason;
83 static inline unsigned long ENTRYLO(unsigned long paddr)
85 return ((paddr & PAGE_MASK) |
86 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
87 _CACHE_UNCACHED)) >> 6;
90 void __init bus_error_init(void) { /* nothing */ }
93 * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
94 * to be hit on every IRQ anyway - there's absolutely no point in letting it be
95 * a random TLB entry, as it'll just cause needless churning of the TLB. And we
96 * use the other half for the serial port, which is just a PITA otherwise :)
98 * Device Physical Virtual
99 * MV64340 Internal Regs 0xf4000000 0xf4000000
100 * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
101 * NVRAM (CS1) 0xfc800000 0xfc800000
102 * UARTs (CS2) 0xfd000000 0xfd000000
103 * Internal SRAM 0xfe000000 0xfe000000
104 * M-Systems DOC (CS3) 0xff000000 0xff000000
107 static __init void wire_stupidity_into_tlb(void)
111 local_flush_tlb_all();
113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
115 0xf4000000UL, PM_64K);
116 /* fpga, rtc, and uart */
117 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
118 0xfc000000UL, PM_16M);
119 // /* m-sys and internal SRAM */
120 // add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
121 // 0xfe000000UL, PM_16M);
123 marvell_base = 0xf4000000;
124 //mv64340_sram_base = 0xfe000000; /* Currently unused */
128 unsigned long marvell_base = 0xf4000000L;
129 unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
130 unsigned long uart_base = 0xfd000000L;
131 static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
133 EXPORT_SYMBOL(marvell_base);
135 static __init int per_cpu_mappings(void)
137 marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
138 ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
139 uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
140 rtc_base = ioremap(0xfc000000UL, 0x8000);
141 // ioremap(0xfe000000, 32 << 20);
143 local_flush_tlb_all();
148 arch_initcall(per_cpu_mappings);
150 unsigned long m48t37y_get_time(void)
152 unsigned int year, month, day, hour, min, sec;
154 /* stop the update */
155 rtc_base[0x7ff8] = 0x40;
157 year = BCD2BIN(rtc_base[0x7fff]);
158 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
160 month = BCD2BIN(rtc_base[0x7ffe]);
162 day = BCD2BIN(rtc_base[0x7ffd]);
164 hour = BCD2BIN(rtc_base[0x7ffb]);
165 min = BCD2BIN(rtc_base[0x7ffa]);
166 sec = BCD2BIN(rtc_base[0x7ff9]);
168 /* start the update */
169 rtc_base[0x7ff8] = 0x00;
171 return mktime(year, month, day, hour, min, sec);
174 int m48t37y_set_time(unsigned long sec)
178 /* convert to a more useful format -- note months count from 0 */
183 rtc_base[0x7ff8] = 0x80;
186 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
187 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
190 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
193 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
196 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
197 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
198 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
200 /* day of week -- not really used, but let's keep it up-to-date */
201 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
203 /* disable writing */
204 rtc_base[0x7ff8] = 0x00;
209 void momenco_timer_setup(struct irqaction *irq)
215 * Ugly but the least of all evils. TLB initialization did flush the TLB so
216 * We need to setup mappings again before we can touch the RTC.
218 void momenco_time_init(void)
220 wire_stupidity_into_tlb();
222 mips_hpt_frequency = cpu_clock / 2;
223 board_timer_setup = momenco_timer_setup;
225 rtc_get_time = m48t37y_get_time;
226 rtc_set_time = m48t37y_set_time;
229 static struct resource mv_pci_io_mem0_resource = {
230 .name = "MV64340 PCI0 IO MEM",
231 .flags = IORESOURCE_IO
234 static struct resource mv_pci_mem0_resource = {
235 .name = "MV64340 PCI0 MEM",
236 .flags = IORESOURCE_MEM
239 static struct mv_pci_controller mv_bus0_controller = {
241 .pci_ops = &mv_pci_ops,
242 .mem_resource = &mv_pci_mem0_resource,
243 .io_resource = &mv_pci_io_mem0_resource,
245 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
246 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
249 static uint32_t mv_io_base, mv_io_size;
251 static void ja_pci0_init(void)
253 uint32_t mem0_base, mem0_size;
254 uint32_t io_base, io_size;
256 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
257 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
258 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
259 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
261 mv_pci_io_mem0_resource.start = 0;
262 mv_pci_io_mem0_resource.end = io_size - 1;
263 mv_pci_mem0_resource.start = mem0_base;
264 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
265 mv_bus0_controller.pcic.mem_offset = mem0_base;
266 mv_bus0_controller.pcic.io_offset = 0;
268 ioport_resource.end = io_size - 1;
270 register_pci_controller(&mv_bus0_controller.pcic);
272 mv_io_base = io_base;
273 mv_io_size = io_size;
276 static struct resource mv_pci_io_mem1_resource = {
277 .name = "MV64340 PCI1 IO MEM",
278 .flags = IORESOURCE_IO
281 static struct resource mv_pci_mem1_resource = {
282 .name = "MV64340 PCI1 MEM",
283 .flags = IORESOURCE_MEM
286 static struct mv_pci_controller mv_bus1_controller = {
288 .pci_ops = &mv_pci_ops,
289 .mem_resource = &mv_pci_mem1_resource,
290 .io_resource = &mv_pci_io_mem1_resource,
292 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
293 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
296 static __init void ja_pci1_init(void)
298 uint32_t mem0_base, mem0_size;
299 uint32_t io_base, io_size;
301 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
302 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
303 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
304 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
307 * Here we assume the I/O window of second bus to be contiguous with
308 * the first. A gap is no problem but would waste address space for
309 * remapping the port space.
311 mv_pci_io_mem1_resource.start = mv_io_size;
312 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
313 mv_pci_mem1_resource.start = mem0_base;
314 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
315 mv_bus1_controller.pcic.mem_offset = mem0_base;
316 mv_bus1_controller.pcic.io_offset = 0;
318 ioport_resource.end = io_base + io_size -mv_io_base - 1;
320 register_pci_controller(&mv_bus1_controller.pcic);
322 mv_io_size = io_base + io_size - mv_io_base;
325 static __init int __init ja_pci_init(void)
327 unsigned long io_v_base;
330 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
333 * We require at least one enabled I/O or PCI memory window or we
334 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
336 if (enable & (0x01 << 9) || enable & (0x01 << 10))
339 if (enable & (0x01 << 14) || enable & (0x01 << 15))
343 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
345 panic("Could not ioremap I/O port range");
347 set_io_port_base(io_v_base);
353 arch_initcall(ja_pci_init);
355 static int __init momenco_jaguar_atx_setup(void)
357 unsigned int tmpword;
359 board_time_init = momenco_time_init;
361 _machine_restart = momenco_jaguar_restart;
362 _machine_halt = momenco_jaguar_halt;
363 _machine_power_off = momenco_jaguar_power_off;
366 * initrd_start = (ulong)jaguar_initrd_start;
367 * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
368 * initrd_below_start_ok = 1;
371 wire_stupidity_into_tlb();
374 * shut down ethernet ports, just to be sure our memory doesn't get
375 * corrupted by random ethernet traffic.
377 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
378 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
379 MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
380 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
381 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
382 MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
383 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
384 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
385 while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
386 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
387 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
388 while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
389 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
390 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
391 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
392 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
393 MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2),
394 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
396 /* Turn off the Bit-Error LED */
397 JAGUAR_FPGA_WRITE(0x80, CLR);
399 tmpword = JAGUAR_FPGA_READ(BOARDREV);
401 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
404 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
407 tmpword = JAGUAR_FPGA_READ(FPGA_REV);
408 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
409 tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
410 printk("Reset reason: 0x%x\n", tmpword);
413 printk(" - Power-up reset\n");
416 printk(" - Push-button reset\n");
419 printk(" - Watchdog reset\n");
422 printk(" - JTAG reset\n");
425 printk(" - Unknown reset cause\n");
427 reset_reason = tmpword;
428 JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
430 tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
431 printk("Board Status register: 0x%02x\n", tmpword);
432 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
433 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
435 /* 256MiB of RM9000x2 DDR */
436 // add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
438 /* 128MiB of MV-64340 DDR */
439 // add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
441 /* XXX Memory configuration should be picked up from PMON2k */
442 #ifdef CONFIG_JAGUAR_DMALOW
443 printk("Jaguar ATX DMA-low mode set\n");
444 add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
445 add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
447 /* 128MiB of MV-64340 DDR RAM */
448 printk("Jaguar ATX DMA-low mode is not set\n");
449 add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
452 #ifdef GEMDEBUG_TRACEBUFFER
454 unsigned int tbControl;
456 0 << 26 | /* post trigger delay 0 */
457 0x2 << 16 | /* sequential trace mode */
458 // 0x0 << 16 | /* non-sequential trace mode */
459 // 0xf << 4 | /* watchpoints disabled */
461 2 ; /* interrupt disabled */
462 printk ("setting tbControl = %08lx\n", tbControl);
463 write_32bit_cp0_set1_register($22, tbControl);
464 __asm__ __volatile__(".set noreorder\n\t" \
465 "nop; nop; nop; nop; nop; nop;\n\t" \
466 "nop; nop; nop; nop; nop; nop;\n\t" \
475 early_initcall(momenco_jaguar_atx_setup);