1 /* gt64240r.h - GT-64240 Internal registers definition file */
3 /* Copyright - Galileo technology. */
8 #define GTREG(v) (((v) & 0xff) << 24) | (((v) & 0xff00) << 8) | \
9 (((v) >> 24) & 0xff) | (((v) >> 8) & 0xff00)
12 #define GTREG_SHORT(X) (((X) << 8) | ((X) >> 8))
14 #define LONG_GTREG(X) ((l64) \
15 (((X)&0x00000000000000ffULL) << 56) | \
16 (((X)&0x000000000000ff00ULL) << 40) | \
17 (((X)&0x0000000000ff0000ULL) << 24) | \
18 (((X)&0x00000000ff000000ULL) << 8) | \
19 (((X)&0x000000ff00000000ULL) >> 8) | \
20 (((X)&0x0000ff0000000000ULL) >> 24) | \
21 (((X)&0x00ff000000000000ULL) >> 40) | \
22 (((X)&0xff00000000000000ULL) >> 56))
25 #include "gt64240_dep.h"
27 /****************************************/
28 /* CPU Control Registers */
29 /****************************************/
31 #define CPU_CONFIGURATION 0x000
32 #define CPU_MODE 0x120
33 #define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170
34 #define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178
36 /****************************************/
37 /* Processor Address Space */
38 /****************************************/
41 #define SCS_0_LOW_DECODE_ADDRESS 0x008
42 #define SCS_0_HIGH_DECODE_ADDRESS 0x010
43 #define SCS_1_LOW_DECODE_ADDRESS 0x208
44 #define SCS_1_HIGH_DECODE_ADDRESS 0x210
45 #define SCS_2_LOW_DECODE_ADDRESS 0x018
46 #define SCS_2_HIGH_DECODE_ADDRESS 0x020
47 #define SCS_3_LOW_DECODE_ADDRESS 0x218
48 #define SCS_3_HIGH_DECODE_ADDRESS 0x220
50 #define CS_0_LOW_DECODE_ADDRESS 0x028
51 #define CS_0_HIGH_DECODE_ADDRESS 0x030
52 #define CS_1_LOW_DECODE_ADDRESS 0x228
53 #define CS_1_HIGH_DECODE_ADDRESS 0x230
54 #define CS_2_LOW_DECODE_ADDRESS 0x248
55 #define CS_2_HIGH_DECODE_ADDRESS 0x250
56 #define CS_3_LOW_DECODE_ADDRESS 0x038
57 #define CS_3_HIGH_DECODE_ADDRESS 0x040
58 #define BOOTCS_LOW_DECODE_ADDRESS 0x238
59 #define BOOTCS_HIGH_DECODE_ADDRESS 0x240
61 #define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
62 #define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
63 #define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
64 #define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
65 #define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
66 #define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
67 #define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
68 #define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
69 #define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
70 #define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
72 #define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
73 #define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
74 #define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
75 #define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
76 #define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
77 #define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
78 #define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
79 #define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
80 #define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
81 #define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
83 #define INTERNAL_SPACE_DECODE 0x068
85 #define CPU_0_LOW_DECODE_ADDRESS 0x290
86 #define CPU_0_HIGH_DECODE_ADDRESS 0x298
87 #define CPU_1_LOW_DECODE_ADDRESS 0x2c0
88 #define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
90 #define PCI_0I_O_ADDRESS_REMAP 0x0f0
91 #define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
92 #define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
93 #define PCI_0MEMORY1_ADDRESS_REMAP 0x100
94 #define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
95 #define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
96 #define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
97 #define PCI_0MEMORY3_ADDRESS_REMAP 0x300
98 #define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
100 #define PCI_1I_O_ADDRESS_REMAP 0x108
101 #define PCI_1MEMORY0_ADDRESS_REMAP 0x110
102 #define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
103 #define PCI_1MEMORY1_ADDRESS_REMAP 0x118
104 #define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
105 #define PCI_1MEMORY2_ADDRESS_REMAP 0x310
106 #define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
107 #define PCI_1MEMORY3_ADDRESS_REMAP 0x318
108 #define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
110 /****************************************/
111 /* CPU Sync Barrier */
112 /****************************************/
114 #define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
115 #define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
118 /****************************************/
119 /* CPU Access Protect */
120 /****************************************/
122 #define CPU_LOW_PROTECT_ADDRESS_0 0X180
123 #define CPU_HIGH_PROTECT_ADDRESS_0 0X188
124 #define CPU_LOW_PROTECT_ADDRESS_1 0X190
125 #define CPU_HIGH_PROTECT_ADDRESS_1 0X198
126 #define CPU_LOW_PROTECT_ADDRESS_2 0X1a0
127 #define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8
128 #define CPU_LOW_PROTECT_ADDRESS_3 0X1b0
129 #define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8
130 #define CPU_LOW_PROTECT_ADDRESS_4 0X1c0
131 #define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8
132 #define CPU_LOW_PROTECT_ADDRESS_5 0X1d0
133 #define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8
134 #define CPU_LOW_PROTECT_ADDRESS_6 0X1e0
135 #define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8
136 #define CPU_LOW_PROTECT_ADDRESS_7 0X1f0
137 #define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8
140 /****************************************/
142 /****************************************/
144 #define SNOOP_BASE_ADDRESS_0 0x380
145 #define SNOOP_TOP_ADDRESS_0 0x388
146 #define SNOOP_BASE_ADDRESS_1 0x390
147 #define SNOOP_TOP_ADDRESS_1 0x398
148 #define SNOOP_BASE_ADDRESS_2 0x3a0
149 #define SNOOP_TOP_ADDRESS_2 0x3a8
150 #define SNOOP_BASE_ADDRESS_3 0x3b0
151 #define SNOOP_TOP_ADDRESS_3 0x3b8
153 /****************************************/
154 /* CPU Error Report */
155 /****************************************/
157 #define CPU_ERROR_ADDRESS_LOW 0x070
158 #define CPU_ERROR_ADDRESS_HIGH 0x078
159 #define CPU_ERROR_DATA_LOW 0x128
160 #define CPU_ERROR_DATA_HIGH 0x130
161 #define CPU_ERROR_PARITY 0x138
162 #define CPU_ERROR_CAUSE 0x140
163 #define CPU_ERROR_MASK 0x148
165 /****************************************/
167 /****************************************/
169 #define X_0_ADDRESS 0x360
170 #define X_0_COMMAND_ID 0x368
171 #define X_1_ADDRESS 0x370
172 #define X_1_COMMAND_ID 0x378
173 #define WRITE_DATA_LOW 0x3c0
174 #define WRITE_DATA_HIGH 0x3c8
175 #define WRITE_BYTE_ENABLE 0X3e0
176 #define READ_DATA_LOW 0x3d0
177 #define READ_DATA_HIGH 0x3d8
178 #define READ_ID 0x3e8
181 /****************************************/
182 /* SDRAM and Device Address Space */
183 /****************************************/
186 /****************************************/
187 /* SDRAM Configuration */
188 /****************************************/
190 #define SDRAM_CONFIGURATION 0x448
191 #define SDRAM_OPERATION_MODE 0x474
192 #define SDRAM_ADDRESS_DECODE 0x47C
193 #define SDRAM_TIMING_PARAMETERS 0x4b4
194 #define SDRAM_UMA_CONTROL 0x4a4
195 #define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
196 #define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
197 #define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
200 /****************************************/
201 /* SDRAM Parameters */
202 /****************************************/
204 #define SDRAM_BANK0PARAMETERS 0x44C
205 #define SDRAM_BANK1PARAMETERS 0x450
206 #define SDRAM_BANK2PARAMETERS 0x454
207 #define SDRAM_BANK3PARAMETERS 0x458
210 /****************************************/
211 /* SDRAM Error Report */
212 /****************************************/
214 #define SDRAM_ERROR_DATA_LOW 0x484
215 #define SDRAM_ERROR_DATA_HIGH 0x480
216 #define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
217 #define SDRAM_RECEIVED_ECC 0x488
218 #define SDRAM_CALCULATED_ECC 0x48c
219 #define SDRAM_ECC_CONTROL 0x494
220 #define SDRAM_ECC_ERROR_COUNTER 0x498
223 /****************************************/
224 /* SDunit Debug (for internal use) */
225 /****************************************/
227 #define X0_ADDRESS 0x500
228 #define X0_COMMAND_AND_ID 0x504
229 #define X0_WRITE_DATA_LOW 0x508
230 #define X0_WRITE_DATA_HIGH 0x50c
231 #define X0_WRITE_BYTE_ENABLE 0x518
232 #define X0_READ_DATA_LOW 0x510
233 #define X0_READ_DATA_HIGH 0x514
234 #define X0_READ_ID 0x51c
235 #define X1_ADDRESS 0x520
236 #define X1_COMMAND_AND_ID 0x524
237 #define X1_WRITE_DATA_LOW 0x528
238 #define X1_WRITE_DATA_HIGH 0x52c
239 #define X1_WRITE_BYTE_ENABLE 0x538
240 #define X1_READ_DATA_LOW 0x530
241 #define X1_READ_DATA_HIGH 0x534
242 #define X1_READ_ID 0x53c
243 #define X0_SNOOP_ADDRESS 0x540
244 #define X0_SNOOP_COMMAND 0x544
245 #define X1_SNOOP_ADDRESS 0x548
246 #define X1_SNOOP_COMMAND 0x54c
249 /****************************************/
250 /* Device Parameters */
251 /****************************************/
253 #define DEVICE_BANK0PARAMETERS 0x45c
254 #define DEVICE_BANK1PARAMETERS 0x460
255 #define DEVICE_BANK2PARAMETERS 0x464
256 #define DEVICE_BANK3PARAMETERS 0x468
257 #define DEVICE_BOOT_BANK_PARAMETERS 0x46c
258 #define DEVICE_CONTROL 0x4c0
259 #define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
260 #define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
261 #define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
264 /****************************************/
265 /* Device Interrupt */
266 /****************************************/
268 #define DEVICE_INTERRUPT_CAUSE 0x4d0
269 #define DEVICE_INTERRUPT_MASK 0x4d4
270 #define DEVICE_ERROR_ADDRESS 0x4d8
272 /****************************************/
274 /****************************************/
276 #define CHANNEL0_DMA_BYTE_COUNT 0x800
277 #define CHANNEL1_DMA_BYTE_COUNT 0x804
278 #define CHANNEL2_DMA_BYTE_COUNT 0x808
279 #define CHANNEL3_DMA_BYTE_COUNT 0x80C
280 #define CHANNEL4_DMA_BYTE_COUNT 0x900
281 #define CHANNEL5_DMA_BYTE_COUNT 0x904
282 #define CHANNEL6_DMA_BYTE_COUNT 0x908
283 #define CHANNEL7_DMA_BYTE_COUNT 0x90C
284 #define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
285 #define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
286 #define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
287 #define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
288 #define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
289 #define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
290 #define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
291 #define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
292 #define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
293 #define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
294 #define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
295 #define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
296 #define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
297 #define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
298 #define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
299 #define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
300 #define CHANNEL0NEXT_RECORD_POINTER 0x830
301 #define CHANNEL1NEXT_RECORD_POINTER 0x834
302 #define CHANNEL2NEXT_RECORD_POINTER 0x838
303 #define CHANNEL3NEXT_RECORD_POINTER 0x83C
304 #define CHANNEL4NEXT_RECORD_POINTER 0x930
305 #define CHANNEL5NEXT_RECORD_POINTER 0x934
306 #define CHANNEL6NEXT_RECORD_POINTER 0x938
307 #define CHANNEL7NEXT_RECORD_POINTER 0x93C
308 #define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
309 #define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
310 #define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
311 #define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
312 #define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
313 #define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
314 #define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
315 #define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
316 #define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
317 #define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
318 #define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
319 #define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
320 #define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
321 #define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
322 #define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
323 #define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
324 #define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
325 #define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
326 #define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
327 #define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
328 #define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
329 #define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
330 #define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
331 #define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
332 #define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
333 #define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
334 #define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
335 #define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
336 #define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
337 #define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
338 #define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
339 #define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
341 /****************************************/
342 /* DMA Channel Control */
343 /****************************************/
345 #define CHANNEL0CONTROL 0x840
346 #define CHANNEL0CONTROL_HIGH 0x880
348 #define CHANNEL1CONTROL 0x844
349 #define CHANNEL1CONTROL_HIGH 0x884
351 #define CHANNEL2CONTROL 0x848
352 #define CHANNEL2CONTROL_HIGH 0x888
354 #define CHANNEL3CONTROL 0x84C
355 #define CHANNEL3CONTROL_HIGH 0x88C
357 #define CHANNEL4CONTROL 0x940
358 #define CHANNEL4CONTROL_HIGH 0x980
360 #define CHANNEL5CONTROL 0x944
361 #define CHANNEL5CONTROL_HIGH 0x984
363 #define CHANNEL6CONTROL 0x948
364 #define CHANNEL6CONTROL_HIGH 0x988
366 #define CHANNEL7CONTROL 0x94C
367 #define CHANNEL7CONTROL_HIGH 0x98C
370 /****************************************/
372 /****************************************/
374 #define ARBITER_CONTROL_0_3 0x860
375 #define ARBITER_CONTROL_4_7 0x960
378 /****************************************/
380 /****************************************/
382 #define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
383 #define CHANELS0_3_INTERRUPT_MASK 0x8c4
384 #define CHANELS0_3_ERROR_ADDRESS 0x8c8
385 #define CHANELS0_3_ERROR_SELECT 0x8cc
386 #define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
387 #define CHANELS4_7_INTERRUPT_MASK 0x9c4
388 #define CHANELS4_7_ERROR_ADDRESS 0x9c8
389 #define CHANELS4_7_ERROR_SELECT 0x9cc
392 /****************************************/
393 /* DMA Debug (for internal use) */
394 /****************************************/
396 #define DMA_X0_ADDRESS 0x8e0
397 #define DMA_X0_COMMAND_AND_ID 0x8e4
398 #define DMA_X0_WRITE_DATA_LOW 0x8e8
399 #define DMA_X0_WRITE_DATA_HIGH 0x8ec
400 #define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
401 #define DMA_X0_READ_DATA_LOW 0x8f0
402 #define DMA_X0_READ_DATA_HIGH 0x8f4
403 #define DMA_X0_READ_ID 0x8fc
404 #define DMA_X1_ADDRESS 0x9e0
405 #define DMA_X1_COMMAND_AND_ID 0x9e4
406 #define DMA_X1_WRITE_DATA_LOW 0x9e8
407 #define DMA_X1_WRITE_DATA_HIGH 0x9ec
408 #define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
409 #define DMA_X1_READ_DATA_LOW 0x9f0
410 #define DMA_X1_READ_DATA_HIGH 0x9f4
411 #define DMA_X1_READ_ID 0x9fc
413 /****************************************/
415 /****************************************/
417 #define TIMER_COUNTER0 0x850
418 #define TIMER_COUNTER1 0x854
419 #define TIMER_COUNTER2 0x858
420 #define TIMER_COUNTER3 0x85C
421 #define TIMER_COUNTER_0_3_CONTROL 0x864
422 #define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
423 #define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
424 #define TIMER_COUNTER4 0x950
425 #define TIMER_COUNTER5 0x954
426 #define TIMER_COUNTER6 0x958
427 #define TIMER_COUNTER7 0x95C
428 #define TIMER_COUNTER_4_7_CONTROL 0x964
429 #define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
430 #define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
432 /****************************************/
433 /* PCI Slave Address Decoding */
434 /****************************************/
436 #define PCI_0SCS_0_BANK_SIZE 0xc08
437 #define PCI_1SCS_0_BANK_SIZE 0xc88
438 #define PCI_0SCS_1_BANK_SIZE 0xd08
439 #define PCI_1SCS_1_BANK_SIZE 0xd88
440 #define PCI_0SCS_2_BANK_SIZE 0xc0c
441 #define PCI_1SCS_2_BANK_SIZE 0xc8c
442 #define PCI_0SCS_3_BANK_SIZE 0xd0c
443 #define PCI_1SCS_3_BANK_SIZE 0xd8c
444 #define PCI_0CS_0_BANK_SIZE 0xc10
445 #define PCI_1CS_0_BANK_SIZE 0xc90
446 #define PCI_0CS_1_BANK_SIZE 0xd10
447 #define PCI_1CS_1_BANK_SIZE 0xd90
448 #define PCI_0CS_2_BANK_SIZE 0xd18
449 #define PCI_1CS_2_BANK_SIZE 0xd98
450 #define PCI_0CS_3_BANK_SIZE 0xc14
451 #define PCI_1CS_3_BANK_SIZE 0xc94
452 #define PCI_0CS_BOOT_BANK_SIZE 0xd14
453 #define PCI_1CS_BOOT_BANK_SIZE 0xd94
454 #define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
455 #define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
456 #define PCI_0P2P_MEM1_BAR_SIZE 0xd20
457 #define PCI_1P2P_MEM1_BAR_SIZE 0xda0
458 #define PCI_0P2P_I_O_BAR_SIZE 0xd24
459 #define PCI_1P2P_I_O_BAR_SIZE 0xda4
460 #define PCI_0CPU_BAR_SIZE 0xd28
461 #define PCI_1CPU_BAR_SIZE 0xda8
462 #define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
463 #define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
464 #define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
465 #define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
466 #define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
467 #define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
468 #define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
469 #define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
470 #define PCI_0DAC_CS_0_BANK_SIZE 0xe10
471 #define PCI_1DAC_CS_0_BANK_SIZE 0xe90
472 #define PCI_0DAC_CS_1_BANK_SIZE 0xe14
473 #define PCI_1DAC_CS_1_BANK_SIZE 0xe94
474 #define PCI_0DAC_CS_2_BANK_SIZE 0xe18
475 #define PCI_1DAC_CS_2_BANK_SIZE 0xe98
476 #define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
477 #define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
478 #define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
479 #define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
480 #define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
481 #define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
482 #define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
483 #define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
484 #define PCI_0DAC_CPU_BAR_SIZE 0xe2c
485 #define PCI_1DAC_CPU_BAR_SIZE 0xeac
486 #define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
487 #define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
488 #define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
489 #define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
490 #define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
491 #define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
492 #define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
493 #define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
494 #define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
495 #define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
496 #define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
497 #define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
498 #define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
499 #define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
500 #define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
501 #define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
502 #define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
503 #define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
504 #define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
505 #define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
506 #define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
507 #define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
508 #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
509 #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
510 #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
511 #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
512 #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
513 #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
514 #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
515 #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
516 #define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
517 #define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
518 #define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
519 #define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
520 #define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
521 #define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
522 #define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
523 #define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
524 #define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
525 #define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
526 #define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
527 #define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
528 #define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
529 #define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
530 #define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
531 #define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
532 #define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
533 #define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
534 #define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
535 #define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
536 #define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
537 #define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
538 #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
539 #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
540 #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
541 #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
542 #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
543 #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
544 #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
545 #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
546 #define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
547 #define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
548 #define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
549 #define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
550 #define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
551 #define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
553 /****************************************/
555 /****************************************/
557 #define PCI_0COMMAND 0xc00
558 #define PCI_1COMMAND 0xc80
559 #define PCI_0MODE 0xd00
560 #define PCI_1MODE 0xd80
561 #define PCI_0TIMEOUT_RETRY 0xc04
562 #define PCI_1TIMEOUT_RETRY 0xc84
563 #define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
564 #define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
565 #define MSI_0TRIGGER_TIMER 0xc38
566 #define MSI_1TRIGGER_TIMER 0xcb8
567 #define PCI_0ARBITER_CONTROL 0x1d00
568 #define PCI_1ARBITER_CONTROL 0x1d80
569 /* changing untill here */
570 #define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
571 #define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
572 #define PCI_0CROSS_BAR_TIMEOUT 0x1d04
573 #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
574 #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
575 #define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
576 #define PCI_0P2P_CONFIGURATION 0x1d14
577 #define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
578 #define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
579 #define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
580 #define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10
581 #define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
582 #define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
583 #define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20
584 #define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
585 #define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
586 #define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30
587 #define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
588 #define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
589 #define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40
590 #define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
591 #define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
592 #define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50
593 #define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
594 #define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
595 #define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60
596 #define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
597 #define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
598 #define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70
599 #define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
600 #define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
601 #define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
602 #define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
603 #define PCI_1CROSS_BAR_TIMEOUT 0x1d84
604 #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
605 #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
606 #define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
607 #define PCI_1P2P_CONFIGURATION 0x1d94
608 #define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
609 #define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
610 #define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
611 #define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90
612 #define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
613 #define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
614 #define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0
615 #define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
616 #define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
617 #define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0
618 #define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
619 #define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
620 #define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0
621 #define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
622 #define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
623 #define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0
624 #define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
625 #define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
626 #define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0
627 #define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
628 #define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
629 #define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0
630 #define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
631 #define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
633 /****************************************/
634 /* PCI Snoop Control */
635 /****************************************/
637 #define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
638 #define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
639 #define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
640 #define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
641 #define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
642 #define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
643 #define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
644 #define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
645 #define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
646 #define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
647 #define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
648 #define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
649 #define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
650 #define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
651 #define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
652 #define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
653 #define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
654 #define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
655 #define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
656 #define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
657 #define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
658 #define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
659 #define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
660 #define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
662 /****************************************/
663 /* PCI Configuration Address */
664 /****************************************/
666 #define PCI_0CONFIGURATION_ADDRESS 0xcf8
667 #define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
668 #define PCI_1CONFIGURATION_ADDRESS 0xc78
669 #define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
670 #define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
671 #define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
673 /****************************************/
674 /* PCI Error Report */
675 /****************************************/
677 #define PCI_0SERR_MASK 0xc28
678 #define PCI_0ERROR_ADDRESS_LOW 0x1d40
679 #define PCI_0ERROR_ADDRESS_HIGH 0x1d44
680 #define PCI_0ERROR_DATA_LOW 0x1d48
681 #define PCI_0ERROR_DATA_HIGH 0x1d4c
682 #define PCI_0ERROR_COMMAND 0x1d50
683 #define PCI_0ERROR_CAUSE 0x1d58
684 #define PCI_0ERROR_MASK 0x1d5c
686 #define PCI_1SERR_MASK 0xca8
687 #define PCI_1ERROR_ADDRESS_LOW 0x1dc0
688 #define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
689 #define PCI_1ERROR_DATA_LOW 0x1dc8
690 #define PCI_1ERROR_DATA_HIGH 0x1dcc
691 #define PCI_1ERROR_COMMAND 0x1dd0
692 #define PCI_1ERROR_CAUSE 0x1dd8
693 #define PCI_1ERROR_MASK 0x1ddc
696 /****************************************/
697 /* Lslave Debug (for internal use) */
698 /****************************************/
700 #define L_SLAVE_X0_ADDRESS 0x1d20
701 #define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
702 #define L_SLAVE_X1_ADDRESS 0x1d28
703 #define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
704 #define L_SLAVE_WRITE_DATA_LOW 0x1d30
705 #define L_SLAVE_WRITE_DATA_HIGH 0x1d34
706 #define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
707 #define L_SLAVE_READ_DATA_LOW 0x1d38
708 #define L_SLAVE_READ_DATA_HIGH 0x1d3c
709 #define L_SLAVE_READ_ID 0x1d64
711 /****************************************/
712 /* PCI Configuration Function 0 */
713 /****************************************/
715 #define PCI_DEVICE_AND_VENDOR_ID 0x000
716 #define PCI_STATUS_AND_COMMAND 0x004
717 #define PCI_CLASS_CODE_AND_REVISION_ID 0x008
718 #define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
719 #define PCI_SCS_0_BASE_ADDRESS 0x010
720 #define PCI_SCS_1_BASE_ADDRESS 0x014
721 #define PCI_SCS_2_BASE_ADDRESS 0x018
722 #define PCI_SCS_3_BASE_ADDRESS 0x01C
723 #define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
724 #define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
725 #define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
726 #define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
727 #define PCI_CAPABILTY_LIST_POINTER 0x034
728 #define PCI_INTERRUPT_PIN_AND_LINE 0x03C
729 #define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
730 #define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
731 #define PCI_VPD_ADDRESS 0x048
732 #define PCI_VPD_DATA 0X04c
733 #define PCI_MSI_MESSAGE_CONTROL 0x050
734 #define PCI_MSI_MESSAGE_ADDRESS 0x054
735 #define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
736 #define PCI_MSI_MESSAGE_DATA 0x05c
737 #define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
739 /****************************************/
740 /* PCI Configuration Function 1 */
741 /****************************************/
743 #define PCI_CS_0_BASE_ADDRESS 0x110
744 #define PCI_CS_1_BASE_ADDRESS 0x114
745 #define PCI_CS_2_BASE_ADDRESS 0x118
746 #define PCI_CS_3_BASE_ADDRESS 0x11c
747 #define PCI_BOOTCS_BASE_ADDRESS 0x120
749 /****************************************/
750 /* PCI Configuration Function 2 */
751 /****************************************/
753 #define PCI_P2P_MEM0_BASE_ADDRESS 0x210
754 #define PCI_P2P_MEM1_BASE_ADDRESS 0x214
755 #define PCI_P2P_I_O_BASE_ADDRESS 0x218
756 #define PCI_CPU_BASE_ADDRESS 0x21c
758 /****************************************/
759 /* PCI Configuration Function 4 */
760 /****************************************/
762 #define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
763 #define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
764 #define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
765 #define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
766 #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
767 #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
770 /****************************************/
771 /* PCI Configuration Function 5 */
772 /****************************************/
774 #define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
775 #define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
776 #define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
777 #define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
778 #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
779 #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
782 /****************************************/
783 /* PCI Configuration Function 6 */
784 /****************************************/
786 #define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
787 #define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
788 #define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
789 #define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
790 #define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
791 #define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
793 /****************************************/
794 /* PCI Configuration Function 7 */
795 /****************************************/
797 #define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
798 #define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
799 #define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
800 #define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
801 #define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
802 #define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
804 /****************************************/
806 /****************************************/
808 #define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
809 #define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
810 #define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
811 #define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
812 #define CPU_SELECT_CAUSE_REGISTER 0xc70
813 #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
814 #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
815 #define PCI_0SELECT_CAUSE 0xc74
816 #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
817 #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
818 #define PCI_1SELECT_CAUSE 0xcf4
819 #define CPU_INT_0_MASK 0xe60
820 #define CPU_INT_1_MASK 0xe64
821 #define CPU_INT_2_MASK 0xe68
822 #define CPU_INT_3_MASK 0xe6c
824 /****************************************/
825 /* I20 Support registers */
826 /****************************************/
828 #define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010
829 #define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014
830 #define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018
831 #define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C
832 #define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020
833 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024
834 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028
835 #define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C
836 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030
837 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034
838 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040
839 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044
840 #define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050
841 #define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054
842 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060
843 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064
844 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068
845 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C
846 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070
847 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074
848 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8
849 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC
851 #define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090
852 #define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094
853 #define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098
854 #define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C
855 #define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0
856 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4
857 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8
858 #define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC
859 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0
860 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4
861 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0
862 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4
863 #define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0
864 #define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4
865 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0
866 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4
867 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8
868 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC
869 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0
870 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4
871 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078
872 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C
874 #define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10
875 #define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14
876 #define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18
877 #define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C
878 #define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20
879 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24
880 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28
881 #define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C
882 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30
883 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34
884 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40
885 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44
886 #define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50
887 #define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54
888 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60
889 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64
890 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68
891 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C
892 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70
893 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74
894 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8
895 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC
897 #define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90
898 #define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94
899 #define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98
900 #define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C
901 #define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0
902 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4
903 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8
904 #define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC
905 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0
906 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4
907 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0
908 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4
909 #define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0
910 #define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4
911 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0
912 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4
913 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8
914 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC
915 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0
916 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4
917 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78
918 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C
920 /****************************************/
921 /* Communication Unit Registers */
922 /****************************************/
924 #define ETHERNET_0_ADDRESS_CONTROL_LOW
925 #define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
926 #define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
927 #define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
928 #define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
929 #define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
930 #define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
931 #define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
932 #define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
933 #define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
934 #define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
935 #define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
936 #define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
937 #define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
938 #define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
939 #define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
940 #define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
941 #define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
942 #define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
943 #define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
944 #define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
945 #define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
946 #define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
947 #define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
948 #define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
949 #define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
950 #define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
951 #define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0
952 #define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4
953 #define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8
954 #define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac
955 #define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0
956 #define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4
957 #define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0
958 #define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4
959 #define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
960 #define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
961 #define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
962 #define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
963 #define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
964 #define SERIAL_INIT_LAST_DATA 0xf324
965 #define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
966 #define COMM_UNIT_ARBITER_CONTROL 0xf300
967 #define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
968 #define COMM_UNIT_INTERRUPT_CAUSE 0xf310
969 #define COMM_UNIT_INTERRUPT_MASK 0xf314
970 #define COMM_UNIT_ERROR_ADDRESS 0xf314
972 /****************************************/
973 /* Cunit Debug (for internal use) */
974 /****************************************/
976 #define CUNIT_ADDRESS 0xf340
977 #define CUNIT_COMMAND_AND_ID 0xf344
978 #define CUNIT_WRITE_DATA_LOW 0xf348
979 #define CUNIT_WRITE_DATA_HIGH 0xf34c
980 #define CUNIT_WRITE_BYTE_ENABLE 0xf358
981 #define CUNIT_READ_DATA_LOW 0xf350
982 #define CUNIT_READ_DATA_HIGH 0xf354
983 #define CUNIT_READ_ID 0xf35c
985 /****************************************/
986 /* Fast Ethernet Unit Registers */
987 /****************************************/
991 #define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
992 #define ETHERNET_SMI_REGISTER 0x2010
996 #define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
997 #define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
998 #define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
999 #define ETHERNET0_PORT_STATUS_REGISTER 0x2418
1000 #define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
1001 #define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
1002 #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
1003 #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
1004 #define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
1005 #define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
1006 #define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
1007 #define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
1008 #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
1009 #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
1010 #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
1011 #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
1012 #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
1013 #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
1014 #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
1015 #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
1016 #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
1017 #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
1018 #define ETHERNET0_MIB_COUNTER_BASE 0x2500
1022 #define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
1023 #define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
1024 #define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
1025 #define ETHERNET1_PORT_STATUS_REGISTER 0x2818
1026 #define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
1027 #define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
1028 #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
1029 #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
1030 #define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
1031 #define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
1032 #define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
1033 #define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
1034 #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
1035 #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
1036 #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
1037 #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
1038 #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
1039 #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
1040 #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
1041 #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
1042 #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
1043 #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
1044 #define ETHERNET1_MIB_COUNTER_BASE 0x2900
1048 #define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
1049 #define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
1050 #define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
1051 #define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
1052 #define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
1053 #define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
1054 #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
1055 #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
1056 #define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
1057 #define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
1058 #define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
1059 #define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
1060 #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
1061 #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
1062 #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
1063 #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
1064 #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
1065 #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
1066 #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
1067 #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
1068 #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
1069 #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
1070 #define ETHERNET2_MIB_COUNTER_BASE 0x2d00
1072 /****************************************/
1073 /* SDMA Registers */
1074 /****************************************/
1076 #define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
1077 #define CHANNEL0_CONFIGURATION_REGISTER 0x4000
1078 #define CHANNEL0_COMMAND_REGISTER 0x4008
1079 #define CHANNEL0_RX_CMD_STATUS 0x4800
1080 #define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
1081 #define CHANNEL0_RX_BUFFER_POINTER 0x4808
1082 #define CHANNEL0_RX_NEXT_POINTER 0x480c
1083 #define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
1084 #define CHANNEL0_TX_CMD_STATUS 0x4C00
1085 #define CHANNEL0_TX_PACKET_SIZE 0x4C04
1086 #define CHANNEL0_TX_BUFFER_POINTER 0x4C08
1087 #define CHANNEL0_TX_NEXT_POINTER 0x4C0c
1088 #define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
1089 #define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
1090 #define CHANNEL1_CONFIGURATION_REGISTER 0x6000
1091 #define CHANNEL1_COMMAND_REGISTER 0x6008
1092 #define CHANNEL1_RX_CMD_STATUS 0x6800
1093 #define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804
1094 #define CHANNEL1_RX_BUFFER_POINTER 0x6808
1095 #define CHANNEL1_RX_NEXT_POINTER 0x680c
1096 #define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1097 #define CHANNEL1_TX_CMD_STATUS 0x6C00
1098 #define CHANNEL1_TX_PACKET_SIZE 0x6C04
1099 #define CHANNEL1_TX_BUFFER_POINTER 0x6C08
1100 #define CHANNEL1_TX_NEXT_POINTER 0x6C0c
1101 #define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1102 #define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
1103 #define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
1105 /* SDMA Interrupt */
1107 #define SDMA_CAUSE 0xb820
1108 #define SDMA_MASK 0xb8a0
1111 /****************************************/
1112 /* Baude Rate Generators Registers */
1113 /****************************************/
1117 #define BRG0_CONFIGURATION_REGISTER 0xb200
1118 #define BRG0_BAUDE_TUNING_REGISTER 0xb204
1122 #define BRG1_CONFIGURATION_REGISTER 0xb208
1123 #define BRG1_BAUDE_TUNING_REGISTER 0xb20c
1127 #define BRG2_CONFIGURATION_REGISTER 0xb210
1128 #define BRG2_BAUDE_TUNING_REGISTER 0xb214
1130 /* BRG Interrupts */
1132 #define BRG_CAUSE_REGISTER 0xb834
1133 #define BRG_MASK_REGISTER 0xb8b4
1137 #define MAIN_ROUTING_REGISTER 0xb400
1138 #define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
1139 #define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
1140 #define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
1141 #define WATCHDOG_CONFIGURATION_REGISTER 0xb410
1142 #define WATCHDOG_VALUE_REGISTER 0xb414
1145 /****************************************/
1146 /* Flex TDM Registers */
1147 /****************************************/
1151 #define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
1152 #define FLEXTDM_RECEIVE_READ_POINTER 0xa804
1153 #define FLEXTDM_CONFIGURATION_REGISTER 0xa808
1154 #define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
1155 #define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
1156 #define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
1157 #define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
1159 /* FTDM Interrupts */
1161 #define FTDM_CAUSE_REGISTER 0xb830
1162 #define FTDM_MASK_REGISTER 0xb8b0
1165 /****************************************/
1166 /* GPP Interface Registers */
1167 /****************************************/
1169 #define GPP_IO_CONTROL 0xf100
1170 #define GPP_LEVEL_CONTROL 0xf110
1171 #define GPP_VALUE 0xf104
1172 #define GPP_INTERRUPT_CAUSE 0xf108
1173 #define GPP_INTERRUPT_MASK 0xf10c
1175 #define MPP_CONTROL0 0xf000
1176 #define MPP_CONTROL1 0xf004
1177 #define MPP_CONTROL2 0xf008
1178 #define MPP_CONTROL3 0xf00c
1179 #define DEBUG_PORT_MULTIPLEX 0xf014
1180 #define SERIAL_PORT_MULTIPLEX 0xf010
1182 /****************************************/
1184 /****************************************/
1186 #define I2C_SLAVE_ADDRESS 0xc000
1187 #define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
1188 #define I2C_DATA 0xc004
1189 #define I2C_CONTROL 0xc008
1190 #define I2C_STATUS_BAUDE_RATE 0xc00C
1191 #define I2C_SOFT_RESET 0xc01c
1193 /****************************************/
1194 /* MPSC Registers */
1195 /****************************************/
1199 #define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
1200 #define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
1201 #define MPSC0_PROTOCOL_CONFIGURATION 0x8008
1202 #define CHANNEL0_REGISTER1 0x800c
1203 #define CHANNEL0_REGISTER2 0x8010
1204 #define CHANNEL0_REGISTER3 0x8014
1205 #define CHANNEL0_REGISTER4 0x8018
1206 #define CHANNEL0_REGISTER5 0x801c
1207 #define CHANNEL0_REGISTER6 0x8020
1208 #define CHANNEL0_REGISTER7 0x8024
1209 #define CHANNEL0_REGISTER8 0x8028
1210 #define CHANNEL0_REGISTER9 0x802c
1211 #define CHANNEL0_REGISTER10 0x8030
1212 #define CHANNEL0_REGISTER11 0x8034
1216 #define MPSC1_MAIN_CONFIGURATION_LOW 0x9000
1217 #define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004
1218 #define MPSC1_PROTOCOL_CONFIGURATION 0x9008
1219 #define CHANNEL1_REGISTER1 0x900c
1220 #define CHANNEL1_REGISTER2 0x9010
1221 #define CHANNEL1_REGISTER3 0x9014
1222 #define CHANNEL1_REGISTER4 0x9018
1223 #define CHANNEL1_REGISTER5 0x901c
1224 #define CHANNEL1_REGISTER6 0x9020
1225 #define CHANNEL1_REGISTER7 0x9024
1226 #define CHANNEL1_REGISTER8 0x9028
1227 #define CHANNEL1_REGISTER9 0x902c
1228 #define CHANNEL1_REGISTER10 0x9030
1229 #define CHANNEL1_REGISTER11 0x9034
1231 /* MPSCs Interupts */
1233 #define MPSC0_CAUSE 0xb804
1234 #define MPSC0_MASK 0xb884
1235 #define MPSC1_CAUSE 0xb80c
1236 #define MPSC1_MASK 0xb88c
1238 #endif /* __INCgt64240rh */