2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * MIPS boards specific PCI support.
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
26 #include <asm/mips-boards/msc01_pci.h>
28 #define PCI_ACCESS_READ 0
29 #define PCI_ACCESS_WRITE 1
32 * PCI configuration cycle AD bus definition
35 #define PCI_CFG_TYPE0_REG_SHF 0
36 #define PCI_CFG_TYPE0_FUNC_SHF 8
39 #define PCI_CFG_TYPE1_REG_SHF 0
40 #define PCI_CFG_TYPE1_FUNC_SHF 8
41 #define PCI_CFG_TYPE1_DEV_SHF 11
42 #define PCI_CFG_TYPE1_BUS_SHF 16
44 static int msc_pcibios_config_access(unsigned char access_type,
45 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
47 unsigned char busnum = bus->number;
51 #ifdef CONFIG_MIPS_BOARDS_GEN
52 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
53 /* MIPS Core boards have SOCit connected as device 17 */
58 /* Clear status register bits. */
59 MSC_WRITE(MSC01_PCI_INTSTAT,
60 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
64 type = 0; /* Type 0 */
66 type = 1; /* Type 1 */
68 MSC_WRITE(MSC01_PCI_CFGADDR,
69 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
70 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)
72 MSC01_PCI_CFGADDR_FNUM_SHF) | ((where /
74 MSC01_PCI_CFGADDR_RNUM_SHF)
78 if (access_type == PCI_ACCESS_WRITE)
79 MSC_WRITE(MSC01_PCI_CFGDATA, *data);
81 MSC_READ(MSC01_PCI_CFGDATA, *data);
83 /* Detect Master/Target abort */
84 MSC_READ(MSC01_PCI_INTSTAT, intr);
85 if (intr & (MSC01_PCI_INTCFG_MA_BIT |
86 MSC01_PCI_INTCFG_TA_BIT)) {
90 MSC_READ(MSC01_PCI_INTSTAT, intr);
91 MSC_WRITE(MSC01_PCI_INTSTAT,
92 (MSC01_PCI_INTCFG_MA_BIT |
93 MSC01_PCI_INTCFG_TA_BIT));
103 * We can't address 8 and 16 bit words directly. Instead we have to
104 * read/write a 32bit word and mask/modify the data we actually want.
106 static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
107 int where, int size, u32 * val)
111 if ((size == 2) && (where & 1))
112 return PCIBIOS_BAD_REGISTER_NUMBER;
113 else if ((size == 4) && (where & 3))
114 return PCIBIOS_BAD_REGISTER_NUMBER;
116 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
121 *val = (data >> ((where & 3) << 3)) & 0xff;
123 *val = (data >> ((where & 3) << 3)) & 0xffff;
127 return PCIBIOS_SUCCESSFUL;
130 static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
131 int where, int size, u32 val)
135 if ((size == 2) && (where & 1))
136 return PCIBIOS_BAD_REGISTER_NUMBER;
137 else if ((size == 4) && (where & 3))
138 return PCIBIOS_BAD_REGISTER_NUMBER;
143 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
148 data = (data & ~(0xff << ((where & 3) << 3))) |
149 (val << ((where & 3) << 3));
151 data = (data & ~(0xffff << ((where & 3) << 3))) |
152 (val << ((where & 3) << 3));
155 if (msc_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
159 return PCIBIOS_SUCCESSFUL;
162 struct pci_ops msc_pci_ops = {
163 .read = msc_pcibios_read,
164 .write = msc_pcibios_write