1 #include <linux/kernel.h>
2 #include <linux/init.h>
3 #include <linux/types.h>
6 #include <asm/pci_channel.h>
9 #include <asm/ddb5xxx/ddb5xxx.h>
11 static struct resource extpci_io_resource = {
13 0x1000, /* leave some room for ISA bus */
18 static struct resource extpci_mem_resource = {
20 DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
21 DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
25 extern struct pci_ops ddb5476_ext_pci_ops;
27 struct pci_controller ddb5476_controller = {
28 .pci_ops = &ddb5476_ext_pci_ops,
29 .io_resource = &extpci_io_resource,
30 .mem_resource = &extpci_mem_resource
35 * we fix up irqs based on the slot number.
36 * The first entry is at AD:11.
38 * This does not work for devices on sub-buses yet.
45 #define PCI_EXT_INTA 8
46 #define PCI_EXT_INTB 9
47 #define PCI_EXT_INTC 10
48 #define PCI_EXT_INTD 11
49 #define PCI_EXT_INTE 12
52 * based on ddb5477 manual page 11
54 #define MAX_SLOT_NUM 21
55 static unsigned char irq_map[MAX_SLOT_NUM] = {
56 [ 2] = 9, /* AD:13 USB */
57 [ 3] = 10, /* AD:14 PMU */
58 [ 5] = 0, /* AD:16 P2P bridge */
59 [ 6] = nile4_to_irq(PCI_EXT_INTB), /* AD:17 */
60 [ 7] = nile4_to_irq(PCI_EXT_INTC), /* AD:18 */
61 [ 8] = nile4_to_irq(PCI_EXT_INTD), /* AD:19 */
62 [ 9] = nile4_to_irq(PCI_EXT_INTA), /* AD:20 */
63 [13] = 14, /* AD:24 HD controller, M5229 */
66 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
71 void __init ddb_pci_reset_bus(void)
76 * I am not sure about the "official" procedure, the following
77 * steps work as far as I know:
78 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
79 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
80 * The same is true for both PCI channels.
82 temp = ddb_in32(DDB_PCICTRL + 4);
84 ddb_out32(DDB_PCICTRL + 4, temp);
86 ddb_out32(DDB_PCICTRL + 4, temp);