2 * Copyright 2002 Momentum Computer
3 * Author: Matthew Dharm <mdharm@momenco.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/types.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
33 #include <linux/init.h>
36 #define MASTER_ABORT_BIT 0x100
39 * These functions and structures provide the BIOS scan and mapping of the PCI
43 void gt64240_board_pcibios_fixup_bus(struct pci_bus *c);
45 /* Functions to implement "pci ops" */
46 static int galileo_pcibios_read_config_word(int bus, int devfn,
47 int offset, u16 * val);
48 static int galileo_pcibios_read_config_byte(int bus, int devfn,
49 int offset, u8 * val);
50 static int galileo_pcibios_read_config_dword(int bus, int devfn,
51 int offset, u32 * val);
52 static int galileo_pcibios_write_config_byte(int bus, int devfn,
54 static int galileo_pcibios_write_config_word(int bus, int devfn,
56 static int galileo_pcibios_write_config_dword(int bus, int devfn,
59 static int pci_read(struct pci_bus *bus, unsigned int devfs, int where,
61 static int pci_write(struct pci_bus *bus, unsigned int devfs, int where,
65 * General-purpose PCI functions.
72 * Check if the pci device that are trying to access does really exists
73 * on the evaluation board.
76 * bus - bus number (0 for PCI 0 ; 1 for PCI 1)
77 * dev - number of device on the specific pci bus
80 * 0 - if OK , 1 - if failure
82 static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
84 /* Accessing device 31 crashes the GT-64240. */
91 * galileo_pcibios_(read/write)_config_(dword/word/byte) -
93 * reads/write a dword/word/byte register from the configuration space
96 * Note that bus 0 and bus 1 are local, and we assume all other busses are
97 * bridged from bus 1. This is a safe assumption, since any other
98 * configuration will require major modifications to the CP7000G
102 * dev - device number
103 * offset - register offset in the configuration space
104 * val - value to be written / read
107 * PCIBIOS_SUCCESSFUL when operation was succesfull
108 * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
109 * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
112 static int galileo_pcibios_read_config_dword(int bus, int devfn,
113 int offset, u32 * val)
116 uint32_t address_reg, data_reg;
119 dev = PCI_SLOT(devfn);
120 func = PCI_FUNC(devfn);
122 /* verify the range */
123 if (pci_range_ck(bus, dev))
124 return PCIBIOS_DEVICE_NOT_FOUND;
126 /* select the GT-64240 registers to communicate with the PCI bus */
128 address_reg = PCI_0CONFIGURATION_ADDRESS;
129 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
130 GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT);
132 address_reg = PCI_1CONFIGURATION_ADDRESS;
133 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
134 GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT);
139 address = (bus << 16) | (dev << 11) | (func << 8) |
140 (offset & 0xfc) | 0x80000000;
142 /* start the configuration cycle */
143 GT_WRITE(address_reg, address);
146 GT_READ(data_reg, val);
148 return PCIBIOS_SUCCESSFUL;
152 static int galileo_pcibios_read_config_word(int bus, int devfn,
153 int offset, u16 * val)
156 uint32_t address_reg, data_reg;
159 dev = PCI_SLOT(devfn);
160 func = PCI_FUNC(devfn);
162 /* verify the range */
163 if (pci_range_ck(bus, dev))
164 return PCIBIOS_DEVICE_NOT_FOUND;
166 /* select the GT-64240 registers to communicate with the PCI bus */
168 address_reg = PCI_0CONFIGURATION_ADDRESS;
169 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
170 GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT);
172 address_reg = PCI_1CONFIGURATION_ADDRESS;
173 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
174 GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT);
179 address = (bus << 16) | (dev << 11) | (func << 8) |
180 (offset & 0xfc) | 0x80000000;
182 /* start the configuration cycle */
183 GT_WRITE(address_reg, address);
186 GT_READ_16(data_reg + (offset & 0x3), val);
188 return PCIBIOS_SUCCESSFUL;
191 static int galileo_pcibios_read_config_byte(int bus, int devfn,
192 int offset, u8 * val)
195 uint32_t address_reg, data_reg;
198 dev = PCI_SLOT(devfn);
199 func = PCI_FUNC(devfn);
201 /* verify the range */
202 if (pci_range_ck(bus, dev))
203 return PCIBIOS_DEVICE_NOT_FOUND;
205 /* select the GT-64240 registers to communicate with the PCI bus */
207 address_reg = PCI_0CONFIGURATION_ADDRESS;
208 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
210 address_reg = PCI_1CONFIGURATION_ADDRESS;
211 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
216 address = (bus << 16) | (dev << 11) | (func << 8) |
217 (offset & 0xfc) | 0x80000000;
219 /* start the configuration cycle */
220 GT_WRITE(address_reg, address);
223 GT_READ_8(data_reg + (offset & 0x3), val);
225 return PCIBIOS_SUCCESSFUL;
228 static int galileo_pcibios_write_config_dword(int bus, int devfn,
232 uint32_t address_reg, data_reg;
235 dev = PCI_SLOT(devfn);
236 func = PCI_FUNC(devfn);
238 /* verify the range */
239 if (pci_range_ck(bus, dev))
240 return PCIBIOS_DEVICE_NOT_FOUND;
242 /* select the GT-64240 registers to communicate with the PCI bus */
244 address_reg = PCI_0CONFIGURATION_ADDRESS;
245 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
247 address_reg = PCI_1CONFIGURATION_ADDRESS;
248 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
253 address = (bus << 16) | (dev << 11) | (func << 8) |
254 (offset & 0xfc) | 0x80000000;
256 /* start the configuration cycle */
257 GT_WRITE(address_reg, address);
260 GT_WRITE(data_reg, val);
262 return PCIBIOS_SUCCESSFUL;
266 static int galileo_pcibios_write_config_word(int bus, int devfn,
270 uint32_t address_reg, data_reg;
273 dev = PCI_SLOT(devfn);
274 func = PCI_FUNC(devfn);
276 /* verify the range */
277 if (pci_range_ck(bus, dev))
278 return PCIBIOS_DEVICE_NOT_FOUND;
280 /* select the GT-64240 registers to communicate with the PCI bus */
282 address_reg = PCI_0CONFIGURATION_ADDRESS;
283 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
285 address_reg = PCI_1CONFIGURATION_ADDRESS;
286 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
291 address = (bus << 16) | (dev << 11) | (func << 8) |
292 (offset & 0xfc) | 0x80000000;
294 /* start the configuration cycle */
295 GT_WRITE(address_reg, address);
298 GT_WRITE_16(data_reg + (offset & 0x3), val);
300 return PCIBIOS_SUCCESSFUL;
303 static int galileo_pcibios_write_config_byte(int bus, int devfn,
307 uint32_t address_reg, data_reg;
310 dev = PCI_SLOT(devfn);
311 func = PCI_FUNC(devfn);
313 /* verify the range */
314 if (pci_range_ck(bus, dev))
315 return PCIBIOS_DEVICE_NOT_FOUND;
317 /* select the GT-64240 registers to communicate with the PCI bus */
319 address_reg = PCI_0CONFIGURATION_ADDRESS;
320 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
322 address_reg = PCI_1CONFIGURATION_ADDRESS;
323 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
328 address = (bus << 16) | (dev << 11) | (func << 8) |
329 (offset & 0xfc) | 0x80000000;
331 /* start the configuration cycle */
332 GT_WRITE(address_reg, address);
335 GT_WRITE_8(data_reg + (offset & 0x3), val);
337 return PCIBIOS_SUCCESSFUL;
340 struct pci_ops galileo_pci_ops = {
345 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
350 return galileo_pcibios_read_config_byte(bus->number,
354 return galileo_pcibios_read_config_word(bus->number,
358 return galileo_pcibios_read_config_dword(bus->number,
362 return PCIBIOS_FUNC_NOT_SUPPORTED;
365 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
370 return galileo_pcibios_write_config_byte(bus->number,
374 return galileo_pcibios_write_config_word(bus->number,
378 return galileo_pcibios_write_config_dword(bus->number,
382 return PCIBIOS_FUNC_NOT_SUPPORTED;
385 struct pci_fixup pcibios_fixups[] = {
389 void __devinit pcibios_fixup_bus(struct pci_bus *c)
391 gt64240_board_pcibios_fixup_bus(c);
395 /********************************************************************
396 * pci0P2PConfig - This function set the PCI_0 P2P configurate.
397 * For more information on the P2P read PCI spec.
399 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
401 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
403 * unsigned int busNum - The CPI bus number to which the PCI interface
405 * unsigned int devNum - The PCI interface's device number.
409 void pci0P2PConfig(unsigned int SecondBusLow, unsigned int SecondBusHigh,
410 unsigned int busNum, unsigned int devNum)
414 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
415 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
416 GT_WRITE(PCI_0P2P_CONFIGURATION, regData);
419 /********************************************************************
420 * pci1P2PConfig - This function set the PCI_1 P2P configurate.
421 * For more information on the P2P read PCI spec.
423 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
425 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
427 * unsigned int busNum - The CPI bus number to which the PCI interface
429 * unsigned int devNum - The PCI interface's device number.
433 void pci1P2PConfig(unsigned int SecondBusLow, unsigned int SecondBusHigh,
434 unsigned int busNum, unsigned int devNum)
438 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
439 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
440 GT_WRITE(PCI_1P2P_CONFIGURATION, regData);
443 #define PCI0_STATUS_COMMAND_REG 0x4
444 #define PCI1_STATUS_COMMAND_REG 0x84
446 static int __init pcibios_init(void)
448 /* Reset PCI I/O and PCI MEM values */
449 ioport_resource.start = 0xe0000000;
450 ioport_resource.end = 0xe0000000 + 0x20000000 - 1;
451 iomem_resource.start = 0xc0000000;
452 iomem_resource.end = 0xc0000000 + 0x20000000 - 1;
454 pci_scan_bus(0, &galileo_pci_ops, NULL);
455 pci_scan_bus(1, &galileo_pci_ops, NULL);
460 subsys_initcall(pcibios_init);