2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 * BCM1250-specific PCI support
22 * This module provides the glue between Linux's PCI subsystem
23 * and the hardware. We basically provide glue for accessing
24 * configuration space, and set up the translation for I/O
27 * To access configuration space, we use ioremap. In the 32-bit
28 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
29 * kernel mapped memory. Hopefully neither of these should be a huge
32 #include <linux/config.h>
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/init.h>
38 #include <linux/console.h>
41 #include <asm/pci_channel.h>
43 #include <asm/sibyte/sb1250_defs.h>
44 #include <asm/sibyte/sb1250_regs.h>
45 #include <asm/sibyte/sb1250_scd.h>
46 #include <asm/sibyte/board.h>
49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg
52 #define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where))
53 #define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
55 static void *cfg_space;
57 #define PCI_BUS_ENABLED 1
58 #define LDT_BUS_ENABLED 2
59 #define PCI_DEVICE_MODE 4
61 static int sb1250_bus_status = 0;
63 #define PCI_BRIDGE_DEVICE 0
64 #define LDT_BRIDGE_DEVICE 1
66 #ifdef CONFIG_SIBYTE_HAS_LDT
68 * HT's level-sensitive interrupts require EOI, which is generated
69 * through a 4MB memory-mapped region
71 unsigned long ldt_eoi_space;
75 * Read/write 32-bit values in config space.
77 static inline u32 READCFG32(u32 addr)
79 return *(u32 *) (cfg_space + (addr & ~3));
82 static inline void WRITECFG32(u32 addr, u32 data)
84 *(u32 *) (cfg_space + (addr & ~3)) = data;
87 int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
93 * Some checks before doing config cycles:
94 * In PCI Device Mode, hide everything on bus 0 except the LDT host
95 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
97 static int sb1250_pci_can_access(struct pci_bus *bus, int devfn)
101 if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
104 if (bus->number == 0) {
105 devno = PCI_SLOT(devfn);
106 if (devno == LDT_BRIDGE_DEVICE)
107 return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
108 else if (sb1250_bus_status & PCI_DEVICE_MODE)
117 * Read/write access functions for various sizes of values
118 * in config space. Return all 1's for disallowed accesses
119 * for a kludgy but adequate simulation of master aborts.
122 static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn,
123 int where, int size, u32 * val)
127 if ((size == 2) && (where & 1))
128 return PCIBIOS_BAD_REGISTER_NUMBER;
129 else if ((size == 4) && (where & 3))
130 return PCIBIOS_BAD_REGISTER_NUMBER;
132 if (sb1250_pci_can_access(bus, devfn))
133 data = READCFG32(CFGADDR(bus, devfn, where));
138 *val = (data >> ((where & 3) << 3)) & 0xff;
140 *val = (data >> ((where & 3) << 3)) & 0xffff;
144 return PCIBIOS_SUCCESSFUL;
147 static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
148 int where, int size, u32 val)
150 u32 cfgaddr = CFGADDR(bus, devfn, where);
153 if ((size == 2) && (where & 1))
154 return PCIBIOS_BAD_REGISTER_NUMBER;
155 else if ((size == 4) && (where & 3))
156 return PCIBIOS_BAD_REGISTER_NUMBER;
158 if (!sb1250_pci_can_access(bus, devfn))
159 return PCIBIOS_BAD_REGISTER_NUMBER;
161 data = READCFG32(cfgaddr);
164 data = (data & ~(0xff << ((where & 3) << 3))) |
165 (val << ((where & 3) << 3));
167 data = (data & ~(0xffff << ((where & 3) << 3))) |
168 (val << ((where & 3) << 3));
172 WRITECFG32(cfgaddr, data);
174 return PCIBIOS_SUCCESSFUL;
177 struct pci_ops sb1250_pci_ops = {
178 .read = sb1250_pcibios_read,
179 .write = sb1250_pcibios_write
182 static struct resource sb1250_mem_resource = {
183 .name = "SB1250 PCI MEM",
184 .start = 0x14000000UL,
186 .flags = IORESOURCE_MEM,
189 static struct resource sb1250_io_resource = {
190 .name = "SB1250 IO MEM",
191 .start = 0x14000000UL,
193 .flags = IORESOURCE_IO,
196 struct pci_controller sb1250_controller = {
197 .pci_ops = &sb1250_pci_ops,
198 .mem_resource = &sb1250_mem_resource,
199 .io_resource = &sb1250_io_resource
202 static int __init sb1250_pcibios_init(void)
206 extern int pci_probe_only;
208 /* CFE will assign PCI resources */
211 /* set resource limit to avoid errors */
212 ioport_resource.end = 0x0000ffff; /* 32MB reserved by sb1250 */
213 iomem_resource.end = 0xffffffff; /* no HT support yet */
216 ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);
219 * See if the PCI bus has been configured by the firmware.
221 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
222 if (!(reg & M_SYS_PCI_HOST)) {
223 sb1250_bus_status |= PCI_DEVICE_MODE;
227 (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
229 if (!(cmdreg & PCI_COMMAND_MASTER)) {
231 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
235 sb1250_bus_status |= PCI_BUS_ENABLED;
239 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
240 * space. Use "match bytes" policy to make everything look
241 * little-endian. So, you need to also set
242 * CONFIG_SWAP_IO_SPACE, but this is the combination that
243 * works correctly with most of Linux's drivers.
244 * XXX ehs: Should this happen in PCI Device mode?
247 set_io_port_base((unsigned long)
248 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
249 isa_slot_offset = (unsigned long)
250 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
252 #ifdef CONFIG_SIBYTE_HAS_LDT
254 * Also check the LDT bridge's enable, just in case we didn't
255 * initialize that one.
258 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
260 if (cmdreg & PCI_COMMAND_MASTER) {
261 sb1250_bus_status |= LDT_BUS_ENABLED;
264 * Need bits 23:16 to convey vector number. Note that
265 * this consumes 4MB of kernel-mapped memory
266 * (Kseg2/Kseg3) for 32-bit kernel.
268 ldt_eoi_space = (unsigned long)
269 ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES,
274 register_pci_controller(&sb1250_controller);
276 #ifdef CONFIG_VGA_CONSOLE
277 take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
281 arch_initcall(sb1250_pcibios_init);
283 struct pci_fixup pcibios_fixups[] = {