3 * arch/mips/vr41xx/common/pciu.c
5 * BRIEF MODULE DESCRIPTION
6 * PCI Control Unit routines for the NEC VR4100 series.
9 * yyuasa@mvista.com or source@mvista.com
11 * Copyright 2001-2003 MontaVista Software Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
26 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
27 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 * Paul Mundt <lethal@chaoticdreams.org>
36 * - Fix deadlock-causing PCIU access race for VR4131.
38 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
39 * - New creation, NEC VR4122 and VR4131 are supported.
41 #include <linux/config.h>
42 #include <linux/init.h>
43 #include <linux/pci.h>
44 #include <linux/types.h>
45 #include <linux/delay.h>
49 #include <asm/pci_channel.h>
50 #include <asm/vr41xx/vr41xx.h>
52 #include "pci-vr41xx.h"
54 static inline int vr41xx_pci_config_access(unsigned char bus,
55 unsigned int devfn, int where)
59 * Type 0 configuration
61 if (PCI_SLOT(devfn) < 11 || where > 255)
64 writel((1UL << PCI_SLOT(devfn)) |
65 (PCI_FUNC(devfn) << 8) |
66 (where & 0xfc), PCICONFAREG);
69 * Type 1 configuration
75 (devfn << 8) | (where & 0xfc) | 1UL, PCICONFAREG);
81 static int vr41xx_pci_config_read(struct pci_bus *bus, unsigned int devfn,
82 int where, int size, u32 * val)
87 if (vr41xx_pci_config_access(bus->number, devfn, where) < 0)
88 return PCIBIOS_DEVICE_NOT_FOUND;
90 data = readl(PCICONFDREG);
94 *val = (data >> ((where & 3) << 3)) & 0xffUL;
97 *val = (data >> ((where & 2) << 3)) & 0xffffUL;
103 return PCIBIOS_FUNC_NOT_SUPPORTED;
106 return PCIBIOS_SUCCESSFUL;
109 static int vr41xx_pci_config_write(struct pci_bus *bus, unsigned int devfn,
110 int where, int size, u32 val)
115 if (vr41xx_pci_config_access(bus->number, devfn, where) < 0)
116 return PCIBIOS_DEVICE_NOT_FOUND;
118 data = readl(PCICONFDREG);
122 shift = (where & 3) << 3;
123 data &= ~(0xff << shift);
124 data |= ((val & 0xff) << shift);
127 shift = (where & 2) << 3;
128 data &= ~(0xffff << shift);
129 data |= ((val & 0xffff) << shift);
135 return PCIBIOS_FUNC_NOT_SUPPORTED;
138 writel(data, PCICONFDREG);
140 return PCIBIOS_SUCCESSFUL;
143 struct pci_ops vr41xx_pci_ops = {
144 .read = vr41xx_pci_config_read,
145 .write = vr41xx_pci_config_write,
148 void __init vr41xx_pciu_init(struct vr41xx_pci_address_map *map)
150 struct vr41xx_pci_address_space *s;
151 unsigned long vtclock;
158 /* Disable PCI interrupt */
159 writew(0, MPCIINTREG);
161 /* Supply VTClock to PCIU */
162 vr41xx_supply_clock(PCIU_CLOCK);
165 * Sleep for 1us after setting MSKPPCIU bit in CMUCLKMSK
166 * before doing any PCIU access to avoid deadlock on VR4131.
170 /* Select PCI clock */
171 vtclock = vr41xx_get_vtclock_frequency();
172 if (vtclock < MAX_PCI_CLOCK)
173 writel(EQUAL_VTCLOCK, PCICLKSELREG);
174 else if ((vtclock / 2) < MAX_PCI_CLOCK)
175 writel(HALF_VTCLOCK, PCICLKSELREG);
176 else if ((vtclock / 4) < MAX_PCI_CLOCK)
177 writel(QUARTER_VTCLOCK, PCICLKSELREG);
179 printk(KERN_INFO "Warning: PCI Clock is over 33MHz.\n");
181 /* Supply PCI clock by PCI bus */
182 vr41xx_supply_clock(PCI_CLOCK);
185 * Set PCI memory & I/O space address conversion registers
186 * for master transaction.
188 if (map->mem1 != NULL) {
190 config = (s->internal_base & 0xff000000) |
191 ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) |
192 ((s->pci_base & 0xff000000) >> 24);
193 writel(config, PCIMMAW1REG);
195 if (map->mem2 != NULL) {
197 config = (s->internal_base & 0xff000000) |
198 ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) |
199 ((s->pci_base & 0xff000000) >> 24);
200 writel(config, PCIMMAW2REG);
202 if (map->io != NULL) {
204 config = (s->internal_base & 0xff000000) |
205 ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) |
206 ((s->pci_base & 0xff000000) >> 24);
207 writel(config, PCIMIOAWREG);
210 /* Set target memory windows */
211 writel(0x00081000, PCITAW1REG);
212 writel(0UL, PCITAW2REG);
213 pciu_write_config_dword(PCI_BASE_ADDRESS_0, 0UL);
214 pciu_write_config_dword(PCI_BASE_ADDRESS_1, 0UL);
216 /* Clear bus error */
217 n = readl(BUSERRADREG);
219 if (current_cpu_data.cputype == CPU_VR4122) {
220 writel(0UL, PCITRDYVREG);
221 pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x0000f804);
223 writel(100UL, PCITRDYVREG);
224 pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x00008004);
227 writel(CONFIG_DONE, PCIENREG);
228 pciu_write_config_dword(PCI_COMMAND,
232 PCI_COMMAND_PARITY | PCI_COMMAND_SERR);