2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
4 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 * Copyright (C) 1999 - 2001 Kanoj Sarcar
8 #include <linux/config.h>
9 #include <linux/init.h>
10 #include <linux/irq.h>
11 #include <linux/errno.h>
12 #include <linux/signal.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/timex.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/delay.h>
24 #include <asm/bitops.h>
25 #include <asm/bootinfo.h>
27 #include <asm/mipsregs.h>
28 #include <asm/system.h>
30 #include <asm/ptrace.h>
31 #include <asm/processor.h>
32 #include <asm/pci/bridge.h>
33 #include <asm/sn/addrs.h>
34 #include <asm/sn/agent.h>
35 #include <asm/sn/arch.h>
36 #include <asm/sn/hub.h>
37 #include <asm/sn/intr.h>
41 #define DBG(x...) printk(x)
47 * Linux has a controller-independent x86 interrupt architecture.
48 * every controller has a 'controller-template', that is used
49 * by the main code to do the right thing. Each driver-visible
50 * interrupt source is transparently wired to the apropriate
51 * controller. Thus drivers need not be aware of the
52 * interrupt-controller.
54 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
55 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
56 * (IO-APICs assumed to be messaging to Pentium local-APICs)
58 * the code is designed to be easily extended with new/different
59 * interrupt controllers, without having to do assembly magic.
62 extern asmlinkage void ip27_irq(void);
64 extern struct bridge_controller *irq_to_bridge[];
65 extern int irq_to_slot[];
68 * use these macros to get the encoded nasid and widget id
71 #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
72 #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
74 static inline int alloc_level(int cpu, int irq)
76 struct slice_data *si = cpu_data[cpu].data;
77 int level; /* pre-allocated entries */
79 level = find_first_zero_bit(si->irq_alloc_mask, LEVELS_PER_SLICE);
80 if (level >= LEVELS_PER_SLICE)
81 panic("Cpu %d flooded with devices\n", cpu);
83 __set_bit(level, si->irq_alloc_mask);
84 si->level_to_irq[level] = irq;
89 static inline int find_level(cpuid_t *cpunum, int irq)
93 for (cpu = 0; cpu <= NR_CPUS; cpu++) {
94 struct slice_data *si = cpu_data[cpu].data;
99 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
100 if (si->level_to_irq[i] == irq) {
107 panic("Could not identify cpu/level for irq %d\n", irq);
113 static int ms1bit(unsigned long x)
117 s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
118 s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s;
119 s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s;
120 s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s;
121 s = 1; if (x >> 1 == 0) s = 0; b += s;
127 * This code is unnecessarily complex, because we do SA_INTERRUPT
128 * intr enabling. Basically, once we grab the set of intrs we need
129 * to service, we must mask _all_ these interrupts; firstly, to make
130 * sure the same intr does not intr again, causing recursion that
131 * can lead to stack overflow. Secondly, we can not just mask the
132 * one intr we are do_IRQing, because the non-masked intrs in the
133 * first set might intr again, causing multiple servicings of the
134 * same intr. This effect is mostly seen for intercpu intrs.
138 void ip27_do_irq_mask0(struct pt_regs *regs)
141 hubreg_t pend0, mask0;
142 cpuid_t cpu = smp_processor_id();
144 (cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B;
146 /* copied from Irix intpend0() */
147 pend0 = LOCAL_HUB_L(PI_INT_PEND0);
148 mask0 = LOCAL_HUB_L(pi_int_mask0);
150 pend0 &= mask0; /* Pick intrs we should look at */
154 /* Prevent any of the picked intrs from recursing */
155 LOCAL_HUB_S(pi_int_mask0, mask0 & ~pend0);
157 swlevel = ms1bit(pend0);
159 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
160 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
161 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
162 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
163 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
164 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
165 smp_call_function_interrupt();
166 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
167 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
168 smp_call_function_interrupt();
172 /* "map" swlevel to irq */
173 struct slice_data *si = cpu_data[cpu].data;
175 irq = si->level_to_irq[swlevel];
179 /* clear bit in pend0 */
180 pend0 ^= 1UL << swlevel;
182 /* Now allow the set of serviced intrs again */
183 LOCAL_HUB_S(pi_int_mask0, mask0);
184 LOCAL_HUB_L(PI_INT_PEND0);
187 void ip27_do_irq_mask1(struct pt_regs *regs)
190 hubreg_t pend1, mask1;
191 cpuid_t cpu = smp_processor_id();
192 int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B;
193 struct slice_data *si = cpu_data[cpu].data;
195 /* copied from Irix intpend0() */
196 pend1 = LOCAL_HUB_L(PI_INT_PEND1);
197 mask1 = LOCAL_HUB_L(pi_int_mask1);
199 pend1 &= mask1; /* Pick intrs we should look at */
203 /* Prevent any of the picked intrs from recursing */
204 LOCAL_HUB_S(pi_int_mask1, mask1 & ~pend1);
206 swlevel = ms1bit(pend1);
207 /* "map" swlevel to irq */
208 irq = si->level_to_irq[swlevel];
209 LOCAL_HUB_CLR_INTR(swlevel);
211 /* clear bit in pend1 */
212 pend1 ^= 1UL << swlevel;
214 /* Now allow the set of serviced intrs again */
215 LOCAL_HUB_S(pi_int_mask1, mask1);
216 LOCAL_HUB_L(PI_INT_PEND1);
219 void ip27_prof_timer(struct pt_regs *regs)
221 panic("CPU %d got a profiling interrupt", smp_processor_id());
224 void ip27_hub_error(struct pt_regs *regs)
226 panic("CPU %d got a hub error interrupt", smp_processor_id());
229 static int intr_connect_level(int cpu, int bit)
231 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
232 struct slice_data *si = cpu_data[cpu].data;
234 __set_bit(bit, si->irq_enable_mask);
236 /* Make sure it's not already pending when we connect it. */
237 REMOTE_HUB_CLR_INTR(nasid, bit);
239 if (!cputoslice(cpu)) {
240 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
241 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
243 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
244 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
250 static int intr_disconnect_level(int cpu, int bit)
252 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
253 struct slice_data *si = cpu_data[cpu].data;
255 __clear_bit(bit, si->irq_enable_mask);
257 if (!cputoslice(cpu)) {
258 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
259 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
261 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
262 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
268 /* Startup one of the (PCI ...) IRQs routes over a bridge. */
269 static unsigned int startup_bridge_irq(unsigned int irq)
271 struct bridge_controller *bc;
276 pin = SLOT_FROM_PCI_IRQ(irq);
277 bc = IRQ_TO_BRIDGE(irq);
280 DBG("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin);
282 * "map" irq to a swlevel greater than 6 since the first 6 bits
283 * of INT_PEND0 are taken
285 swlevel = alloc_level(bc->irq_cpu, irq);
286 intr_connect_level(bc->irq_cpu, swlevel);
288 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
289 bridge->b_int_enable |= (1 << pin);
290 /* more stuff in int_enable reg */
291 bridge->b_int_enable |= 0x7ffffe00;
294 * Enable sending of an interrupt clear packt to the hub on a high to
295 * low transition of the interrupt pin.
297 * IRIX sets additional bits in the address which are documented as
298 * reserved in the bridge docs.
300 bridge->b_int_mode |= (1UL << pin);
303 * We assume the bridge to have a 1:1 mapping between devices
304 * (slots) and intr pins.
306 device = bridge->b_int_device;
307 device &= ~(7 << (pin*3));
308 device |= (pin << (pin*3));
309 bridge->b_int_device = device;
311 bridge->b_widget.w_tflush; /* Flush */
313 return 0; /* Never anything pending. */
316 /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
317 static void shutdown_bridge_irq(unsigned int irq)
319 struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
320 bridge_t *bridge = bc->base;
321 struct slice_data *si = cpu_data[bc->irq_cpu].data;
325 DBG("bridge_shutdown: irq 0x%x\n", irq);
326 pin = SLOT_FROM_PCI_IRQ(irq);
329 * map irq to a swlevel greater than 6 since the first 6 bits
330 * of INT_PEND0 are taken
332 swlevel = find_level(&cpu, irq);
333 intr_disconnect_level(cpu, swlevel);
335 __clear_bit(swlevel, si->irq_alloc_mask);
336 si->level_to_irq[swlevel] = -1;
338 bridge->b_int_enable &= ~(1 << pin);
339 bridge->b_widget.w_tflush; /* Flush */
342 static inline void enable_bridge_irq(unsigned int irq)
344 /* All the braindamage happens magically for us in ip27_do_irq */
347 static void disable_bridge_irq(unsigned int irq)
349 /* All the braindamage happens magically for us in ip27_do_irq */
352 static void mask_and_ack_bridge_irq(unsigned int irq)
354 /* All the braindamage happens magically for us in ip27_do_irq */
357 static void end_bridge_irq(unsigned int irq)
361 static struct hw_interrupt_type bridge_irq_type = {
362 .typename = "bridge",
363 .startup = startup_bridge_irq,
364 .shutdown = shutdown_bridge_irq,
365 .enable = enable_bridge_irq,
366 .disable = disable_bridge_irq,
367 .ack = mask_and_ack_bridge_irq,
368 .end = end_bridge_irq,
371 static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
373 unsigned int allocate_irqno(void)
378 irq = find_first_zero_bit(irq_map, LEVELS_PER_SLICE);
383 if (test_and_set_bit(irq, irq_map))
389 void free_irqno(unsigned int irq)
391 clear_bit(irq, irq_map);
394 void __init init_IRQ(void)
398 set_except_vector(0, ip27_irq);
401 * Right now the bridge irq is our kitchen sink interrupt type
403 for (i = 0; i <= NR_IRQS; i++) {
404 irq_desc[i].status = IRQ_DISABLED;
405 irq_desc[i].action = 0;
406 irq_desc[i].depth = 1;
407 irq_desc[i].handler = &bridge_irq_type;
411 void install_ipi(void)
413 int slice = LOCAL_HUB_L(PI_CPU_NUM);
414 int cpu = smp_processor_id();
415 struct slice_data *si = cpu_data[cpu].data;
419 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
420 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
421 mask = LOCAL_HUB_L(PI_INT_MASK0_A); /* Slice A */
422 set = (1UL << CPU_RESCHED_A_IRQ) | (1UL << CPU_CALL_A_IRQ);
424 si->irq_enable_mask[0] |= set;
425 si->irq_alloc_mask[0] |= set;
426 LOCAL_HUB_S(PI_INT_MASK0_A, mask);
428 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
429 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
430 mask = LOCAL_HUB_L(PI_INT_MASK0_B); /* Slice B */
431 set = (1UL << CPU_RESCHED_B_IRQ) | (1UL << CPU_CALL_B_IRQ);
433 si->irq_enable_mask[1] |= set;
434 si->irq_alloc_mask[1] |= set;
435 LOCAL_HUB_S(PI_INT_MASK0_B, mask);