2 * Code to handle IP32 IRQs
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2001 Keith M Wesolowski
11 #include <linux/init.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/bitops.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
20 #include <linux/random.h>
21 #include <linux/sched.h>
23 #include <asm/bitops.h>
24 #include <asm/mipsregs.h>
25 #include <asm/signal.h>
26 #include <asm/system.h>
28 #include <asm/ip32/crime.h>
29 #include <asm/ip32/mace.h>
30 #include <asm/ip32/ip32_ints.h>
32 /* issue a PIO read to make sure no PIO writes are pending */
33 #define flush_crime_bus() crime_read(CRIME_CONTROL);
34 static void inline flush_mace_bus(void)
36 volatile unsigned long junk = mace_perif_ctrl_read(misc);
41 #define DBG(x...) printk(x)
48 * IP0 -> software (ignored)
49 * IP1 -> software (ignored)
50 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
51 * IP3 -> (irq1) X unknown
52 * IP4 -> (irq2) X unknown
53 * IP5 -> (irq3) X unknown
54 * IP6 -> (irq4) X unknown
55 * IP7 -> (irq5) 0 CPU count/compare timer (system timer)
59 * CRIME_INT_STAT 31:0:
64 * 3 -> 4 Mace ethernet
65 * 4 -> S SuperIO sub-interrupt
66 * 5 -> M Miscellaneous sub-interrupt
67 * 6 -> A Audio sub-interrupt
68 * 7 -> 8 PCI bridge errors
69 * 8 -> 9 PCI SCSI aic7xxx 0
70 * 9 -> 10 PCI SCSI aic7xxx 1
72 * 11 -> 12 unused (PCI slot 1)
73 * 12 -> 13 unused (PCI slot 2)
74 * 13 -> 14 unused (PCI shared 0)
75 * 14 -> 15 unused (PCI shared 1)
76 * 15 -> 16 unused (PCI shared 2)
82 * 21 -> 22 Memory errors
83 * 22 -> 23 RE empty edge (E)
84 * 23 -> 24 RE full edge (E)
85 * 24 -> 25 RE idle edge (E)
86 * 25 -> 26 RE empty level
87 * 26 -> 27 RE full level
88 * 27 -> 28 RE idle level
89 * 28 -> 29 unused (software 0) (E)
90 * 29 -> 30 unused (software 1) (E)
91 * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
94 * S, M, A: Use the MACE ISA interrupt register
95 * MACE_ISA_INT_STAT 31:0
100 * 10 -> X Keyboard polled
102 * 12 -> X Mouse polled
103 * 13-15 -> 46-48 Count/compare timers
104 * 16-19 -> 49-52 Parallel (16 E)
105 * 20-25 -> 53-58 Serial 1 (22 E)
106 * 26-31 -> 59-64 Serial 2 (28 E)
108 * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
109 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
110 * is quite different anyway.
114 * IRQ spinlock - Ralf says not to disable CPU interrupts,
115 * and I think he knows better.
117 static spinlock_t ip32_irq_lock = SPIN_LOCK_UNLOCKED;
119 /* Some initial interrupts to set up */
120 extern irqreturn_t crime_memerr_intr (int irq, void *dev_id,
121 struct pt_regs *regs);
122 extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id,
123 struct pt_regs *regs);
125 struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT,
126 CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
127 struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT,
128 CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
130 extern void ip32_handle_int(void);
133 * For interrupts wired from a single device to the CPU. Only the clock
134 * uses this it seems, which is IRQ 0 and IP7.
137 static void enable_cpu_irq(unsigned int irq)
139 set_c0_status(STATUSF_IP7);
142 static unsigned int startup_cpu_irq(unsigned int irq)
148 static void disable_cpu_irq(unsigned int irq)
150 clear_c0_status(STATUSF_IP7);
153 static void end_cpu_irq(unsigned int irq)
155 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
156 enable_cpu_irq (irq);
159 #define shutdown_cpu_irq disable_cpu_irq
160 #define mask_and_ack_cpu_irq disable_cpu_irq
162 static struct hw_interrupt_type ip32_cpu_interrupt = {
168 mask_and_ack_cpu_irq,
174 * This is for pure CRIME interrupts - ie not MACE. The advantage?
175 * We get to split the register in half and do faster lookups.
178 static uint64_t crime_mask;
180 static void enable_crime_irq(unsigned int irq)
184 spin_lock_irqsave(&ip32_irq_lock, flags);
185 crime_mask |= 1 << (irq - 1);
186 crime_write(crime_mask, CRIME_INT_MASK);
187 spin_unlock_irqrestore(&ip32_irq_lock, flags);
190 static unsigned int startup_crime_irq(unsigned int irq)
192 enable_crime_irq(irq);
193 return 0; /* This is probably not right; we could have pending irqs */
196 static void disable_crime_irq(unsigned int irq)
200 spin_lock_irqsave(&ip32_irq_lock, flags);
201 crime_mask &= ~(1 << (irq - 1));
202 crime_write(crime_mask, CRIME_INT_MASK);
204 spin_unlock_irqrestore(&ip32_irq_lock, flags);
207 static void mask_and_ack_crime_irq(unsigned int irq)
211 /* Edge triggered interrupts must be cleared. */
212 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
213 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
214 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
216 spin_lock_irqsave(&ip32_irq_lock, flags);
217 crime_int = crime_read(CRIME_HARD_INT);
218 crime_int &= ~(1 << (irq - 1));
219 crime_write(crime_int, CRIME_HARD_INT);
220 spin_unlock_irqrestore(&ip32_irq_lock, flags);
222 disable_crime_irq(irq);
225 static void end_crime_irq(unsigned int irq)
227 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
228 enable_crime_irq(irq);
231 #define shutdown_crime_irq disable_crime_irq
233 static struct hw_interrupt_type ip32_crime_interrupt = {
239 mask_and_ack_crime_irq,
245 * This is for MACE PCI interrupts. We can decrease bus traffic by masking
246 * as close to the source as possible. This also means we can take the
247 * next chunk of the CRIME register in one piece.
250 static unsigned long macepci_mask;
252 static void enable_macepci_irq(unsigned int irq)
256 spin_lock_irqsave(&ip32_irq_lock, flags);
257 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
258 mace->pci.control = macepci_mask;
259 crime_mask |= 1 << (irq - 1);
260 crime_write(crime_mask, CRIME_INT_MASK);
261 spin_unlock_irqrestore(&ip32_irq_lock, flags);
264 static unsigned int startup_macepci_irq(unsigned int irq)
266 enable_macepci_irq (irq);
270 static void disable_macepci_irq(unsigned int irq)
274 spin_lock_irqsave(&ip32_irq_lock, flags);
275 crime_mask &= ~(1 << (irq - 1));
276 crime_write(crime_mask, CRIME_INT_MASK);
278 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
279 mace->pci.control = macepci_mask;
281 spin_unlock_irqrestore(&ip32_irq_lock, flags);
284 static void end_macepci_irq(unsigned int irq)
286 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
287 enable_macepci_irq(irq);
290 #define shutdown_macepci_irq disable_macepci_irq
291 #define mask_and_ack_macepci_irq disable_macepci_irq
293 static struct hw_interrupt_type ip32_macepci_interrupt = {
296 shutdown_macepci_irq,
299 mask_and_ack_macepci_irq,
304 /* This is used for MACE ISA interrupts. That means bits 4-6 in the
308 #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \
309 MACEISA_AUDIO_SC_INT | \
310 MACEISA_AUDIO1_DMAT_INT | \
311 MACEISA_AUDIO1_OF_INT | \
312 MACEISA_AUDIO2_DMAT_INT | \
313 MACEISA_AUDIO2_MERR_INT | \
314 MACEISA_AUDIO3_DMAT_INT | \
315 MACEISA_AUDIO3_MERR_INT)
316 #define MACEISA_MISC_INT (MACEISA_RTC_INT | \
318 MACEISA_KEYB_POLL_INT | \
319 MACEISA_MOUSE_INT | \
320 MACEISA_MOUSE_POLL_INT | \
321 MACEISA_TIMER0_INT | \
322 MACEISA_TIMER1_INT | \
324 #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \
325 MACEISA_PAR_CTXA_INT | \
326 MACEISA_PAR_CTXB_INT | \
327 MACEISA_PAR_MERR_INT | \
328 MACEISA_SERIAL1_INT | \
329 MACEISA_SERIAL1_TDMAT_INT | \
330 MACEISA_SERIAL1_TDMAPR_INT | \
331 MACEISA_SERIAL1_TDMAME_INT | \
332 MACEISA_SERIAL1_RDMAT_INT | \
333 MACEISA_SERIAL1_RDMAOR_INT | \
334 MACEISA_SERIAL2_INT | \
335 MACEISA_SERIAL2_TDMAT_INT | \
336 MACEISA_SERIAL2_TDMAPR_INT | \
337 MACEISA_SERIAL2_TDMAME_INT | \
338 MACEISA_SERIAL2_RDMAT_INT | \
339 MACEISA_SERIAL2_RDMAOR_INT)
341 static unsigned long maceisa_mask;
343 static void enable_maceisa_irq (unsigned int irq)
345 unsigned int crime_int = 0;
348 DBG ("maceisa enable: %u\n", irq);
351 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
352 crime_int = MACE_AUDIO_INT;
354 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
355 crime_int = MACE_MISC_INT;
357 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
358 crime_int = MACE_SUPERIO_INT;
361 DBG ("crime_int %08x enabled\n", crime_int);
362 spin_lock_irqsave(&ip32_irq_lock, flags);
363 crime_mask |= crime_int;
364 crime_write(crime_mask, CRIME_INT_MASK);
365 maceisa_mask |= 1 << (irq - 33);
366 mace_perif_ctrl_write(maceisa_mask, imask);
367 spin_unlock_irqrestore(&ip32_irq_lock, flags);
370 static unsigned int startup_maceisa_irq(unsigned int irq)
372 enable_maceisa_irq(irq);
376 static void disable_maceisa_irq(unsigned int irq)
378 unsigned int crime_int = 0;
381 spin_lock_irqsave(&ip32_irq_lock, flags);
382 maceisa_mask &= ~(1 << (irq - 33));
383 if(!(maceisa_mask & MACEISA_AUDIO_INT))
384 crime_int |= MACE_AUDIO_INT;
385 if(!(maceisa_mask & MACEISA_MISC_INT))
386 crime_int |= MACE_MISC_INT;
387 if(!(maceisa_mask & MACEISA_SUPERIO_INT))
388 crime_int |= MACE_SUPERIO_INT;
389 crime_mask &= ~crime_int;
390 crime_write(crime_mask, CRIME_INT_MASK);
392 mace_perif_ctrl_write(maceisa_mask, imask);
394 spin_unlock_irqrestore(&ip32_irq_lock, flags);
397 static void mask_and_ack_maceisa_irq(unsigned int irq)
399 unsigned long mace_int, flags;
402 case MACEISA_PARALLEL_IRQ:
403 case MACEISA_SERIAL1_TDMAPR_IRQ:
404 case MACEISA_SERIAL2_TDMAPR_IRQ:
406 spin_lock_irqsave(&ip32_irq_lock, flags);
407 mace_int = mace_perif_ctrl_read(istat);
408 mace_int &= ~(1 << (irq - 33));
409 mace_perif_ctrl_write(mace_int, istat);
410 spin_unlock_irqrestore(&ip32_irq_lock, flags);
413 disable_maceisa_irq(irq);
416 static void end_maceisa_irq(unsigned irq)
418 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
419 enable_maceisa_irq(irq);
422 #define shutdown_maceisa_irq disable_maceisa_irq
424 static struct hw_interrupt_type ip32_maceisa_interrupt = {
427 shutdown_maceisa_irq,
430 mask_and_ack_maceisa_irq,
435 /* This is used for regular non-ISA, non-PCI MACE interrupts. That means
436 * bits 0-3 and 7 in the CRIME register.
439 static void enable_mace_irq(unsigned int irq)
443 spin_lock_irqsave(&ip32_irq_lock, flags);
444 crime_mask |= 1 << (irq - 1);
445 crime_write(crime_mask, CRIME_INT_MASK);
446 spin_unlock_irqrestore(&ip32_irq_lock, flags);
449 static unsigned int startup_mace_irq(unsigned int irq)
451 enable_mace_irq(irq);
455 static void disable_mace_irq(unsigned int irq)
459 spin_lock_irqsave(&ip32_irq_lock, flags);
460 crime_mask &= ~(1 << (irq - 1));
461 crime_write(crime_mask, CRIME_INT_MASK);
463 spin_unlock_irqrestore(&ip32_irq_lock, flags);
466 static void end_mace_irq(unsigned int irq)
468 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
469 enable_mace_irq(irq);
472 #define shutdown_mace_irq disable_mace_irq
473 #define mask_and_ack_mace_irq disable_mace_irq
475 static struct hw_interrupt_type ip32_mace_interrupt = {
481 mask_and_ack_mace_irq,
486 static void ip32_unknown_interrupt(struct pt_regs *regs)
490 printk ("Unknown interrupt occurred!\n");
491 printk ("cp0_status: %08x\n", read_c0_status());
492 printk ("cp0_cause: %08x\n", read_c0_cause());
493 crime = crime_read(CRIME_INT_MASK);
494 printk ("CRIME intr mask: %016lx\n", crime);
495 crime = crime_read(CRIME_INT_STAT);
496 printk ("CRIME intr status: %016lx\n", crime);
497 crime = crime_read(CRIME_HARD_INT);
498 printk ("CRIME hardware intr register: %016lx\n", crime);
499 printk ("MACE ISA intr mask: %08lx\n", mace_perif_ctrl_read(imask));
500 printk ("MACE ISA intr status: %08lx\n", mace_perif_ctrl_read(istat));
501 printk ("MACE PCI control register: %08x\n", mace->pci.control);
503 printk("Register dump:\n");
506 printk("Please mail this report to linux-mips@linux-mips.org\n");
507 printk("Spinning...");
511 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */
512 /* change this to loop over all edge-triggered irqs, exception masked out ones */
513 void ip32_irq0(struct pt_regs *regs)
518 crime_int = crime_read(CRIME_INT_STAT) & crime_mask;
519 irq = ffs(crime_int);
520 crime_int = 1 << (irq - 1);
522 if (crime_int & CRIME_MACEISA_INT_MASK) {
523 unsigned long mace_int = mace_perif_ctrl_read(istat);
524 irq = ffs(mace_int & maceisa_mask) + 32;
526 DBG("*irq %u*\n", irq);
530 void ip32_irq1(struct pt_regs *regs)
532 ip32_unknown_interrupt(regs);
535 void ip32_irq2(struct pt_regs *regs)
537 ip32_unknown_interrupt(regs);
540 void ip32_irq3(struct pt_regs *regs)
542 ip32_unknown_interrupt(regs);
545 void ip32_irq4(struct pt_regs *regs)
547 ip32_unknown_interrupt(regs);
550 void ip32_irq5(struct pt_regs *regs)
552 ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs);
555 void __init init_IRQ(void)
560 /* Install our interrupt handler, then clear and disable all
561 * CRIME and MACE interrupts. */
562 crime_write(0, CRIME_INT_MASK);
563 crime_write(0, CRIME_HARD_INT);
564 crime_write(0, CRIME_SOFT_INT);
565 mace_perif_ctrl_write(0, istat);
566 mace_perif_ctrl_write(0, imask);
567 set_except_vector(0, ip32_handle_int);
569 for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
570 hw_irq_controller *controller;
572 if (irq == IP32_R4K_TIMER_IRQ)
573 controller = &ip32_cpu_interrupt;
574 else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
575 controller = &ip32_mace_interrupt;
576 else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
577 controller = &ip32_macepci_interrupt;
578 else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
579 controller = &ip32_crime_interrupt;
581 controller = &ip32_maceisa_interrupt;
583 irq_desc[irq].status = IRQ_DISABLED;
584 irq_desc[irq].action = 0;
585 irq_desc[irq].depth = 0;
586 irq_desc[irq].handler = controller;
588 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
589 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
591 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
592 change_c0_status(ST0_IM, ALLINTS);