2 * cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
4 * Copyright (C) 2001-2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copuright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
25 * - New creation, NEC VR4122 and VR4131 are supported.
26 * - Added support for NEC VR4111 and VR4121.
28 * Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
29 * - Added support for NEC VR4133.
31 #include <linux/init.h>
32 #include <linux/smp.h>
33 #include <linux/spinlock.h>
34 #include <linux/types.h>
38 #include <asm/vr41xx/vr41xx.h>
40 #define CMUCLKMSK_TYPE1 KSEG1ADDR(0x0b000060)
41 #define CMUCLKMSK_TYPE2 KSEG1ADDR(0x0f000060)
47 #define MSKDSIU 0x0820
49 #define MSKPCIU 0x0080
50 #define MSKSSIU 0x0100
51 #define MSKSHSP 0x0200
52 #define MSKFFIR 0x0400
53 #define MSKSCSI 0x1000
54 #define MSKPPCIU 0x2000
55 #define CMUCLKMSK2 KSEG1ADDR(0x0f000064)
57 #define MSKMAC0 0x0002
58 #define MSKMAC1 0x0004
60 static uint32_t cmu_base;
61 static uint16_t cmuclkmsk, cmuclkmsk2;
62 static spinlock_t cmu_lock;
64 #define read_cmuclkmsk() readw(cmu_base)
65 #define read_cmuclkmsk2() readw(CMUCLKMSK2)
66 #define write_cmuclkmsk() writew(cmuclkmsk, cmu_base)
67 #define write_cmuclkmsk2() writew(cmuclkmsk2, CMUCLKMSK2)
69 void vr41xx_supply_clock(vr41xx_clock_t clock)
71 spin_lock_irq(&cmu_lock);
78 cmuclkmsk |= MSKSIU | MSKSSIU;
87 cmuclkmsk |= MSKFIR | MSKFFIR;
90 if (current_cpu_data.cputype == CPU_VR4111 ||
91 current_cpu_data.cputype == CPU_VR4121)
94 cmuclkmsk |= MSKSIU | MSKDSIU;
97 cmuclkmsk |= MSKCSI | MSKSCSI;
100 cmuclkmsk |= MSKPCIU;
103 cmuclkmsk |= MSKSHSP;
106 cmuclkmsk |= MSKPPCIU;
109 cmuclkmsk2 |= MSKCEU;
112 cmuclkmsk2 |= MSKMAC0;
115 cmuclkmsk2 |= MSKMAC1;
121 if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
122 clock == ETHER1_CLOCK)
127 spin_unlock_irq(&cmu_lock);
130 void vr41xx_mask_clock(vr41xx_clock_t clock)
132 spin_lock_irq(&cmu_lock);
136 cmuclkmsk &= ~MSKPIU;
139 if (current_cpu_data.cputype == CPU_VR4111 ||
140 current_cpu_data.cputype == CPU_VR4121) {
141 cmuclkmsk &= ~(MSKSIU | MSKSSIU);
143 if (cmuclkmsk & MSKDSIU)
144 cmuclkmsk &= ~MSKSSIU;
146 cmuclkmsk &= ~(MSKSIU | MSKSSIU);
150 cmuclkmsk &= ~MSKAIU;
153 cmuclkmsk &= ~MSKKIU;
156 cmuclkmsk &= ~(MSKFIR | MSKFFIR);
159 if (current_cpu_data.cputype == CPU_VR4111 ||
160 current_cpu_data.cputype == CPU_VR4121) {
161 cmuclkmsk &= ~MSKDSIU;
163 if (cmuclkmsk & MSKSIU)
164 cmuclkmsk &= ~MSKDSIU;
166 cmuclkmsk &= ~(MSKSIU | MSKDSIU);
170 cmuclkmsk &= ~(MSKCSI | MSKSCSI);
173 cmuclkmsk &= ~MSKPCIU;
176 cmuclkmsk &= ~MSKSHSP;
179 cmuclkmsk &= ~MSKPPCIU;
182 cmuclkmsk2 &= ~MSKCEU;
185 cmuclkmsk2 &= ~MSKMAC0;
188 cmuclkmsk2 &= ~MSKMAC1;
194 if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
195 clock == ETHER1_CLOCK)
200 spin_unlock_irq(&cmu_lock);
203 static int __init vr41xx_cmu_init(void)
205 switch (current_cpu_data.cputype) {
208 cmu_base = CMUCLKMSK_TYPE1;
212 cmu_base = CMUCLKMSK_TYPE2;
215 cmu_base = CMUCLKMSK_TYPE2;
216 cmuclkmsk2 = read_cmuclkmsk2();
219 panic("Unexpected CPU of NEC VR4100 series");
223 cmuclkmsk = read_cmuclkmsk();
225 spin_lock_init(&cmu_lock);
230 early_initcall(vr41xx_cmu_init);