arch/parisc/kernel/cache.c

   1 /* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1999 Helge Deller (07-13-1999)
   8  * Copyright (C) 1999 SuSE GmbH Nuernberg
   9  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
  10  *
  11  * Cache and TLB management
  12  *
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/pagemap.h>
  21
  22 #include <asm/pdc.h>
  23 #include <asm/cache.h>
  24 #include <asm/cacheflush.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/system.h>
  27 #include <asm/page.h>
  28 #include <asm/pgalloc.h>
  29 #include <asm/processor.h>
  30
  31 int split_tlb;
  32 int dcache_stride;
  33 int icache_stride;
  34 EXPORT_SYMBOL(dcache_stride);
  35
  36
  37 #if defined(CONFIG_SMP)
  38 /* On some machines (e.g. ones with the Merced bus), there can be
  39  * only a single PxTLB broadcast at a time; this must be guaranteed
  40  * by software.  We put a spinlock around all TLB flushes  to
  41  * ensure this.
  42  */
  43 spinlock_t pa_tlb_lock = SPIN_LOCK_UNLOCKED;
  44 EXPORT_SYMBOL(pa_tlb_lock);
  45 #endif
  46
  47 struct pdc_cache_info cache_info;
  48 #ifndef CONFIG_PA20
  49 static struct pdc_btlb_info btlb_info;
  50 #endif
  51
  52 #ifdef CONFIG_SMP
  53 void
  54 flush_data_cache(void)
  55 {
  56         on_each_cpu((void (*)(void *))flush_data_cache_local, NULL, 1, 1);
  57 }
  58 #endif
  59
  60 void
  61 flush_cache_all_local(void)
  62 {
  63         flush_instruction_cache_local();
  64         flush_data_cache_local();
  65 }
  66 EXPORT_SYMBOL(flush_cache_all_local);
  67
  68 /* flushes EVERYTHING (tlb & cache) */
  69
  70 void
  71 flush_all_caches(void)
  72 {
  73         flush_cache_all();
  74         flush_tlb_all();
  75 }
  76 EXPORT_SYMBOL(flush_all_caches);
  77
  78 void
  79 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  80 {
  81         struct page *page = pte_page(pte);
  82
  83         if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
  84             test_bit(PG_dcache_dirty, &page->flags)) {
  85
  86                 flush_kernel_dcache_page(page_address(page));
  87                 clear_bit(PG_dcache_dirty, &page->flags);
  88         }
  89 }
  90
  91 void
  92 show_cache_info(struct seq_file *m)
  93 {
  94         seq_printf(m, "I-cache\t\t: %ld KB\n",
  95                 cache_info.ic_size/1024 );
  96         seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %d-way associative)\n",
  97                 cache_info.dc_size/1024,
  98                 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
  99                 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
 100                 (cache_info.dc_conf.cc_assoc)
 101         );
 102
 103         seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
 104                 cache_info.it_size,
 105                 cache_info.dt_size,
 106                 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
 107         );
 108
 109 #ifndef CONFIG_PA20
 110         /* BTLB - Block TLB */
 111         if (btlb_info.max_size==0) {
 112                 seq_printf(m, "BTLB\t\t: not supported\n" );
 113         } else {
 114                 seq_printf(m,
 115                 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 116                 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 117                 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 118                 btlb_info.max_size, (int)4096,
 119                 btlb_info.max_size>>8,
 120                 btlb_info.fixed_range_info.num_i,
 121                 btlb_info.fixed_range_info.num_d,
 122                 btlb_info.fixed_range_info.num_comb,
 123                 btlb_info.variable_range_info.num_i,
 124                 btlb_info.variable_range_info.num_d,
 125                 btlb_info.variable_range_info.num_comb
 126                 );
 127         }
 128 #endif
 129 }
 130
 131 void __init
 132 parisc_cache_init(void)
 133 {
 134         if (pdc_cache_info(&cache_info) < 0)
 135                 panic("parisc_cache_init: pdc_cache_info failed");
 136
 137 #if 0
 138         printk("ic_size %lx dc_size %lx it_size %lx\n",
 139                 cache_info.ic_size,
 140                 cache_info.dc_size,
 141                 cache_info.it_size);
 142
 143         printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 144                 cache_info.dc_base,
 145                 cache_info.dc_stride,
 146                 cache_info.dc_count,
 147                 cache_info.dc_loop);
 148
 149         printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 150                 *(unsigned long *) (&cache_info.dc_conf),
 151                 cache_info.dc_conf.cc_alias,
 152                 cache_info.dc_conf.cc_block,
 153                 cache_info.dc_conf.cc_line,
 154                 cache_info.dc_conf.cc_shift);
 155         printk("        wt %d sh %d cst %d assoc %d\n",
 156                 cache_info.dc_conf.cc_wt,
 157                 cache_info.dc_conf.cc_sh,
 158                 cache_info.dc_conf.cc_cst,
 159                 cache_info.dc_conf.cc_assoc);
 160
 161         printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 162                 cache_info.ic_base,
 163                 cache_info.ic_stride,
 164                 cache_info.ic_count,
 165                 cache_info.ic_loop);
 166
 167         printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 168                 *(unsigned long *) (&cache_info.ic_conf),
 169                 cache_info.ic_conf.cc_alias,
 170                 cache_info.ic_conf.cc_block,
 171                 cache_info.ic_conf.cc_line,
 172                 cache_info.ic_conf.cc_shift);
 173         printk("        wt %d sh %d cst %d assoc %d\n",
 174                 cache_info.ic_conf.cc_wt,
 175                 cache_info.ic_conf.cc_sh,
 176                 cache_info.ic_conf.cc_cst,
 177                 cache_info.ic_conf.cc_assoc);
 178
 179         printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 180                 cache_info.dt_conf.tc_sh,
 181                 cache_info.dt_conf.tc_page,
 182                 cache_info.dt_conf.tc_cst,
 183                 cache_info.dt_conf.tc_aid,
 184                 cache_info.dt_conf.tc_pad1);
 185
 186         printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 187                 cache_info.it_conf.tc_sh,
 188                 cache_info.it_conf.tc_page,
 189                 cache_info.it_conf.tc_cst,
 190                 cache_info.it_conf.tc_aid,
 191                 cache_info.it_conf.tc_pad1);
 192 #endif
 193
 194         split_tlb = 0;
 195         if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 196                 if (cache_info.dt_conf.tc_sh == 2)
 197                         printk(KERN_WARNING "Unexpected TLB configuration. "
 198                         "Will flush I/D separately (could be optimized).\n");
 199
 200                 split_tlb = 1;
 201         }
 202
 203         /* "New and Improved" version from Jim Hull
 204          *      (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
 205          */
 206 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
 207         dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
 208         icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 209 #undef CAFL_STRIDE
 210
 211 #ifndef CONFIG_PA20
 212         if (pdc_btlb_info(&btlb_info) < 0) {
 213                 memset(&btlb_info, 0, sizeof btlb_info);
 214         }
 215 #endif
 216
 217         if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 218                                                 PDC_MODEL_NVA_UNSUPPORTED) {
 219                 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
 220 #if 0
 221                 panic("SMP kernel required to avoid non-equivalent aliasing");
 222 #endif
 223         }
 224 }
 225
 226 void disable_sr_hashing(void)
 227 {
 228         int srhash_type;
 229
 230         switch (boot_cpu_data.cpu_type) {
 231         case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 232                 BUG();
 233                 return;
 234
 235         case pcxs:
 236         case pcxt:
 237         case pcxt_:
 238                 srhash_type = SRHASH_PCXST;
 239                 break;
 240
 241         case pcxl:
 242                 srhash_type = SRHASH_PCXL;
 243                 break;
 244
 245         case pcxl2: /* pcxl2 doesn't support space register hashing */
 246                 return;
 247
 248         default: /* Currently all PA2.0 machines use the same ins. sequence */
 249                 srhash_type = SRHASH_PA20;
 250                 break;
 251         }
 252
 253         disable_sr_hashing_asm(srhash_type);
 254 }
 255
 256 void flush_dcache_page(struct page *page)
 257 {
 258         struct address_space *mapping = page_mapping(page);
 259         struct vm_area_struct *mpnt;
 260         struct prio_tree_iter iter;
 261         unsigned long offset;
 262         unsigned long addr;
 263         pgoff_t pgoff;
 264         pte_t *pte;
 265         unsigned long pfn = page_to_pfn(page);
 266
 267
 268         if (mapping && !mapping_mapped(mapping)) {
 269                 set_bit(PG_dcache_dirty, &page->flags);
 270                 return;
 271         }
 272
 273         flush_kernel_dcache_page(page_address(page));
 274
 275         if (!mapping)
 276                 return;
 277
 278         pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 279
 280         /* We have carefully arranged in arch_get_unmapped_area() that
 281          * *any* mappings of a file are always congruently mapped (whether
 282          * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 283          * to flush one address here for them all to become coherent */
 284
 285         flush_dcache_mmap_lock(mapping);
 286         vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
 287                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 288                 addr = mpnt->vm_start + offset;
 289
 290                 /* Flush instructions produce non access tlb misses.
 291                  * On PA, we nullify these instructions rather than
 292                  * taking a page fault if the pte doesn't exist.
 293                  * This is just for speed.  If the page translation
 294                  * isn't there, there's no point exciting the
 295                  * nadtlb handler into a nullification frenzy */
 296
 297
 298                 if(!(pte = translation_exists(mpnt, addr)))
 299                         continue;
 300
 301                 /* make sure we really have this page: the private
 302                  * mappings may cover this area but have COW'd this
 303                  * particular page */
 304                 if(pte_pfn(*pte) != pfn)
 305                         continue;
 306
 307                 __flush_cache_page(mpnt, addr);
 308
 309                 break;
 310         }
 311         flush_dcache_mmap_unlock(mapping);
 312 }
 313 EXPORT_SYMBOL(flush_dcache_page);
 314
 315 /* Defined in arch/parisc/kernel/pacache.S */
 316 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 317 EXPORT_SYMBOL(flush_kernel_dcache_page);
 318 EXPORT_SYMBOL(flush_data_cache_local);
 319 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
 320
 321 void clear_user_page_asm(void *page, unsigned long vaddr)
 322 {
 323         /* This function is implemented in assembly in pacache.S */
 324         extern void __clear_user_page_asm(void *page, unsigned long vaddr);
 325
 326         purge_tlb_start();
 327         __clear_user_page_asm(page, vaddr);
 328         purge_tlb_end();
 329 }