2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/config.h>
26 #include <asm/offsets.h>
28 /* we have the following possibilities to act on an interruption:
29 * - handle in assembly and use shadowed registers only
30 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/assembly.h> /* for LDREG/STREG defines */
34 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
38 #include <asm/thread_info.h>
54 .import pa_dbit_lock,data
56 /* space_to_prot macro creates a prot id from a space id */
58 #if (SPACEID_SHIFT) == 0
59 .macro space_to_prot spc prot
60 depd,z \spc,62,31,\prot
63 .macro space_to_prot spc prot
64 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
68 /* Switch to virtual mapping, trashing only %r1 */
73 or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
79 ldil L%KERNEL_PSW, %r1
80 ldo R%KERNEL_PSW(%r1), %r1
82 mtctl %r0, %cr17 /* Clear IIASQ tail */
83 mtctl %r0, %cr17 /* Clear IIASQ head */
86 mtctl %r1, %cr18 /* Set IIAOQ tail */
88 mtctl %r1, %cr18 /* Set IIAOQ head */
95 * The "get_stack" macros are responsible for determining the
100 * Already using a kernel stack, so call the
101 * get_stack_use_r30 macro to push a pt_regs structure
102 * on the stack, and store registers there.
104 * Need to set up a kernel stack, so call the
105 * get_stack_use_cr30 macro to set up a pointer
106 * to the pt_regs structure contained within the
107 * task pointer pointed to by cr30. Set the stack
108 * pointer to point to the end of the task structure.
112 * Already using a kernel stack, check to see if r30
113 * is already pointing to the per processor interrupt
114 * stack. If it is, call the get_stack_use_r30 macro
115 * to push a pt_regs structure on the stack, and store
116 * registers there. Otherwise, call get_stack_use_cr31
117 * to get a pointer to the base of the interrupt stack
118 * and push a pt_regs structure on that stack.
120 * Need to set up a kernel stack, so call the
121 * get_stack_use_cr30 macro to set up a pointer
122 * to the pt_regs structure contained within the
123 * task pointer pointed to by cr30. Set the stack
124 * pointer to point to the end of the task structure.
125 * N.B: We don't use the interrupt stack for the
126 * first interrupt from userland, because signals/
127 * resched's are processed when returning to userland,
128 * and we can sleep in those cases.
130 * Note that we use shadowed registers for temps until
131 * we can save %r26 and %r29. %r26 is used to preserve
132 * %r8 (a shadowed register) which temporarily contained
133 * either the fault type ("code") or the eirr. We need
134 * to use a non-shadowed register to carry the value over
135 * the rfir in virt_map. We use %r26 since this value winds
136 * up being passed as the argument to either do_cpu_irq_mask
137 * or handle_interruption. %r29 is used to hold a pointer
138 * the register save area, and once again, it needs to
139 * be a non-shadowed register so that it survives the rfir.
141 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
144 .macro get_stack_use_cr30
146 /* we save the registers in the task struct */
150 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
152 ldo TASK_REGS(%r9),%r9
153 STREG %r30, PT_GR30(%r9)
154 STREG %r29,PT_GR29(%r9)
155 STREG %r26,PT_GR26(%r9)
158 ldo THREAD_SZ_ALGN(%r1), %r30
161 .macro get_stack_use_r30
163 /* we put a struct pt_regs on the stack and save the registers there */
166 STREG %r30,PT_GR30(%r9)
167 ldo PT_SZ_ALGN(%r30),%r30
168 STREG %r29,PT_GR29(%r9)
169 STREG %r26,PT_GR26(%r9)
174 LDREG PT_GR1(%r29), %r1
175 LDREG PT_GR30(%r29),%r30
176 LDREG PT_GR29(%r29),%r29
179 /* default interruption handler
180 * (calls traps.c:handle_interruption) */
187 /* Interrupt interruption handler
188 * (calls irq.c:do_cpu_irq_mask) */
195 .import os_hpmc, code
199 nop /* must be a NOP, will be patched later */
200 ldil L%PA(os_hpmc), %r3
201 ldo R%PA(os_hpmc)(%r3), %r3
204 .word 0 /* checksum (will be patched) */
205 .word PA(os_hpmc) /* address of handler */
206 .word 0 /* length of handler */
210 * Performance Note: Instructions will be moved up into
211 * this part of the code later on, once we are sure
212 * that the tlb miss handlers are close to final form.
215 /* Register definitions for tlb miss handler macros */
217 va = r8 /* virtual address for which the trap occured */
218 spc = r24 /* space for which the trap occured */
223 * itlb miss interruption handler (parisc 1.1 - 32 bit)
237 * itlb miss interruption handler (parisc 2.0)
254 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
256 * Note: naitlb misses will be treated
257 * as an ordinary itlb miss for now.
258 * However, note that naitlb misses
259 * have the faulting address in the
263 .macro naitlb_11 code
268 /* FIXME: If user causes a naitlb miss, the priv level may not be in
269 * lower bits of va, where the itlb miss handler is expecting them
277 * naitlb miss interruption handler (parisc 2.0)
279 * Note: naitlb misses will be treated
280 * as an ordinary itlb miss for now.
281 * However, note that naitlb misses
282 * have the faulting address in the
286 .macro naitlb_20 code
295 /* FIXME: If user causes a naitlb miss, the priv level may not be in
296 * lower bits of va, where the itlb miss handler is expecting them
304 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
318 * dtlb miss interruption handler (parisc 2.0)
335 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
337 .macro nadtlb_11 code
347 /* nadtlb miss interruption handler (parisc 2.0) */
349 .macro nadtlb_20 code
364 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
378 * dirty bit trap interruption handler (parisc 2.0)
394 /* The following are simple 32 vs 64 bit instruction
395 * abstractions for the macros */
396 .macro EXTR reg1,start,length,reg2
398 extrd,u \reg1,32+\start,\length,\reg2
400 extrw,u \reg1,\start,\length,\reg2
404 .macro DEP reg1,start,length,reg2
406 depd \reg1,32+\start,\length,\reg2
408 depw \reg1,\start,\length,\reg2
412 .macro DEPI val,start,length,reg
414 depdi \val,32+\start,\length,\reg
416 depwi \val,\start,\length,\reg
420 /* In LP64, the space contains part of the upper 32 bits of the
421 * fault. We have to extract this and place it in the va,
422 * zeroing the corresponding bits in the space register */
423 .macro space_adjust spc,va,tmp
425 extrd,u \spc,63,SPACEID_SHIFT,\tmp
426 depd %r0,63,SPACEID_SHIFT,\spc
427 depd \tmp,31,SPACEID_SHIFT,\va
431 .import swapper_pg_dir,code
433 /* Get the pgd. For faults on space zero (kernel space), this
434 * is simply swapper_pg_dir. For user space faults, the
435 * pgd is stored in %cr25 */
436 .macro get_pgd spc,reg
437 ldil L%PA(swapper_pg_dir),\reg
438 ldo R%PA(swapper_pg_dir)(\reg),\reg
439 or,COND(=) %r0,\spc,%r0
444 space_check(spc,tmp,fault)
446 spc - The space we saw the fault with.
447 tmp - The place to store the current space.
448 fault - Function to call on failure.
450 Only allow faults on different spaces from the
451 currently active one if we're the kernel
454 .macro space_check spc,tmp,fault
456 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
457 * as kernel, so defeat the space
460 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
461 cmpb,COND(<>),n \tmp,\spc,\fault
464 /* Look up a PTE in a 2-Level scheme (faulting at each
465 * level if the entry isn't present
467 * NOTE: we use ldw even for LP64, since the short pointers
468 * can address up to 1TB
470 .macro L2_ptep pmd,pte,index,va,fault
472 EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
474 EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
476 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
478 ldw,s \index(\pmd),\pmd
479 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
480 DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
483 shld %r9,PxD_VALUE_SHIFT,\pmd
485 shlw %r9,PxD_VALUE_SHIFT,\pmd
487 EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
488 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
489 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
490 LDREG %r0(\pmd),\pte /* pmd is now pte */
491 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
494 /* Look up PTE in a 3-Level scheme.
496 * Here we implement a Hybrid L2/L3 scheme: we allocate the
497 * first pmd adjacent to the pgd. This means that we can
498 * subtract a constant offset to get to it. The pmd and pgd
499 * sizes are arranged so that a single pmd covers 4GB (giving
500 * a full LP64 process access to 8TB) so our lookups are
501 * effectively L2 for the first 4GB of the kernel (i.e. for
502 * all ILP32 processes and all the kernel for machines with
503 * under 4GB of memory) */
504 .macro L3_ptep pgd,pte,index,va,fault
505 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
507 extrd,u,*= \va,31,32,%r0
508 ldw,s \index(\pgd),\pgd
509 extrd,u,*= \va,31,32,%r0
510 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
511 extrd,u,*= \va,31,32,%r0
512 shld \pgd,PxD_VALUE_SHIFT,\index
513 extrd,u,*= \va,31,32,%r0
515 extrd,u,*<> \va,31,32,%r0
516 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
517 L2_ptep \pgd,\pte,\index,\va,\fault
520 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
521 * don't needlessly dirty the cache line if it was already set */
522 .macro update_ptep ptep,pte,tmp,tmp1
523 ldi _PAGE_ACCESSED,\tmp1
525 and,COND(<>) \tmp1,\pte,%r0
529 /* Set the dirty bit (and accessed bit). No need to be
530 * clever, this is only used from the dirty fault */
531 .macro update_dirty ptep,pte,tmp
532 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
537 /* Convert the pte and prot to tlb insertion values. How
538 * this happens is quite subtle, read below */
539 .macro make_insert_tlb spc,pte,prot
540 space_to_prot \spc \prot /* create prot id from space */
541 /* The following is the real subtlety. This is depositing
542 * T <-> _PAGE_REFTRAP
544 * B <-> _PAGE_DMB (memory break)
546 * Then incredible subtlety: The access rights are
547 * _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ
548 * See 3-14 of the parisc 2.0 manual
550 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
551 * trigger an access rights trap in user space if the user
552 * tries to read an unreadable page */
555 /* PAGE_USER indicates the page can be read with user privileges,
556 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
557 * contains _PAGE_READ */
558 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
560 /* If we're a gateway page, drop PL2 back to zero for promotion
561 * to kernel privilege (so we can execute the page as kernel).
562 * Any privilege promotion page always denys read and write */
563 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
564 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
566 /* Get rid of prot bits and convert to page addr for iitlbt */
568 depd %r0,63,PAGE_SHIFT,\pte
569 extrd,u \pte,56,32,\pte
572 /* Identical macro to make_insert_tlb above, except it
573 * makes the tlb entry for the differently formatted pa11
574 * insertion instructions */
575 .macro make_insert_tlb_11 spc,pte,prot
576 zdep \spc,30,15,\prot
578 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
580 extru,= \pte,_PAGE_USER_BIT,1,%r0
581 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
582 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
583 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
585 /* Get rid of prot bits and convert to page addr for iitlba */
588 extru \pte,24,25,\pte
592 /* This is for ILP32 PA2.0 only. The TLB insertion needs
593 * to extend into I/O space if the address is 0xfXXXXXXX
594 * so we extend the f's into the top word of the pte in
596 .macro f_extend pte,tmp
597 extrd,s \pte,42,4,\tmp
599 extrd,s \pte,63,25,\pte
602 /* The alias region is an 8MB aligned 16MB to do clear and
603 * copy user pages at addresses congruent with the user
606 * To use the alias page, you set %r26 up with the to TLB
607 * entry (identifying the physical page) and %r23 up with
608 * the from tlb entry (or nothing if only a to entry---for
609 * clear_user_page_asm) */
610 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault
611 cmpib,COND(<>),n 0,\spc,\fault
612 ldil L%(TMPALIAS_MAP_START),\tmp
613 #if defined(__LP64__) && (TMPALIAS_MAP_START >= 0x80000000)
614 /* on LP64, ldi will sign extend into the upper 32 bits,
615 * which is behaviour we don't want */
620 cmpb,COND(<>),n \tmp,\tmp1,\fault
621 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot
622 depd,z \prot,8,7,\prot
624 * OK, it is in the temp alias region, check whether "from" or "to".
625 * Check "subtle" note in pacache.S re: r23/r26.
628 extrd,u,*= \va,41,1,%r0
630 extrw,u,= \va,9,1,%r0
632 or,COND(tr) %r23,%r0,\pte
638 * Align fault_vector_20 on 4K boundary so that both
639 * fault_vector_11 and fault_vector_20 are on the
640 * same page. This is only necessary as long as we
641 * write protect the kernel text, which we may stop
642 * doing once we use large page translations to cover
643 * the static part of the kernel address space.
646 .export fault_vector_20
653 /* First vector is invalid (0) */
654 .ascii "cows can fly"
696 .export fault_vector_11
701 /* First vector is invalid (0) */
702 .ascii "cows can fly"
744 .import handle_interruption,code
745 .import do_cpu_irq_mask,code
748 * r26 = function to be called
749 * r25 = argument to pass in
750 * r24 = flags for do_fork()
752 * Kernel threads don't ever return, so they don't need
753 * a true register context. We just save away the arguments
754 * for copy_thread/ret_ to properly set up the child.
757 #define CLONE_VM 0x100 /* Must agree with <linux/sched.h> */
758 #define CLONE_UNTRACED 0x00800000
760 .export __kernel_thread, code
763 STREG %r2, -RP_OFFSET(%r30)
766 ldo PT_SZ_ALGN(%r30),%r30
768 /* Yo, function pointers in wide mode are little structs... -PB */
770 STREG %r2, PT_GR27(%r1) /* Store childs %dp */
773 STREG %r22, PT_GR22(%r1) /* save r22 (arg5) */
774 copy %r0, %r22 /* user_tid */
776 STREG %r26, PT_GR26(%r1) /* Store function & argument for child */
777 STREG %r25, PT_GR25(%r1)
778 ldil L%CLONE_UNTRACED, %r26
779 ldo CLONE_VM(%r26), %r26 /* Force CLONE_VM since only init_mm */
780 or %r26, %r24, %r26 /* will have kernel mappings. */
781 ldi 1, %r25 /* stack_start, signals kernel thread */
782 stw %r0, -52(%r30) /* user_tid */
784 ldo -16(%r30),%r29 /* Reference param save area */
787 copy %r1, %r24 /* pt_regs */
789 /* Parent Returns here */
791 LDREG -PT_SZ_ALGN-RP_OFFSET(%r30), %r2
792 ldo -PT_SZ_ALGN(%r30), %r30
799 * copy_thread moved args from temp save area set up above
800 * into task save area.
803 .export ret_from_kernel_thread
804 ret_from_kernel_thread:
806 /* Call schedule_tail first though */
807 BL schedule_tail, %r2
810 LDREG TI_TASK-THREAD_SZ_ALGN(%r30), %r1
811 LDREG TASK_PT_GR25(%r1), %r26
813 LDREG TASK_PT_GR27(%r1), %r27
814 LDREG TASK_PT_GR22(%r1), %r22
816 LDREG TASK_PT_GR26(%r1), %r1
821 ldo -16(%r30),%r29 /* Reference param save area */
822 loadgp /* Thread could have been in a module */
827 .import sys_execve, code
828 .export __execve, code
832 ldo PT_SZ_ALGN(%r30), %r30
833 STREG %r26, PT_GR26(%r16)
834 STREG %r25, PT_GR25(%r16)
835 STREG %r24, PT_GR24(%r16)
837 ldo -16(%r30),%r29 /* Reference param save area */
842 cmpib,=,n 0,%r28,intr_return /* forward */
844 /* yes, this will trap and die. */
853 * struct task_struct *_switch_to(struct task_struct *prev,
854 * struct task_struct *next)
856 * switch kernel stacks and return prev */
857 .export _switch_to, code
859 STREG %r2, -RP_OFFSET(%r30)
863 ldil L%_switch_to_ret, %r2
864 ldo R%_switch_to_ret(%r2), %r2
866 STREG %r2, TASK_PT_KPC(%r26)
867 LDREG TASK_PT_KPC(%r25), %r2
869 STREG %r30, TASK_PT_KSP(%r26)
870 LDREG TASK_PT_KSP(%r25), %r30
871 LDREG TASK_THREAD_INFO(%r25), %r25
876 mtctl %r0, %cr0 /* Needed for single stepping */
879 LDREG -RP_OFFSET(%r30), %r2
884 * Common rfi return path for interruptions, kernel execve, and
885 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
886 * return via this path if the signal was received when the process
887 * was running; if the process was blocked on a syscall then the
888 * normal syscall_exit path is used. All syscalls for traced
889 * proceses exit via intr_restore.
891 * XXX If any syscalls that change a processes space id ever exit
892 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
895 * Note that the following code uses a "relied upon translation".
896 * See the parisc ACD for details. The ssm is necessary due to a
902 .export syscall_exit_rfi
905 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
906 ldo TASK_REGS(%r16),%r16
907 /* Force iaoq to userspace, as the user has had access to our current
908 * context via sigcontext. Also Filter the PSW for the same reason.
910 LDREG PT_IAOQ0(%r16),%r19
912 STREG %r19,PT_IAOQ0(%r16)
913 LDREG PT_IAOQ1(%r16),%r19
915 STREG %r19,PT_IAOQ1(%r16)
916 LDREG PT_PSW(%r16),%r19
917 ldil L%USER_PSW_MASK,%r1
918 ldo R%USER_PSW_MASK(%r1),%r1
920 ldil L%USER_PSW_HI_MASK,%r20
921 ldo R%USER_PSW_HI_MASK(%r20),%r20
924 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
926 ldo R%USER_PSW(%r1),%r1
927 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
928 STREG %r19,PT_PSW(%r16)
931 * If we aren't being traced, we never saved space registers
932 * (we don't store them in the sigcontext), so set them
933 * to "proper" values now (otherwise we'll wind up restoring
934 * whatever was last stored in the task structure, which might
935 * be inconsistent if an interrupt occured while on the gateway
936 * page) Note that we may be "trashing" values the user put in
937 * them, but we don't support the the user changing them.
940 STREG %r0,PT_SR2(%r16)
942 STREG %r19,PT_SR0(%r16)
943 STREG %r19,PT_SR1(%r16)
944 STREG %r19,PT_SR3(%r16)
945 STREG %r19,PT_SR4(%r16)
946 STREG %r19,PT_SR5(%r16)
947 STREG %r19,PT_SR6(%r16)
948 STREG %r19,PT_SR7(%r16)
951 /* NOTE: Need to enable interrupts incase we schedule. */
954 /* Check for software interrupts */
956 .import irq_stat,data
959 ldo R%irq_stat(%r19),%r19
962 ldw TI_CPU(%r1),%r1 /* get cpu # - int */
963 /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount
964 ** irq_stat[] is defined using ____cacheline_aligned.
971 add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
972 #endif /* CONFIG_SMP */
974 LDREG IRQSTAT_SIRQ_PEND(%r19),%r20 /* hardirq.h: unsigned long */
975 cmpib,<>,n 0,%r20,intr_do_softirq /* forward */
979 /* check for reschedule */
981 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
982 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
987 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_SIGPENDING */
988 bb,<,n %r19, 31-TIF_SIGPENDING, intr_do_signal /* forward */
992 ldo PT_FR31(%r29),%r1
996 /* Create a "relied upon translation" PA 2.0 Arch. F-5 */
1006 rsm (PSW_SM_Q|PSW_SM_P|PSW_SM_D|PSW_SM_I),%r0
1008 /* Restore space id's and special cr's from PT_REGS
1009 * structure pointed to by r29 */
1012 /* Important: Note that rest_stack restores r29
1013 * last (we are using it)! It also restores r1 and r30. */
1026 .import do_softirq,code
1030 ldo -16(%r30),%r29 /* Reference param save area */
1034 b intr_check_resched
1037 .import schedule,code
1039 /* Only do reschedule if we are returning to user space */
1040 LDREG PT_IASQ0(%r16), %r20
1041 CMPIB= 0,%r20,intr_restore /* backward */
1043 LDREG PT_IASQ1(%r16), %r20
1044 CMPIB= 0,%r20,intr_restore /* backward */
1048 ldo -16(%r30),%r29 /* Reference param save area */
1051 ldil L%intr_check_sig, %r2
1053 ldo R%intr_check_sig(%r2), %r2
1056 .import do_signal,code
1059 This check is critical to having LWS
1060 working. The IASQ is zero on the gateway
1061 page and we cannot deliver any signals until
1062 we get off the gateway page.
1064 Only do signals if we are returning to user space
1066 LDREG PT_IASQ0(%r16), %r20
1067 CMPIB= 0,%r20,intr_restore /* backward */
1069 LDREG PT_IASQ1(%r16), %r20
1070 CMPIB= 0,%r20,intr_restore /* backward */
1073 copy %r0, %r24 /* unsigned long in_syscall */
1074 copy %r16, %r25 /* struct pt_regs *regs */
1076 ldo -16(%r30),%r29 /* Reference param save area */
1080 copy %r0, %r26 /* sigset_t *oldset = NULL */
1086 * External interrupts.
1095 #if 0 /* Interrupt Stack support not working yet! */
1098 /* FIXME! depi below has hardcoded idea of interrupt stack size (32k)*/
1116 ldo PT_FR0(%r29), %r24
1121 copy %r29, %r26 /* arg0 is pt_regs */
1122 copy %r29, %r16 /* save pt_regs */
1124 ldil L%intr_return, %r2
1127 ldo -16(%r30),%r29 /* Reference param save area */
1131 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1134 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1136 .export intr_save, code /* for os_hpmc */
1152 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1155 * FIXME: 1) Use a #define for the hardwired "6" below (and in
1157 * 2) Once we start executing code above 4 Gb, we need
1158 * to adjust iasq/iaoq here in the same way we
1159 * adjust isr/ior below.
1162 CMPIB=,n 6,%r26,skip_save_ior
1164 /* save_specials left ipsw value in r8 for us to test */
1166 mfctl %cr20, %r16 /* isr */
1167 mfctl %cr21, %r17 /* ior */
1171 * If the interrupted code was running with W bit off (32 bit),
1172 * clear the b bits (bits 0 & 1) in the ior.
1174 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1178 * FIXME: This code has hardwired assumptions about the split
1179 * between space bits and offset bits. This will change
1180 * when we allow alternate page sizes.
1183 /* adjust isr/ior. */
1185 extrd,u %r16,63,7,%r1 /* get high bits from isr for ior */
1186 depd %r1,31,7,%r17 /* deposit them into ior */
1187 depdi 0,63,7,%r16 /* clear them from isr */
1189 STREG %r16, PT_ISR(%r29)
1190 STREG %r17, PT_IOR(%r29)
1197 ldo PT_FR0(%r29), %r25
1202 copy %r29, %r25 /* arg1 is pt_regs */
1204 ldo -16(%r30),%r29 /* Reference param save area */
1207 ldil L%intr_check_sig, %r2
1208 copy %r25, %r16 /* save pt_regs */
1210 b handle_interruption
1211 ldo R%intr_check_sig(%r2), %r2
1215 * Note for all tlb miss handlers:
1217 * cr24 contains a pointer to the kernel address space
1220 * cr25 contains a pointer to the current user address
1221 * space page directory.
1223 * sr3 will contain the space id of the user address space
1224 * of the current running thread while that thread is
1225 * running in the kernel.
1229 * register number allocations. Note that these are all
1230 * in the shadowed registers
1233 t0 = r1 /* temporary register 0 */
1234 va = r8 /* virtual address for which the trap occured */
1235 t1 = r9 /* temporary register 1 */
1236 pte = r16 /* pte/phys page # */
1237 prot = r17 /* prot bits */
1238 spc = r24 /* space for which the trap occured */
1239 ptp = r25 /* page directory/page table pointer */
1244 space_adjust spc,va,t0
1246 space_check spc,t0,dtlb_fault
1248 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1250 update_ptep ptp,pte,t0,t1
1252 make_insert_tlb spc,pte,prot
1259 dtlb_check_alias_20w:
1260 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1268 space_adjust spc,va,t0
1270 space_check spc,t0,nadtlb_fault
1272 L3_ptep ptp,pte,t0,va,nadtlb_check_flush_20w
1274 update_ptep ptp,pte,t0,t1
1276 make_insert_tlb spc,pte,prot
1283 nadtlb_check_flush_20w:
1284 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1286 /* Insert a "flush only" translation */
1291 /* Get rid of prot bits and convert to page addr for idtlbt */
1294 extrd,u pte,56,52,pte
1305 space_check spc,t0,dtlb_fault
1307 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1309 update_ptep ptp,pte,t0,t1
1311 make_insert_tlb_11 spc,pte,prot
1313 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1316 idtlba pte,(%sr1,va)
1317 idtlbp prot,(%sr1,va)
1319 mtsp t0, %sr1 /* Restore sr1 */
1324 dtlb_check_alias_11:
1326 /* Check to see if fault is in the temporary alias region */
1328 cmpib,<>,n 0,spc,dtlb_fault /* forward */
1329 ldil L%(TMPALIAS_MAP_START),t0
1332 cmpb,<>,n t0,t1,dtlb_fault /* forward */
1333 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot
1334 depw,z prot,8,7,prot
1337 * OK, it is in the temp alias region, check whether "from" or "to".
1338 * Check "subtle" note in pacache.S re: r23/r26.
1342 or,tr %r23,%r0,pte /* If "from" use "from" page */
1343 or %r26,%r0,pte /* else "to", use "to" page */
1354 space_check spc,t0,nadtlb_fault
1356 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_11
1358 update_ptep ptp,pte,t0,t1
1360 make_insert_tlb_11 spc,pte,prot
1363 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1366 idtlba pte,(%sr1,va)
1367 idtlbp prot,(%sr1,va)
1369 mtsp t0, %sr1 /* Restore sr1 */
1374 nadtlb_check_flush_11:
1375 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1377 /* Insert a "flush only" translation */
1382 /* Get rid of prot bits and convert to page addr for idtlba */
1387 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1390 idtlba pte,(%sr1,va)
1391 idtlbp prot,(%sr1,va)
1393 mtsp t0, %sr1 /* Restore sr1 */
1399 space_adjust spc,va,t0
1401 space_check spc,t0,dtlb_fault
1403 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1405 update_ptep ptp,pte,t0,t1
1407 make_insert_tlb spc,pte,prot
1416 dtlb_check_alias_20:
1417 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1427 space_check spc,t0,nadtlb_fault
1429 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_20
1431 update_ptep ptp,pte,t0,t1
1433 make_insert_tlb spc,pte,prot
1442 nadtlb_check_flush_20:
1443 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1445 /* Insert a "flush only" translation */
1450 /* Get rid of prot bits and convert to page addr for idtlbt */
1453 extrd,u pte,56,32,pte
1463 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1464 * probei instructions. We don't want to fault for these
1465 * instructions (not only does it not make sense, it can cause
1466 * deadlocks, since some flushes are done with the mmap
1467 * semaphore held). If the translation doesn't exist, we can't
1468 * insert a translation, so have to emulate the side effects
1469 * of the instruction. Since we don't insert a translation
1470 * we can get a lot of faults during a flush loop, so it makes
1471 * sense to try to do it here with minimum overhead. We only
1472 * emulate fdc,fic,pdc,probew,prober instructions whose base
1473 * and index registers are not shadowed. We defer everything
1474 * else to the "slow" path.
1477 mfctl %cr19,%r9 /* Get iir */
1479 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1480 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1482 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1485 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1486 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1487 BL get_register,%r25
1488 extrw,u %r9,15,5,%r8 /* Get index register # */
1489 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1491 BL get_register,%r25
1492 extrw,u %r9,10,5,%r8 /* Get base register # */
1493 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1494 BL set_register,%r25
1495 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1498 mfctl %cr22,%r8 /* Get ipsw */
1500 or %r8,%r9,%r8 /* Set PSW_N */
1507 When there is no translation for the probe address then we
1508 must nullify the insn and return zero in the target regsiter.
1509 This will indicate to the calling code that it does not have
1510 write/read privileges to this address.
1512 This should technically work for prober and probew in PA 1.1,
1513 and also probe,r and probe,w in PA 2.0
1515 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1516 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1522 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1523 BL get_register,%r25 /* Find the target register */
1524 extrw,u %r9,31,5,%r8 /* Get target register */
1525 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1526 BL set_register,%r25
1527 copy %r0,%r1 /* Write zero to target register */
1528 b nadtlb_nullify /* Nullify return insn */
1536 * I miss is a little different, since we allow users to fault
1537 * on the gateway page which is in the kernel address space.
1540 space_adjust spc,va,t0
1542 space_check spc,t0,itlb_fault
1544 L3_ptep ptp,pte,t0,va,itlb_fault
1546 update_ptep ptp,pte,t0,t1
1548 make_insert_tlb spc,pte,prot
1560 space_check spc,t0,itlb_fault
1562 L2_ptep ptp,pte,t0,va,itlb_fault
1564 update_ptep ptp,pte,t0,t1
1566 make_insert_tlb_11 spc,pte,prot
1568 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1571 iitlba pte,(%sr1,va)
1572 iitlbp prot,(%sr1,va)
1574 mtsp t0, %sr1 /* Restore sr1 */
1582 space_check spc,t0,itlb_fault
1584 L2_ptep ptp,pte,t0,va,itlb_fault
1586 update_ptep ptp,pte,t0,t1
1588 make_insert_tlb spc,pte,prot
1602 space_adjust spc,va,t0
1604 space_check spc,t0,dbit_fault
1606 L3_ptep ptp,pte,t0,va,dbit_fault
1609 CMPIB=,n 0,spc,dbit_nolock_20w
1610 ldil L%PA(pa_dbit_lock),t0
1611 ldo R%PA(pa_dbit_lock)(t0),t0
1615 cmpib,= 0,t1,dbit_spin_20w
1620 update_dirty ptp,pte,t1
1622 make_insert_tlb spc,pte,prot
1626 CMPIB=,n 0,spc,dbit_nounlock_20w
1641 space_check spc,t0,dbit_fault
1643 L2_ptep ptp,pte,t0,va,dbit_fault
1646 CMPIB=,n 0,spc,dbit_nolock_11
1647 ldil L%PA(pa_dbit_lock),t0
1648 ldo R%PA(pa_dbit_lock)(t0),t0
1652 cmpib,= 0,t1,dbit_spin_11
1657 update_dirty ptp,pte,t1
1659 make_insert_tlb_11 spc,pte,prot
1661 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1664 idtlba pte,(%sr1,va)
1665 idtlbp prot,(%sr1,va)
1667 mtsp t1, %sr1 /* Restore sr1 */
1669 CMPIB=,n 0,spc,dbit_nounlock_11
1682 space_check spc,t0,dbit_fault
1684 L2_ptep ptp,pte,t0,va,dbit_fault
1687 CMPIB=,n 0,spc,dbit_nolock_20
1688 ldil L%PA(pa_dbit_lock),t0
1689 ldo R%PA(pa_dbit_lock)(t0),t0
1693 cmpib,= 0,t1,dbit_spin_20
1698 update_dirty ptp,pte,t1
1700 make_insert_tlb spc,pte,prot
1707 CMPIB=,n 0,spc,dbit_nounlock_20
1718 .import handle_interruption,code
1722 ldi 31,%r8 /* Use an unused code */
1740 /* Register saving semantics for system calls:
1742 %r1 clobbered by system call macro in userspace
1743 %r2 saved in PT_REGS by gateway page
1744 %r3 - %r18 preserved by C code (saved by signal code)
1745 %r19 - %r20 saved in PT_REGS by gateway page
1746 %r21 - %r22 non-standard syscall args
1747 stored in kernel stack by gateway page
1748 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1749 %r27 - %r30 saved in PT_REGS by gateway page
1750 %r31 syscall return pointer
1753 /* Floating point registers (FIXME: what do we do with these?)
1755 %fr0 - %fr3 status/exception, not preserved
1756 %fr4 - %fr7 arguments
1757 %fr8 - %fr11 not preserved by C code
1758 %fr12 - %fr21 preserved by C code
1759 %fr22 - %fr31 not preserved by C code
1762 .macro reg_save regs
1763 STREG %r3, PT_GR3(\regs)
1764 STREG %r4, PT_GR4(\regs)
1765 STREG %r5, PT_GR5(\regs)
1766 STREG %r6, PT_GR6(\regs)
1767 STREG %r7, PT_GR7(\regs)
1768 STREG %r8, PT_GR8(\regs)
1769 STREG %r9, PT_GR9(\regs)
1770 STREG %r10,PT_GR10(\regs)
1771 STREG %r11,PT_GR11(\regs)
1772 STREG %r12,PT_GR12(\regs)
1773 STREG %r13,PT_GR13(\regs)
1774 STREG %r14,PT_GR14(\regs)
1775 STREG %r15,PT_GR15(\regs)
1776 STREG %r16,PT_GR16(\regs)
1777 STREG %r17,PT_GR17(\regs)
1778 STREG %r18,PT_GR18(\regs)
1781 .macro reg_restore regs
1782 LDREG PT_GR3(\regs), %r3
1783 LDREG PT_GR4(\regs), %r4
1784 LDREG PT_GR5(\regs), %r5
1785 LDREG PT_GR6(\regs), %r6
1786 LDREG PT_GR7(\regs), %r7
1787 LDREG PT_GR8(\regs), %r8
1788 LDREG PT_GR9(\regs), %r9
1789 LDREG PT_GR10(\regs),%r10
1790 LDREG PT_GR11(\regs),%r11
1791 LDREG PT_GR12(\regs),%r12
1792 LDREG PT_GR13(\regs),%r13
1793 LDREG PT_GR14(\regs),%r14
1794 LDREG PT_GR15(\regs),%r15
1795 LDREG PT_GR16(\regs),%r16
1796 LDREG PT_GR17(\regs),%r17
1797 LDREG PT_GR18(\regs),%r18
1800 .export sys_fork_wrapper
1801 .export child_return
1803 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1804 ldo TASK_REGS(%r1),%r1
1807 STREG %r3, PT_CR27(%r1)
1809 STREG %r2,-RP_OFFSET(%r30)
1810 ldo FRAME_SIZE(%r30),%r30
1812 ldo -16(%r30),%r29 /* Reference param save area */
1815 /* These are call-clobbered registers and therefore
1816 also syscall-clobbered (we hope). */
1817 STREG %r2,PT_GR19(%r1) /* save for child */
1818 STREG %r30,PT_GR21(%r1)
1820 LDREG PT_GR30(%r1),%r25
1825 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1827 ldo -FRAME_SIZE(%r30),%r30 /* get the stackframe */
1828 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1829 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1831 LDREG PT_CR27(%r1), %r3
1835 /* strace expects syscall # to be preserved in r20 */
1838 STREG %r20,PT_GR20(%r1)
1840 /* Set the return value for the child */
1842 BL schedule_tail, %r2
1845 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE-FRAME_SIZE(%r30), %r1
1846 LDREG TASK_PT_GR19(%r1),%r2
1851 .export sys_clone_wrapper
1853 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1854 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1857 STREG %r3, PT_CR27(%r1)
1859 STREG %r2,-RP_OFFSET(%r30)
1860 ldo FRAME_SIZE(%r30),%r30
1862 ldo -16(%r30),%r29 /* Reference param save area */
1865 STREG %r2,PT_GR19(%r1) /* save for child */
1866 STREG %r30,PT_GR21(%r1)
1871 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1873 .export sys_vfork_wrapper
1875 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1876 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1879 STREG %r3, PT_CR27(%r1)
1881 STREG %r2,-RP_OFFSET(%r30)
1882 ldo FRAME_SIZE(%r30),%r30
1884 ldo -16(%r30),%r29 /* Reference param save area */
1887 STREG %r2,PT_GR19(%r1) /* save for child */
1888 STREG %r30,PT_GR21(%r1)
1894 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1897 .macro execve_wrapper execve
1898 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1899 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1902 * Do we need to save/restore r3-r18 here?
1903 * I don't think so. why would new thread need old
1904 * threads registers?
1907 /* %arg0 - %arg3 are already saved for us. */
1909 STREG %r2,-RP_OFFSET(%r30)
1910 ldo FRAME_SIZE(%r30),%r30
1912 ldo -16(%r30),%r29 /* Reference param save area */
1917 ldo -FRAME_SIZE(%r30),%r30
1918 LDREG -RP_OFFSET(%r30),%r2
1920 /* If exec succeeded we need to load the args */
1923 cmpb,>>= %r28,%r1,error_\execve
1931 .export sys_execve_wrapper
1935 execve_wrapper sys_execve
1938 .export sys32_execve_wrapper
1939 .import sys32_execve
1941 sys32_execve_wrapper:
1942 execve_wrapper sys32_execve
1945 .export sys_rt_sigreturn_wrapper
1946 sys_rt_sigreturn_wrapper:
1947 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1948 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1949 /* Don't save regs, we are going to restore them from sigcontext. */
1950 STREG %r2, -RP_OFFSET(%r30)
1952 ldo FRAME_SIZE(%r30), %r30
1953 BL sys_rt_sigreturn,%r2
1954 ldo -16(%r30),%r29 /* Reference param save area */
1956 BL sys_rt_sigreturn,%r2
1957 ldo FRAME_SIZE(%r30), %r30
1960 ldo -FRAME_SIZE(%r30), %r30
1961 LDREG -RP_OFFSET(%r30), %r2
1963 /* FIXME: I think we need to restore a few more things here. */
1964 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1965 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1968 /* If the signal was received while the process was blocked on a
1969 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1970 * take us to syscall_exit_rfi and on to intr_return.
1973 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1975 .export sys_sigaltstack_wrapper
1976 sys_sigaltstack_wrapper:
1977 /* Get the user stack pointer */
1978 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1979 ldo TASK_REGS(%r1),%r24 /* get pt regs */
1980 LDREG TASK_PT_GR30(%r24),%r24
1981 STREG %r2, -RP_OFFSET(%r30)
1983 ldo FRAME_SIZE(%r30), %r30
1984 b,l do_sigaltstack,%r2
1985 ldo -16(%r30),%r29 /* Reference param save area */
1987 bl do_sigaltstack,%r2
1988 ldo FRAME_SIZE(%r30), %r30
1991 ldo -FRAME_SIZE(%r30), %r30
1992 LDREG -RP_OFFSET(%r30), %r2
1997 .export sys32_sigaltstack_wrapper
1998 sys32_sigaltstack_wrapper:
1999 /* Get the user stack pointer */
2000 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r24
2001 LDREG TASK_PT_GR30(%r24),%r24
2002 STREG %r2, -RP_OFFSET(%r30)
2003 ldo FRAME_SIZE(%r30), %r30
2004 b,l do_sigaltstack32,%r2
2005 ldo -16(%r30),%r29 /* Reference param save area */
2007 ldo -FRAME_SIZE(%r30), %r30
2008 LDREG -RP_OFFSET(%r30), %r2
2013 .export sys_rt_sigsuspend_wrapper
2014 sys_rt_sigsuspend_wrapper:
2015 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
2016 ldo TASK_REGS(%r1),%r24
2019 STREG %r2, -RP_OFFSET(%r30)
2021 ldo FRAME_SIZE(%r30), %r30
2022 b,l sys_rt_sigsuspend,%r2
2023 ldo -16(%r30),%r29 /* Reference param save area */
2025 bl sys_rt_sigsuspend,%r2
2026 ldo FRAME_SIZE(%r30), %r30
2029 ldo -FRAME_SIZE(%r30), %r30
2030 LDREG -RP_OFFSET(%r30), %r2
2032 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
2033 ldo TASK_REGS(%r1),%r1
2039 .export syscall_exit
2042 /* NOTE: HP-UX syscalls also come through here
2043 * after hpux_syscall_exit fixes up return
2046 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
2047 * via syscall_exit_rfi if the signal was received while the process
2051 /* save return value now */
2054 LDREG TI_TASK(%r1),%r1
2055 STREG %r28,TASK_PT_GR28(%r1)
2059 /* <linux/personality.h> cannot be easily included */
2060 #define PER_HPUX 0x10
2061 LDREG TASK_PERSONALITY(%r1),%r19
2063 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
2064 ldo -PER_HPUX(%r19), %r19
2067 /* Save other hpux returns if personality is PER_HPUX */
2068 STREG %r22,TASK_PT_GR22(%r1)
2069 STREG %r29,TASK_PT_GR29(%r1)
2072 #endif /* CONFIG_HPUX */
2074 /* Seems to me that dp could be wrong here, if the syscall involved
2075 * calling a module, and nothing got round to restoring dp on return.
2081 /* Check for software interrupts */
2083 .import irq_stat,data
2085 ldil L%irq_stat,%r19
2086 ldo R%irq_stat(%r19),%r19
2089 /* sched.h: int processor */
2090 /* %r26 is used as scratch register to index into irq_stat[] */
2091 ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */
2093 /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */
2099 add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
2100 #endif /* CONFIG_SMP */
2102 LDREG IRQSTAT_SIRQ_PEND(%r19),%r20 /* hardirq.h: unsigned long */
2103 cmpib,<>,n 0,%r20,syscall_do_softirq /* forward */
2105 syscall_check_resched:
2107 /* check for reschedule */
2109 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
2110 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
2113 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* get ti flags */
2114 bb,<,n %r19, 31-TIF_SIGPENDING, syscall_do_signal /* forward */
2117 /* Are we being ptraced? */
2118 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2120 LDREG TASK_PTRACE(%r1), %r19
2121 bb,< %r19,31,syscall_restore_rfi
2124 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
2127 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
2130 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
2131 LDREG TASK_PT_GR19(%r1),%r19
2132 LDREG TASK_PT_GR20(%r1),%r20
2133 LDREG TASK_PT_GR21(%r1),%r21
2134 LDREG TASK_PT_GR22(%r1),%r22
2135 LDREG TASK_PT_GR23(%r1),%r23
2136 LDREG TASK_PT_GR24(%r1),%r24
2137 LDREG TASK_PT_GR25(%r1),%r25
2138 LDREG TASK_PT_GR26(%r1),%r26
2139 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
2140 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
2141 LDREG TASK_PT_GR29(%r1),%r29
2142 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
2144 /* NOTE: We use rsm/ssm pair to make this operation atomic */
2146 LDREG TASK_PT_GR30(%r1),%r30 /* restore user sp */
2147 mfsp %sr3,%r1 /* Get users space id */
2148 mtsp %r1,%sr7 /* Restore sr7 */
2151 /* Set sr2 to zero for userspace syscalls to work. */
2153 mtsp %r1,%sr4 /* Restore sr4 */
2154 mtsp %r1,%sr5 /* Restore sr5 */
2155 mtsp %r1,%sr6 /* Restore sr6 */
2157 depi 3,31,2,%r31 /* ensure return to user mode. */
2160 /* decide whether to reset the wide mode bit
2162 * For a syscall, the W bit is stored in the lowest bit
2163 * of sp. Extract it and reset W if it is zero */
2164 extrd,u,*<> %r30,63,1,%r1
2166 /* now reset the lowest bit of sp if it was set */
2169 be,n 0(%sr3,%r31) /* return to user space */
2171 /* We have to return via an RFI, so that PSW T and R bits can be set
2173 * This sets up pt_regs so we can return via intr_restore, which is not
2174 * the most efficient way of doing things, but it works.
2176 syscall_restore_rfi:
2177 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
2178 mtctl %r2,%cr0 /* for immediate trap */
2179 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
2180 ldi 0x0b,%r20 /* Create new PSW */
2181 depi -1,13,1,%r20 /* C, Q, D, and I bits */
2183 /* The values of PA_SINGLESTEP_BIT and PA_BLOCKSTEP_BIT are
2184 * set in include/linux/ptrace.h and converted to PA bitmap
2185 * numbers in asm-offsets.c */
2187 /* if ((%r19.PA_SINGLESTEP_BIT)) { %r20.27=1} */
2188 extru,= %r19,PA_SINGLESTEP_BIT,1,%r0
2189 depi -1,27,1,%r20 /* R bit */
2191 /* if ((%r19.PA_BLOCKSTEP_BIT)) { %r20.7=1} */
2192 extru,= %r19,PA_BLOCKSTEP_BIT,1,%r0
2193 depi -1,7,1,%r20 /* T bit */
2195 STREG %r20,TASK_PT_PSW(%r1)
2197 /* Always store space registers, since sr3 can be changed (e.g. fork) */
2200 STREG %r25,TASK_PT_SR3(%r1)
2201 STREG %r25,TASK_PT_SR4(%r1)
2202 STREG %r25,TASK_PT_SR5(%r1)
2203 STREG %r25,TASK_PT_SR6(%r1)
2204 STREG %r25,TASK_PT_SR7(%r1)
2205 STREG %r25,TASK_PT_IASQ0(%r1)
2206 STREG %r25,TASK_PT_IASQ1(%r1)
2209 /* Now if old D bit is clear, it means we didn't save all registers
2210 * on syscall entry, so do that now. This only happens on TRACEME
2211 * calls, or if someone attached to us while we were on a syscall.
2212 * We could make this more efficient by not saving r3-r18, but
2213 * then we wouldn't be able to use the common intr_restore path.
2214 * It is only for traced processes anyway, so performance is not
2217 bb,< %r2,30,pt_regs_ok /* Branch if D set */
2218 ldo TASK_REGS(%r1),%r25
2219 reg_save %r25 /* Save r3 to r18 */
2221 /* Save the current sr */
2223 STREG %r2,TASK_PT_SR0(%r1)
2225 /* Save the scratch sr */
2227 STREG %r2,TASK_PT_SR1(%r1)
2229 /* sr2 should be set to zero for userspace syscalls */
2230 STREG %r0,TASK_PT_SR2(%r1)
2233 LDREG TASK_PT_GR31(%r1),%r2
2234 depi 3,31,2,%r2 /* ensure return to user mode. */
2235 STREG %r2,TASK_PT_IAOQ0(%r1)
2237 STREG %r2,TASK_PT_IAOQ1(%r1)
2242 .import do_softirq,code
2246 /* NOTE: We enable I-bit incase we schedule later,
2247 * and we might be going back to userspace if we were
2249 b syscall_check_resched
2250 ssm PSW_SM_I, %r0 /* do_softirq returns with I bit off */
2252 .import schedule,code
2256 ldo -16(%r30),%r29 /* Reference param save area */
2260 b syscall_check_bh /* if resched, we start over again */
2263 .import do_signal,code
2265 /* Save callee-save registers (for sigcontext).
2266 FIXME: After this point the process structure should be
2267 consistent with all the relevant state of the process
2268 before the syscall. We need to verify this. */
2269 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2270 ldo TASK_REGS(%r1), %r25 /* struct pt_regs *regs */
2273 ldi 1, %r24 /* unsigned long in_syscall */
2276 ldo -16(%r30),%r29 /* Reference param save area */
2279 copy %r0, %r26 /* sigset_t *oldset = NULL */
2281 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2282 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
2288 * get_register is used by the non access tlb miss handlers to
2289 * copy the value of the general register specified in r8 into
2290 * r1. This routine can't be used for shadowed registers, since
2291 * the rfir will restore the original value. So, for the shadowed
2292 * registers we put a -1 into r1 to indicate that the register
2293 * should not be used (the register being copied could also have
2294 * a -1 in it, but that is OK, it just means that we will have
2295 * to use the slow path instead).
2301 bv %r0(%r25) /* r0 */
2303 bv %r0(%r25) /* r1 - shadowed */
2305 bv %r0(%r25) /* r2 */
2307 bv %r0(%r25) /* r3 */
2309 bv %r0(%r25) /* r4 */
2311 bv %r0(%r25) /* r5 */
2313 bv %r0(%r25) /* r6 */
2315 bv %r0(%r25) /* r7 */
2317 bv %r0(%r25) /* r8 - shadowed */
2319 bv %r0(%r25) /* r9 - shadowed */
2321 bv %r0(%r25) /* r10 */
2323 bv %r0(%r25) /* r11 */
2325 bv %r0(%r25) /* r12 */
2327 bv %r0(%r25) /* r13 */
2329 bv %r0(%r25) /* r14 */
2331 bv %r0(%r25) /* r15 */
2333 bv %r0(%r25) /* r16 - shadowed */
2335 bv %r0(%r25) /* r17 - shadowed */
2337 bv %r0(%r25) /* r18 */
2339 bv %r0(%r25) /* r19 */
2341 bv %r0(%r25) /* r20 */
2343 bv %r0(%r25) /* r21 */
2345 bv %r0(%r25) /* r22 */
2347 bv %r0(%r25) /* r23 */
2349 bv %r0(%r25) /* r24 - shadowed */
2351 bv %r0(%r25) /* r25 - shadowed */
2353 bv %r0(%r25) /* r26 */
2355 bv %r0(%r25) /* r27 */
2357 bv %r0(%r25) /* r28 */
2359 bv %r0(%r25) /* r29 */
2361 bv %r0(%r25) /* r30 */
2363 bv %r0(%r25) /* r31 */
2367 * set_register is used by the non access tlb miss handlers to
2368 * copy the value of r1 into the general register specified in
2375 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2377 bv %r0(%r25) /* r1 */
2379 bv %r0(%r25) /* r2 */
2381 bv %r0(%r25) /* r3 */
2383 bv %r0(%r25) /* r4 */
2385 bv %r0(%r25) /* r5 */
2387 bv %r0(%r25) /* r6 */
2389 bv %r0(%r25) /* r7 */
2391 bv %r0(%r25) /* r8 */
2393 bv %r0(%r25) /* r9 */
2395 bv %r0(%r25) /* r10 */
2397 bv %r0(%r25) /* r11 */
2399 bv %r0(%r25) /* r12 */
2401 bv %r0(%r25) /* r13 */
2403 bv %r0(%r25) /* r14 */
2405 bv %r0(%r25) /* r15 */
2407 bv %r0(%r25) /* r16 */
2409 bv %r0(%r25) /* r17 */
2411 bv %r0(%r25) /* r18 */
2413 bv %r0(%r25) /* r19 */
2415 bv %r0(%r25) /* r20 */
2417 bv %r0(%r25) /* r21 */
2419 bv %r0(%r25) /* r22 */
2421 bv %r0(%r25) /* r23 */
2423 bv %r0(%r25) /* r24 */
2425 bv %r0(%r25) /* r25 */
2427 bv %r0(%r25) /* r26 */
2429 bv %r0(%r25) /* r27 */
2431 bv %r0(%r25) /* r28 */
2433 bv %r0(%r25) /* r29 */
2435 bv %r0(%r25) /* r30 */
2437 bv %r0(%r25) /* r31 */