2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
38 #include <asm/thread_info.h>
54 .import pa_dbit_lock,data
56 /* space_to_prot macro creates a prot id from a space id */
58 #if (SPACEID_SHIFT) == 0
59 .macro space_to_prot spc prot
60 depd,z \spc,62,31,\prot
63 .macro space_to_prot spc prot
64 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
68 /* Switch to virtual mapping, trashing only %r1 */
71 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
75 or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
78 load32 KERNEL_PSW, %r1
80 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
83 mtctl %r0, %cr17 /* Clear IIASQ tail */
84 mtctl %r0, %cr17 /* Clear IIASQ head */
87 mtctl %r1, %cr18 /* Set IIAOQ tail */
89 mtctl %r1, %cr18 /* Set IIAOQ head */
96 * The "get_stack" macros are responsible for determining the
101 * Already using a kernel stack, so call the
102 * get_stack_use_r30 macro to push a pt_regs structure
103 * on the stack, and store registers there.
105 * Need to set up a kernel stack, so call the
106 * get_stack_use_cr30 macro to set up a pointer
107 * to the pt_regs structure contained within the
108 * task pointer pointed to by cr30. Set the stack
109 * pointer to point to the end of the task structure.
113 * Already using a kernel stack, check to see if r30
114 * is already pointing to the per processor interrupt
115 * stack. If it is, call the get_stack_use_r30 macro
116 * to push a pt_regs structure on the stack, and store
117 * registers there. Otherwise, call get_stack_use_cr31
118 * to get a pointer to the base of the interrupt stack
119 * and push a pt_regs structure on that stack.
121 * Need to set up a kernel stack, so call the
122 * get_stack_use_cr30 macro to set up a pointer
123 * to the pt_regs structure contained within the
124 * task pointer pointed to by cr30. Set the stack
125 * pointer to point to the end of the task structure.
126 * N.B: We don't use the interrupt stack for the
127 * first interrupt from userland, because signals/
128 * resched's are processed when returning to userland,
129 * and we can sleep in those cases.
131 * Note that we use shadowed registers for temps until
132 * we can save %r26 and %r29. %r26 is used to preserve
133 * %r8 (a shadowed register) which temporarily contained
134 * either the fault type ("code") or the eirr. We need
135 * to use a non-shadowed register to carry the value over
136 * the rfir in virt_map. We use %r26 since this value winds
137 * up being passed as the argument to either do_cpu_irq_mask
138 * or handle_interruption. %r29 is used to hold a pointer
139 * the register save area, and once again, it needs to
140 * be a non-shadowed register so that it survives the rfir.
142 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
145 .macro get_stack_use_cr30
147 /* we save the registers in the task struct */
151 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
153 ldo TASK_REGS(%r9),%r9
154 STREG %r30, PT_GR30(%r9)
155 STREG %r29,PT_GR29(%r9)
156 STREG %r26,PT_GR26(%r9)
159 ldo THREAD_SZ_ALGN(%r1), %r30
162 .macro get_stack_use_r30
164 /* we put a struct pt_regs on the stack and save the registers there */
167 STREG %r30,PT_GR30(%r9)
168 ldo PT_SZ_ALGN(%r30),%r30
169 STREG %r29,PT_GR29(%r9)
170 STREG %r26,PT_GR26(%r9)
175 LDREG PT_GR1(%r29), %r1
176 LDREG PT_GR30(%r29),%r30
177 LDREG PT_GR29(%r29),%r29
180 /* default interruption handler
181 * (calls traps.c:handle_interruption) */
188 /* Interrupt interruption handler
189 * (calls irq.c:do_cpu_irq_mask) */
196 .import os_hpmc, code
200 nop /* must be a NOP, will be patched later */
201 load32 PA(os_hpmc), %r3
204 .word 0 /* checksum (will be patched) */
205 .word PA(os_hpmc) /* address of handler */
206 .word 0 /* length of handler */
210 * Performance Note: Instructions will be moved up into
211 * this part of the code later on, once we are sure
212 * that the tlb miss handlers are close to final form.
215 /* Register definitions for tlb miss handler macros */
217 va = r8 /* virtual address for which the trap occured */
218 spc = r24 /* space for which the trap occured */
223 * itlb miss interruption handler (parisc 1.1 - 32 bit)
237 * itlb miss interruption handler (parisc 2.0)
254 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
256 * Note: naitlb misses will be treated
257 * as an ordinary itlb miss for now.
258 * However, note that naitlb misses
259 * have the faulting address in the
263 .macro naitlb_11 code
268 /* FIXME: If user causes a naitlb miss, the priv level may not be in
269 * lower bits of va, where the itlb miss handler is expecting them
277 * naitlb miss interruption handler (parisc 2.0)
279 * Note: naitlb misses will be treated
280 * as an ordinary itlb miss for now.
281 * However, note that naitlb misses
282 * have the faulting address in the
286 .macro naitlb_20 code
295 /* FIXME: If user causes a naitlb miss, the priv level may not be in
296 * lower bits of va, where the itlb miss handler is expecting them
304 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
318 * dtlb miss interruption handler (parisc 2.0)
335 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
337 .macro nadtlb_11 code
347 /* nadtlb miss interruption handler (parisc 2.0) */
349 .macro nadtlb_20 code
364 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
378 * dirty bit trap interruption handler (parisc 2.0)
394 /* The following are simple 32 vs 64 bit instruction
395 * abstractions for the macros */
396 .macro EXTR reg1,start,length,reg2
398 extrd,u \reg1,32+\start,\length,\reg2
400 extrw,u \reg1,\start,\length,\reg2
404 .macro DEP reg1,start,length,reg2
406 depd \reg1,32+\start,\length,\reg2
408 depw \reg1,\start,\length,\reg2
412 .macro DEPI val,start,length,reg
414 depdi \val,32+\start,\length,\reg
416 depwi \val,\start,\length,\reg
420 /* In LP64, the space contains part of the upper 32 bits of the
421 * fault. We have to extract this and place it in the va,
422 * zeroing the corresponding bits in the space register */
423 .macro space_adjust spc,va,tmp
425 extrd,u \spc,63,SPACEID_SHIFT,\tmp
426 depd %r0,63,SPACEID_SHIFT,\spc
427 depd \tmp,31,SPACEID_SHIFT,\va
431 .import swapper_pg_dir,code
433 /* Get the pgd. For faults on space zero (kernel space), this
434 * is simply swapper_pg_dir. For user space faults, the
435 * pgd is stored in %cr25 */
436 .macro get_pgd spc,reg
437 ldil L%PA(swapper_pg_dir),\reg
438 ldo R%PA(swapper_pg_dir)(\reg),\reg
439 or,COND(=) %r0,\spc,%r0
444 space_check(spc,tmp,fault)
446 spc - The space we saw the fault with.
447 tmp - The place to store the current space.
448 fault - Function to call on failure.
450 Only allow faults on different spaces from the
451 currently active one if we're the kernel
454 .macro space_check spc,tmp,fault
456 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
457 * as kernel, so defeat the space
460 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
461 cmpb,COND(<>),n \tmp,\spc,\fault
464 /* Look up a PTE in a 2-Level scheme (faulting at each
465 * level if the entry isn't present
467 * NOTE: we use ldw even for LP64, since the short pointers
468 * can address up to 1TB
470 .macro L2_ptep pmd,pte,index,va,fault
472 EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
474 EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
476 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
478 ldw,s \index(\pmd),\pmd
479 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
480 DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
482 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
483 EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
484 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
485 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
486 LDREG %r0(\pmd),\pte /* pmd is now pte */
487 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
490 /* Look up PTE in a 3-Level scheme.
492 * Here we implement a Hybrid L2/L3 scheme: we allocate the
493 * first pmd adjacent to the pgd. This means that we can
494 * subtract a constant offset to get to it. The pmd and pgd
495 * sizes are arranged so that a single pmd covers 4GB (giving
496 * a full LP64 process access to 8TB) so our lookups are
497 * effectively L2 for the first 4GB of the kernel (i.e. for
498 * all ILP32 processes and all the kernel for machines with
499 * under 4GB of memory) */
500 .macro L3_ptep pgd,pte,index,va,fault
501 #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
502 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
504 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
505 ldw,s \index(\pgd),\pgd
506 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
507 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
508 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
509 shld \pgd,PxD_VALUE_SHIFT,\index
510 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
512 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
513 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
515 L2_ptep \pgd,\pte,\index,\va,\fault
518 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
519 * don't needlessly dirty the cache line if it was already set */
520 .macro update_ptep ptep,pte,tmp,tmp1
521 ldi _PAGE_ACCESSED,\tmp1
523 and,COND(<>) \tmp1,\pte,%r0
527 /* Set the dirty bit (and accessed bit). No need to be
528 * clever, this is only used from the dirty fault */
529 .macro update_dirty ptep,pte,tmp
530 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
535 /* Convert the pte and prot to tlb insertion values. How
536 * this happens is quite subtle, read below */
537 .macro make_insert_tlb spc,pte,prot
538 space_to_prot \spc \prot /* create prot id from space */
539 /* The following is the real subtlety. This is depositing
540 * T <-> _PAGE_REFTRAP
542 * B <-> _PAGE_DMB (memory break)
544 * Then incredible subtlety: The access rights are
545 * _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ
546 * See 3-14 of the parisc 2.0 manual
548 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
549 * trigger an access rights trap in user space if the user
550 * tries to read an unreadable page */
553 /* PAGE_USER indicates the page can be read with user privileges,
554 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
555 * contains _PAGE_READ */
556 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
558 /* If we're a gateway page, drop PL2 back to zero for promotion
559 * to kernel privilege (so we can execute the page as kernel).
560 * Any privilege promotion page always denys read and write */
561 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
562 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
564 /* Enforce uncacheable pages.
565 * This should ONLY be use for MMIO on PA 2.0 machines.
566 * Memory/DMA is cache coherent on all PA2.0 machines we support
567 * (that means T-class is NOT supported) and the memory controllers
568 * on most of those machines only handles cache transactions.
570 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
573 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
574 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte
575 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,63-58,\pte
578 /* Identical macro to make_insert_tlb above, except it
579 * makes the tlb entry for the differently formatted pa11
580 * insertion instructions */
581 .macro make_insert_tlb_11 spc,pte,prot
582 zdep \spc,30,15,\prot
584 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
586 extru,= \pte,_PAGE_USER_BIT,1,%r0
587 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
588 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
589 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
591 /* Get rid of prot bits and convert to page addr for iitlba */
593 depi _PAGE_SIZE_ENCODING_DEFAULT,31,ASM_PFN_PTE_SHIFT,\pte
594 extru \pte,24,25,\pte
597 /* This is for ILP32 PA2.0 only. The TLB insertion needs
598 * to extend into I/O space if the address is 0xfXXXXXXX
599 * so we extend the f's into the top word of the pte in
601 .macro f_extend pte,tmp
602 extrd,s \pte,42,4,\tmp
604 extrd,s \pte,63,25,\pte
607 /* The alias region is an 8MB aligned 16MB to do clear and
608 * copy user pages at addresses congruent with the user
611 * To use the alias page, you set %r26 up with the to TLB
612 * entry (identifying the physical page) and %r23 up with
613 * the from tlb entry (or nothing if only a to entry---for
614 * clear_user_page_asm) */
615 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault
616 cmpib,COND(<>),n 0,\spc,\fault
617 ldil L%(TMPALIAS_MAP_START),\tmp
618 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
619 /* on LP64, ldi will sign extend into the upper 32 bits,
620 * which is behaviour we don't want */
625 cmpb,COND(<>),n \tmp,\tmp1,\fault
626 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot
627 depd,z \prot,8,7,\prot
629 * OK, it is in the temp alias region, check whether "from" or "to".
630 * Check "subtle" note in pacache.S re: r23/r26.
633 extrd,u,*= \va,41,1,%r0
635 extrw,u,= \va,9,1,%r0
637 or,COND(tr) %r23,%r0,\pte
643 * Align fault_vector_20 on 4K boundary so that both
644 * fault_vector_11 and fault_vector_20 are on the
645 * same page. This is only necessary as long as we
646 * write protect the kernel text, which we may stop
647 * doing once we use large page translations to cover
648 * the static part of the kernel address space.
651 .export fault_vector_20
658 /* First vector is invalid (0) */
659 .ascii "cows can fly"
701 .export fault_vector_11
706 /* First vector is invalid (0) */
707 .ascii "cows can fly"
749 .import handle_interruption,code
750 .import do_cpu_irq_mask,code
753 * r26 = function to be called
754 * r25 = argument to pass in
755 * r24 = flags for do_fork()
757 * Kernel threads don't ever return, so they don't need
758 * a true register context. We just save away the arguments
759 * for copy_thread/ret_ to properly set up the child.
762 #define CLONE_VM 0x100 /* Must agree with <linux/sched.h> */
763 #define CLONE_UNTRACED 0x00800000
764 #define CLONE_KTHREAD 0x10000000
766 .export __kernel_thread, code
769 STREG %r2, -RP_OFFSET(%r30)
772 ldo PT_SZ_ALGN(%r30),%r30
774 /* Yo, function pointers in wide mode are little structs... -PB */
776 STREG %r2, PT_GR27(%r1) /* Store childs %dp */
779 STREG %r22, PT_GR22(%r1) /* save r22 (arg5) */
780 copy %r0, %r22 /* user_tid */
782 STREG %r26, PT_GR26(%r1) /* Store function & argument for child */
783 STREG %r25, PT_GR25(%r1)
784 ldil L%CLONE_UNTRACED, %r26
785 ldo CLONE_VM(%r26), %r26 /* Force CLONE_VM since only init_mm */
786 or %r26, %r24, %r26 /* will have kernel mappings. */
787 ldi 1, %r25 /* stack_start, signals kernel thread */
788 stw %r0, -52(%r30) /* user_tid */
790 ldo -16(%r30),%r29 /* Reference param save area */
793 copy %r1, %r24 /* pt_regs */
795 /* Parent Returns here */
797 LDREG -PT_SZ_ALGN-RP_OFFSET(%r30), %r2
798 ldo -PT_SZ_ALGN(%r30), %r30
805 * copy_thread moved args from temp save area set up above
806 * into task save area.
809 .export ret_from_kernel_thread
810 ret_from_kernel_thread:
812 /* Call schedule_tail first though */
813 BL schedule_tail, %r2
816 LDREG TI_TASK-THREAD_SZ_ALGN(%r30), %r1
817 LDREG TASK_PT_GR25(%r1), %r26
819 LDREG TASK_PT_GR27(%r1), %r27
820 LDREG TASK_PT_GR22(%r1), %r22
822 LDREG TASK_PT_GR26(%r1), %r1
827 ldo -16(%r30),%r29 /* Reference param save area */
828 loadgp /* Thread could have been in a module */
838 .import sys_execve, code
839 .export __execve, code
843 ldo PT_SZ_ALGN(%r30), %r30
844 STREG %r26, PT_GR26(%r16)
845 STREG %r25, PT_GR25(%r16)
846 STREG %r24, PT_GR24(%r16)
848 ldo -16(%r30),%r29 /* Reference param save area */
853 cmpib,=,n 0,%r28,intr_return /* forward */
855 /* yes, this will trap and die. */
864 * struct task_struct *_switch_to(struct task_struct *prev,
865 * struct task_struct *next)
867 * switch kernel stacks and return prev */
868 .export _switch_to, code
870 STREG %r2, -RP_OFFSET(%r30)
875 load32 _switch_to_ret, %r2
877 STREG %r2, TASK_PT_KPC(%r26)
878 LDREG TASK_PT_KPC(%r25), %r2
880 STREG %r30, TASK_PT_KSP(%r26)
881 LDREG TASK_PT_KSP(%r25), %r30
882 LDREG TASK_THREAD_INFO(%r25), %r25
887 mtctl %r0, %cr0 /* Needed for single stepping */
891 LDREG -RP_OFFSET(%r30), %r2
896 * Common rfi return path for interruptions, kernel execve, and
897 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
898 * return via this path if the signal was received when the process
899 * was running; if the process was blocked on a syscall then the
900 * normal syscall_exit path is used. All syscalls for traced
901 * proceses exit via intr_restore.
903 * XXX If any syscalls that change a processes space id ever exit
904 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
911 .export syscall_exit_rfi
914 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
915 ldo TASK_REGS(%r16),%r16
916 /* Force iaoq to userspace, as the user has had access to our current
917 * context via sigcontext. Also Filter the PSW for the same reason.
919 LDREG PT_IAOQ0(%r16),%r19
921 STREG %r19,PT_IAOQ0(%r16)
922 LDREG PT_IAOQ1(%r16),%r19
924 STREG %r19,PT_IAOQ1(%r16)
925 LDREG PT_PSW(%r16),%r19
926 load32 USER_PSW_MASK,%r1
928 load32 USER_PSW_HI_MASK,%r20
931 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
933 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
934 STREG %r19,PT_PSW(%r16)
937 * If we aren't being traced, we never saved space registers
938 * (we don't store them in the sigcontext), so set them
939 * to "proper" values now (otherwise we'll wind up restoring
940 * whatever was last stored in the task structure, which might
941 * be inconsistent if an interrupt occured while on the gateway
942 * page). Note that we may be "trashing" values the user put in
943 * them, but we don't support the user changing them.
946 STREG %r0,PT_SR2(%r16)
948 STREG %r19,PT_SR0(%r16)
949 STREG %r19,PT_SR1(%r16)
950 STREG %r19,PT_SR3(%r16)
951 STREG %r19,PT_SR4(%r16)
952 STREG %r19,PT_SR5(%r16)
953 STREG %r19,PT_SR6(%r16)
954 STREG %r19,PT_SR7(%r16)
957 /* NOTE: Need to enable interrupts incase we schedule. */
960 /* Check for software interrupts */
962 .import irq_stat,data
967 ldw TI_CPU(%r1),%r1 /* get cpu # - int */
968 /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount
969 ** irq_stat[] is defined using ____cacheline_aligned.
971 SHLREG %r1,L1_CACHE_SHIFT,%r20
972 add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
973 #endif /* CONFIG_SMP */
977 /* check for reschedule */
979 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
980 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
985 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_SIGPENDING */
986 bb,<,n %r19, 31-TIF_SIGPENDING, intr_do_signal /* forward */
990 ldo PT_FR31(%r29),%r1
994 /* inverse of virt_map */
996 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
999 /* Restore space id's and special cr's from PT_REGS
1000 * structure pointed to by r29
1004 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
1005 * It also restores r1 and r30.
1019 #ifndef CONFIG_PREEMPT
1020 # define intr_do_preempt intr_restore
1021 #endif /* !CONFIG_PREEMPT */
1023 .import schedule,code
1025 /* Only call schedule on return to userspace. If we're returning
1026 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
1027 * we jump back to intr_restore.
1029 LDREG PT_IASQ0(%r16), %r20
1030 CMPIB= 0, %r20, intr_do_preempt
1032 LDREG PT_IASQ1(%r16), %r20
1033 CMPIB= 0, %r20, intr_do_preempt
1037 ldo -16(%r30),%r29 /* Reference param save area */
1040 ldil L%intr_check_sig, %r2
1041 #ifndef CONFIG_64BIT
1044 load32 schedule, %r20
1047 ldo R%intr_check_sig(%r2), %r2
1049 /* preempt the current task on returning to kernel
1050 * mode from an interrupt, iff need_resched is set,
1051 * and preempt_count is 0. otherwise, we continue on
1052 * our merry way back to the current running task.
1054 #ifdef CONFIG_PREEMPT
1055 .import preempt_schedule_irq,code
1057 rsm PSW_SM_I, %r0 /* disable interrupts */
1059 /* current_thread_info()->preempt_count */
1061 LDREG TI_PRE_COUNT(%r1), %r19
1062 CMPIB<> 0, %r19, intr_restore /* if preempt_count > 0 */
1063 nop /* prev insn branched backwards */
1065 /* check if we interrupted a critical path */
1066 LDREG PT_PSW(%r16), %r20
1067 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1070 BL preempt_schedule_irq, %r2
1073 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
1074 #endif /* CONFIG_PREEMPT */
1076 .import do_signal,code
1079 This check is critical to having LWS
1080 working. The IASQ is zero on the gateway
1081 page and we cannot deliver any signals until
1082 we get off the gateway page.
1084 Only do signals if we are returning to user space
1086 LDREG PT_IASQ0(%r16), %r20
1087 CMPIB= 0,%r20,intr_restore /* backward */
1089 LDREG PT_IASQ1(%r16), %r20
1090 CMPIB= 0,%r20,intr_restore /* backward */
1093 copy %r0, %r24 /* unsigned long in_syscall */
1094 copy %r16, %r25 /* struct pt_regs *regs */
1096 ldo -16(%r30),%r29 /* Reference param save area */
1100 copy %r0, %r26 /* sigset_t *oldset = NULL */
1106 * External interrupts.
1115 #if 0 /* Interrupt Stack support not working yet! */
1118 /* FIXME! depi below has hardcoded idea of interrupt stack size (32k)*/
1136 ldo PT_FR0(%r29), %r24
1141 copy %r29, %r26 /* arg0 is pt_regs */
1142 copy %r29, %r16 /* save pt_regs */
1144 ldil L%intr_return, %r2
1147 ldo -16(%r30),%r29 /* Reference param save area */
1151 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1154 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1156 .export intr_save, code /* for os_hpmc */
1172 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1175 * FIXME: 1) Use a #define for the hardwired "6" below (and in
1177 * 2) Once we start executing code above 4 Gb, we need
1178 * to adjust iasq/iaoq here in the same way we
1179 * adjust isr/ior below.
1182 CMPIB=,n 6,%r26,skip_save_ior
1185 mfctl %cr20, %r16 /* isr */
1186 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1187 mfctl %cr21, %r17 /* ior */
1192 * If the interrupted code was running with W bit off (32 bit),
1193 * clear the b bits (bits 0 & 1) in the ior.
1194 * save_specials left ipsw value in r8 for us to test.
1196 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1200 * FIXME: This code has hardwired assumptions about the split
1201 * between space bits and offset bits. This will change
1202 * when we allow alternate page sizes.
1205 /* adjust isr/ior. */
1206 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1207 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1208 depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
1210 STREG %r16, PT_ISR(%r29)
1211 STREG %r17, PT_IOR(%r29)
1218 ldo PT_FR0(%r29), %r25
1223 copy %r29, %r25 /* arg1 is pt_regs */
1225 ldo -16(%r30),%r29 /* Reference param save area */
1228 ldil L%intr_check_sig, %r2
1229 copy %r25, %r16 /* save pt_regs */
1231 b handle_interruption
1232 ldo R%intr_check_sig(%r2), %r2
1236 * Note for all tlb miss handlers:
1238 * cr24 contains a pointer to the kernel address space
1241 * cr25 contains a pointer to the current user address
1242 * space page directory.
1244 * sr3 will contain the space id of the user address space
1245 * of the current running thread while that thread is
1246 * running in the kernel.
1250 * register number allocations. Note that these are all
1251 * in the shadowed registers
1254 t0 = r1 /* temporary register 0 */
1255 va = r8 /* virtual address for which the trap occured */
1256 t1 = r9 /* temporary register 1 */
1257 pte = r16 /* pte/phys page # */
1258 prot = r17 /* prot bits */
1259 spc = r24 /* space for which the trap occured */
1260 ptp = r25 /* page directory/page table pointer */
1265 space_adjust spc,va,t0
1267 space_check spc,t0,dtlb_fault
1269 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1271 update_ptep ptp,pte,t0,t1
1273 make_insert_tlb spc,pte,prot
1280 dtlb_check_alias_20w:
1281 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1289 space_adjust spc,va,t0
1291 space_check spc,t0,nadtlb_fault
1293 L3_ptep ptp,pte,t0,va,nadtlb_check_flush_20w
1295 update_ptep ptp,pte,t0,t1
1297 make_insert_tlb spc,pte,prot
1304 nadtlb_check_flush_20w:
1305 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1307 /* Insert a "flush only" translation */
1312 /* Get rid of prot bits and convert to page addr for idtlbt */
1315 extrd,u pte,56,52,pte
1326 space_check spc,t0,dtlb_fault
1328 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1330 update_ptep ptp,pte,t0,t1
1332 make_insert_tlb_11 spc,pte,prot
1334 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1337 idtlba pte,(%sr1,va)
1338 idtlbp prot,(%sr1,va)
1340 mtsp t0, %sr1 /* Restore sr1 */
1345 dtlb_check_alias_11:
1347 /* Check to see if fault is in the temporary alias region */
1349 cmpib,<>,n 0,spc,dtlb_fault /* forward */
1350 ldil L%(TMPALIAS_MAP_START),t0
1353 cmpb,<>,n t0,t1,dtlb_fault /* forward */
1354 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot
1355 depw,z prot,8,7,prot
1358 * OK, it is in the temp alias region, check whether "from" or "to".
1359 * Check "subtle" note in pacache.S re: r23/r26.
1363 or,tr %r23,%r0,pte /* If "from" use "from" page */
1364 or %r26,%r0,pte /* else "to", use "to" page */
1375 space_check spc,t0,nadtlb_fault
1377 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_11
1379 update_ptep ptp,pte,t0,t1
1381 make_insert_tlb_11 spc,pte,prot
1384 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1387 idtlba pte,(%sr1,va)
1388 idtlbp prot,(%sr1,va)
1390 mtsp t0, %sr1 /* Restore sr1 */
1395 nadtlb_check_flush_11:
1396 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1398 /* Insert a "flush only" translation */
1403 /* Get rid of prot bits and convert to page addr for idtlba */
1408 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1411 idtlba pte,(%sr1,va)
1412 idtlbp prot,(%sr1,va)
1414 mtsp t0, %sr1 /* Restore sr1 */
1420 space_adjust spc,va,t0
1422 space_check spc,t0,dtlb_fault
1424 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1426 update_ptep ptp,pte,t0,t1
1428 make_insert_tlb spc,pte,prot
1437 dtlb_check_alias_20:
1438 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1448 space_check spc,t0,nadtlb_fault
1450 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_20
1452 update_ptep ptp,pte,t0,t1
1454 make_insert_tlb spc,pte,prot
1463 nadtlb_check_flush_20:
1464 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1466 /* Insert a "flush only" translation */
1471 /* Get rid of prot bits and convert to page addr for idtlbt */
1474 extrd,u pte,56,32,pte
1484 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1485 * probei instructions. We don't want to fault for these
1486 * instructions (not only does it not make sense, it can cause
1487 * deadlocks, since some flushes are done with the mmap
1488 * semaphore held). If the translation doesn't exist, we can't
1489 * insert a translation, so have to emulate the side effects
1490 * of the instruction. Since we don't insert a translation
1491 * we can get a lot of faults during a flush loop, so it makes
1492 * sense to try to do it here with minimum overhead. We only
1493 * emulate fdc,fic,pdc,probew,prober instructions whose base
1494 * and index registers are not shadowed. We defer everything
1495 * else to the "slow" path.
1498 mfctl %cr19,%r9 /* Get iir */
1500 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1501 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1503 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1506 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1507 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1508 BL get_register,%r25
1509 extrw,u %r9,15,5,%r8 /* Get index register # */
1510 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1512 BL get_register,%r25
1513 extrw,u %r9,10,5,%r8 /* Get base register # */
1514 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1515 BL set_register,%r25
1516 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1521 or %r8,%r9,%r8 /* Set PSW_N */
1528 When there is no translation for the probe address then we
1529 must nullify the insn and return zero in the target regsiter.
1530 This will indicate to the calling code that it does not have
1531 write/read privileges to this address.
1533 This should technically work for prober and probew in PA 1.1,
1534 and also probe,r and probe,w in PA 2.0
1536 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1537 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1543 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1544 BL get_register,%r25 /* Find the target register */
1545 extrw,u %r9,31,5,%r8 /* Get target register */
1546 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */
1547 BL set_register,%r25
1548 copy %r0,%r1 /* Write zero to target register */
1549 b nadtlb_nullify /* Nullify return insn */
1557 * I miss is a little different, since we allow users to fault
1558 * on the gateway page which is in the kernel address space.
1561 space_adjust spc,va,t0
1563 space_check spc,t0,itlb_fault
1565 L3_ptep ptp,pte,t0,va,itlb_fault
1567 update_ptep ptp,pte,t0,t1
1569 make_insert_tlb spc,pte,prot
1581 space_check spc,t0,itlb_fault
1583 L2_ptep ptp,pte,t0,va,itlb_fault
1585 update_ptep ptp,pte,t0,t1
1587 make_insert_tlb_11 spc,pte,prot
1589 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1592 iitlba pte,(%sr1,va)
1593 iitlbp prot,(%sr1,va)
1595 mtsp t0, %sr1 /* Restore sr1 */
1603 space_check spc,t0,itlb_fault
1605 L2_ptep ptp,pte,t0,va,itlb_fault
1607 update_ptep ptp,pte,t0,t1
1609 make_insert_tlb spc,pte,prot
1623 space_adjust spc,va,t0
1625 space_check spc,t0,dbit_fault
1627 L3_ptep ptp,pte,t0,va,dbit_fault
1630 CMPIB=,n 0,spc,dbit_nolock_20w
1631 load32 PA(pa_dbit_lock),t0
1635 cmpib,= 0,t1,dbit_spin_20w
1640 update_dirty ptp,pte,t1
1642 make_insert_tlb spc,pte,prot
1646 CMPIB=,n 0,spc,dbit_nounlock_20w
1661 space_check spc,t0,dbit_fault
1663 L2_ptep ptp,pte,t0,va,dbit_fault
1666 CMPIB=,n 0,spc,dbit_nolock_11
1667 load32 PA(pa_dbit_lock),t0
1671 cmpib,= 0,t1,dbit_spin_11
1676 update_dirty ptp,pte,t1
1678 make_insert_tlb_11 spc,pte,prot
1680 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1683 idtlba pte,(%sr1,va)
1684 idtlbp prot,(%sr1,va)
1686 mtsp t1, %sr1 /* Restore sr1 */
1688 CMPIB=,n 0,spc,dbit_nounlock_11
1701 space_check spc,t0,dbit_fault
1703 L2_ptep ptp,pte,t0,va,dbit_fault
1706 CMPIB=,n 0,spc,dbit_nolock_20
1707 load32 PA(pa_dbit_lock),t0
1711 cmpib,= 0,t1,dbit_spin_20
1716 update_dirty ptp,pte,t1
1718 make_insert_tlb spc,pte,prot
1725 CMPIB=,n 0,spc,dbit_nounlock_20
1736 .import handle_interruption,code
1740 ldi 31,%r8 /* Use an unused code */
1758 /* Register saving semantics for system calls:
1760 %r1 clobbered by system call macro in userspace
1761 %r2 saved in PT_REGS by gateway page
1762 %r3 - %r18 preserved by C code (saved by signal code)
1763 %r19 - %r20 saved in PT_REGS by gateway page
1764 %r21 - %r22 non-standard syscall args
1765 stored in kernel stack by gateway page
1766 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1767 %r27 - %r30 saved in PT_REGS by gateway page
1768 %r31 syscall return pointer
1771 /* Floating point registers (FIXME: what do we do with these?)
1773 %fr0 - %fr3 status/exception, not preserved
1774 %fr4 - %fr7 arguments
1775 %fr8 - %fr11 not preserved by C code
1776 %fr12 - %fr21 preserved by C code
1777 %fr22 - %fr31 not preserved by C code
1780 .macro reg_save regs
1781 STREG %r3, PT_GR3(\regs)
1782 STREG %r4, PT_GR4(\regs)
1783 STREG %r5, PT_GR5(\regs)
1784 STREG %r6, PT_GR6(\regs)
1785 STREG %r7, PT_GR7(\regs)
1786 STREG %r8, PT_GR8(\regs)
1787 STREG %r9, PT_GR9(\regs)
1788 STREG %r10,PT_GR10(\regs)
1789 STREG %r11,PT_GR11(\regs)
1790 STREG %r12,PT_GR12(\regs)
1791 STREG %r13,PT_GR13(\regs)
1792 STREG %r14,PT_GR14(\regs)
1793 STREG %r15,PT_GR15(\regs)
1794 STREG %r16,PT_GR16(\regs)
1795 STREG %r17,PT_GR17(\regs)
1796 STREG %r18,PT_GR18(\regs)
1799 .macro reg_restore regs
1800 LDREG PT_GR3(\regs), %r3
1801 LDREG PT_GR4(\regs), %r4
1802 LDREG PT_GR5(\regs), %r5
1803 LDREG PT_GR6(\regs), %r6
1804 LDREG PT_GR7(\regs), %r7
1805 LDREG PT_GR8(\regs), %r8
1806 LDREG PT_GR9(\regs), %r9
1807 LDREG PT_GR10(\regs),%r10
1808 LDREG PT_GR11(\regs),%r11
1809 LDREG PT_GR12(\regs),%r12
1810 LDREG PT_GR13(\regs),%r13
1811 LDREG PT_GR14(\regs),%r14
1812 LDREG PT_GR15(\regs),%r15
1813 LDREG PT_GR16(\regs),%r16
1814 LDREG PT_GR17(\regs),%r17
1815 LDREG PT_GR18(\regs),%r18
1818 .export sys_fork_wrapper
1819 .export child_return
1821 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1822 ldo TASK_REGS(%r1),%r1
1825 STREG %r3, PT_CR27(%r1)
1827 STREG %r2,-RP_OFFSET(%r30)
1828 ldo FRAME_SIZE(%r30),%r30
1830 ldo -16(%r30),%r29 /* Reference param save area */
1833 /* These are call-clobbered registers and therefore
1834 also syscall-clobbered (we hope). */
1835 STREG %r2,PT_GR19(%r1) /* save for child */
1836 STREG %r30,PT_GR21(%r1)
1838 LDREG PT_GR30(%r1),%r25
1843 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1845 ldo -FRAME_SIZE(%r30),%r30 /* get the stackframe */
1846 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1847 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1849 LDREG PT_CR27(%r1), %r3
1853 /* strace expects syscall # to be preserved in r20 */
1856 STREG %r20,PT_GR20(%r1)
1858 /* Set the return value for the child */
1860 BL schedule_tail, %r2
1863 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE-FRAME_SIZE(%r30), %r1
1864 LDREG TASK_PT_GR19(%r1),%r2
1869 .export sys_clone_wrapper
1871 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1872 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1875 STREG %r3, PT_CR27(%r1)
1877 STREG %r2,-RP_OFFSET(%r30)
1878 ldo FRAME_SIZE(%r30),%r30
1880 ldo -16(%r30),%r29 /* Reference param save area */
1883 /* WARNING - Clobbers r19 and r21, userspace must save these! */
1884 STREG %r2,PT_GR19(%r1) /* save for child */
1885 STREG %r30,PT_GR21(%r1)
1890 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1892 .export sys_vfork_wrapper
1894 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1895 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1898 STREG %r3, PT_CR27(%r1)
1900 STREG %r2,-RP_OFFSET(%r30)
1901 ldo FRAME_SIZE(%r30),%r30
1903 ldo -16(%r30),%r29 /* Reference param save area */
1906 STREG %r2,PT_GR19(%r1) /* save for child */
1907 STREG %r30,PT_GR21(%r1)
1913 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1916 .macro execve_wrapper execve
1917 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1918 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1921 * Do we need to save/restore r3-r18 here?
1922 * I don't think so. why would new thread need old
1923 * threads registers?
1926 /* %arg0 - %arg3 are already saved for us. */
1928 STREG %r2,-RP_OFFSET(%r30)
1929 ldo FRAME_SIZE(%r30),%r30
1931 ldo -16(%r30),%r29 /* Reference param save area */
1936 ldo -FRAME_SIZE(%r30),%r30
1937 LDREG -RP_OFFSET(%r30),%r2
1939 /* If exec succeeded we need to load the args */
1942 cmpb,>>= %r28,%r1,error_\execve
1950 .export sys_execve_wrapper
1954 execve_wrapper sys_execve
1957 .export sys32_execve_wrapper
1958 .import sys32_execve
1960 sys32_execve_wrapper:
1961 execve_wrapper sys32_execve
1964 .export sys_rt_sigreturn_wrapper
1965 sys_rt_sigreturn_wrapper:
1966 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1967 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1968 /* Don't save regs, we are going to restore them from sigcontext. */
1969 STREG %r2, -RP_OFFSET(%r30)
1971 ldo FRAME_SIZE(%r30), %r30
1972 BL sys_rt_sigreturn,%r2
1973 ldo -16(%r30),%r29 /* Reference param save area */
1975 BL sys_rt_sigreturn,%r2
1976 ldo FRAME_SIZE(%r30), %r30
1979 ldo -FRAME_SIZE(%r30), %r30
1980 LDREG -RP_OFFSET(%r30), %r2
1982 /* FIXME: I think we need to restore a few more things here. */
1983 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1984 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1987 /* If the signal was received while the process was blocked on a
1988 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1989 * take us to syscall_exit_rfi and on to intr_return.
1992 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1994 .export sys_sigaltstack_wrapper
1995 sys_sigaltstack_wrapper:
1996 /* Get the user stack pointer */
1997 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1998 ldo TASK_REGS(%r1),%r24 /* get pt regs */
1999 LDREG TASK_PT_GR30(%r24),%r24
2000 STREG %r2, -RP_OFFSET(%r30)
2002 ldo FRAME_SIZE(%r30), %r30
2003 b,l do_sigaltstack,%r2
2004 ldo -16(%r30),%r29 /* Reference param save area */
2006 bl do_sigaltstack,%r2
2007 ldo FRAME_SIZE(%r30), %r30
2010 ldo -FRAME_SIZE(%r30), %r30
2011 LDREG -RP_OFFSET(%r30), %r2
2016 .export sys32_sigaltstack_wrapper
2017 sys32_sigaltstack_wrapper:
2018 /* Get the user stack pointer */
2019 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r24
2020 LDREG TASK_PT_GR30(%r24),%r24
2021 STREG %r2, -RP_OFFSET(%r30)
2022 ldo FRAME_SIZE(%r30), %r30
2023 b,l do_sigaltstack32,%r2
2024 ldo -16(%r30),%r29 /* Reference param save area */
2026 ldo -FRAME_SIZE(%r30), %r30
2027 LDREG -RP_OFFSET(%r30), %r2
2032 .export sys_rt_sigsuspend_wrapper
2033 sys_rt_sigsuspend_wrapper:
2034 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
2035 ldo TASK_REGS(%r1),%r24
2038 STREG %r2, -RP_OFFSET(%r30)
2040 ldo FRAME_SIZE(%r30), %r30
2041 b,l sys_rt_sigsuspend,%r2
2042 ldo -16(%r30),%r29 /* Reference param save area */
2044 bl sys_rt_sigsuspend,%r2
2045 ldo FRAME_SIZE(%r30), %r30
2048 ldo -FRAME_SIZE(%r30), %r30
2049 LDREG -RP_OFFSET(%r30), %r2
2051 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
2052 ldo TASK_REGS(%r1),%r1
2058 .export syscall_exit
2061 /* NOTE: HP-UX syscalls also come through here
2062 * after hpux_syscall_exit fixes up return
2065 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
2066 * via syscall_exit_rfi if the signal was received while the process
2070 /* save return value now */
2073 LDREG TI_TASK(%r1),%r1
2074 STREG %r28,TASK_PT_GR28(%r1)
2078 /* <linux/personality.h> cannot be easily included */
2079 #define PER_HPUX 0x10
2080 LDREG TASK_PERSONALITY(%r1),%r19
2082 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
2083 ldo -PER_HPUX(%r19), %r19
2086 /* Save other hpux returns if personality is PER_HPUX */
2087 STREG %r22,TASK_PT_GR22(%r1)
2088 STREG %r29,TASK_PT_GR29(%r1)
2091 #endif /* CONFIG_HPUX */
2093 /* Seems to me that dp could be wrong here, if the syscall involved
2094 * calling a module, and nothing got round to restoring dp on return.
2100 /* Check for software interrupts */
2102 .import irq_stat,data
2104 load32 irq_stat,%r19
2107 /* sched.h: int processor */
2108 /* %r26 is used as scratch register to index into irq_stat[] */
2109 ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */
2111 /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */
2112 SHLREG %r26,L1_CACHE_SHIFT,%r20
2113 add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
2114 #endif /* CONFIG_SMP */
2116 syscall_check_resched:
2118 /* check for reschedule */
2120 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
2121 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
2124 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* get ti flags */
2125 bb,<,n %r19, 31-TIF_SIGPENDING, syscall_do_signal /* forward */
2128 /* Are we being ptraced? */
2129 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2131 LDREG TASK_PTRACE(%r1), %r19
2132 bb,< %r19,31,syscall_restore_rfi
2135 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
2138 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
2141 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
2142 LDREG TASK_PT_GR19(%r1),%r19
2143 LDREG TASK_PT_GR20(%r1),%r20
2144 LDREG TASK_PT_GR21(%r1),%r21
2145 LDREG TASK_PT_GR22(%r1),%r22
2146 LDREG TASK_PT_GR23(%r1),%r23
2147 LDREG TASK_PT_GR24(%r1),%r24
2148 LDREG TASK_PT_GR25(%r1),%r25
2149 LDREG TASK_PT_GR26(%r1),%r26
2150 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
2151 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
2152 LDREG TASK_PT_GR29(%r1),%r29
2153 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
2155 /* NOTE: We use rsm/ssm pair to make this operation atomic */
2157 LDREG TASK_PT_GR30(%r1),%r30 /* restore user sp */
2158 mfsp %sr3,%r1 /* Get users space id */
2159 mtsp %r1,%sr7 /* Restore sr7 */
2162 /* Set sr2 to zero for userspace syscalls to work. */
2164 mtsp %r1,%sr4 /* Restore sr4 */
2165 mtsp %r1,%sr5 /* Restore sr5 */
2166 mtsp %r1,%sr6 /* Restore sr6 */
2168 depi 3,31,2,%r31 /* ensure return to user mode. */
2171 /* decide whether to reset the wide mode bit
2173 * For a syscall, the W bit is stored in the lowest bit
2174 * of sp. Extract it and reset W if it is zero */
2175 extrd,u,*<> %r30,63,1,%r1
2177 /* now reset the lowest bit of sp if it was set */
2180 be,n 0(%sr3,%r31) /* return to user space */
2182 /* We have to return via an RFI, so that PSW T and R bits can be set
2184 * This sets up pt_regs so we can return via intr_restore, which is not
2185 * the most efficient way of doing things, but it works.
2187 syscall_restore_rfi:
2188 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
2189 mtctl %r2,%cr0 /* for immediate trap */
2190 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
2191 ldi 0x0b,%r20 /* Create new PSW */
2192 depi -1,13,1,%r20 /* C, Q, D, and I bits */
2194 /* The values of PA_SINGLESTEP_BIT and PA_BLOCKSTEP_BIT are
2195 * set in include/linux/ptrace.h and converted to PA bitmap
2196 * numbers in asm-offsets.c */
2198 /* if ((%r19.PA_SINGLESTEP_BIT)) { %r20.27=1} */
2199 extru,= %r19,PA_SINGLESTEP_BIT,1,%r0
2200 depi -1,27,1,%r20 /* R bit */
2202 /* if ((%r19.PA_BLOCKSTEP_BIT)) { %r20.7=1} */
2203 extru,= %r19,PA_BLOCKSTEP_BIT,1,%r0
2204 depi -1,7,1,%r20 /* T bit */
2206 STREG %r20,TASK_PT_PSW(%r1)
2208 /* Always store space registers, since sr3 can be changed (e.g. fork) */
2211 STREG %r25,TASK_PT_SR3(%r1)
2212 STREG %r25,TASK_PT_SR4(%r1)
2213 STREG %r25,TASK_PT_SR5(%r1)
2214 STREG %r25,TASK_PT_SR6(%r1)
2215 STREG %r25,TASK_PT_SR7(%r1)
2216 STREG %r25,TASK_PT_IASQ0(%r1)
2217 STREG %r25,TASK_PT_IASQ1(%r1)
2220 /* Now if old D bit is clear, it means we didn't save all registers
2221 * on syscall entry, so do that now. This only happens on TRACEME
2222 * calls, or if someone attached to us while we were on a syscall.
2223 * We could make this more efficient by not saving r3-r18, but
2224 * then we wouldn't be able to use the common intr_restore path.
2225 * It is only for traced processes anyway, so performance is not
2228 bb,< %r2,30,pt_regs_ok /* Branch if D set */
2229 ldo TASK_REGS(%r1),%r25
2230 reg_save %r25 /* Save r3 to r18 */
2232 /* Save the current sr */
2234 STREG %r2,TASK_PT_SR0(%r1)
2236 /* Save the scratch sr */
2238 STREG %r2,TASK_PT_SR1(%r1)
2240 /* sr2 should be set to zero for userspace syscalls */
2241 STREG %r0,TASK_PT_SR2(%r1)
2244 LDREG TASK_PT_GR31(%r1),%r2
2245 depi 3,31,2,%r2 /* ensure return to user mode. */
2246 STREG %r2,TASK_PT_IAOQ0(%r1)
2248 STREG %r2,TASK_PT_IAOQ1(%r1)
2253 .import schedule,code
2257 ldo -16(%r30),%r29 /* Reference param save area */
2261 b syscall_check_bh /* if resched, we start over again */
2264 .import do_signal,code
2266 /* Save callee-save registers (for sigcontext).
2267 FIXME: After this point the process structure should be
2268 consistent with all the relevant state of the process
2269 before the syscall. We need to verify this. */
2270 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2271 ldo TASK_REGS(%r1), %r25 /* struct pt_regs *regs */
2274 ldi 1, %r24 /* unsigned long in_syscall */
2277 ldo -16(%r30),%r29 /* Reference param save area */
2280 copy %r0, %r26 /* sigset_t *oldset = NULL */
2282 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2283 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
2286 b,n syscall_check_sig
2289 * get_register is used by the non access tlb miss handlers to
2290 * copy the value of the general register specified in r8 into
2291 * r1. This routine can't be used for shadowed registers, since
2292 * the rfir will restore the original value. So, for the shadowed
2293 * registers we put a -1 into r1 to indicate that the register
2294 * should not be used (the register being copied could also have
2295 * a -1 in it, but that is OK, it just means that we will have
2296 * to use the slow path instead).
2302 bv %r0(%r25) /* r0 */
2304 bv %r0(%r25) /* r1 - shadowed */
2306 bv %r0(%r25) /* r2 */
2308 bv %r0(%r25) /* r3 */
2310 bv %r0(%r25) /* r4 */
2312 bv %r0(%r25) /* r5 */
2314 bv %r0(%r25) /* r6 */
2316 bv %r0(%r25) /* r7 */
2318 bv %r0(%r25) /* r8 - shadowed */
2320 bv %r0(%r25) /* r9 - shadowed */
2322 bv %r0(%r25) /* r10 */
2324 bv %r0(%r25) /* r11 */
2326 bv %r0(%r25) /* r12 */
2328 bv %r0(%r25) /* r13 */
2330 bv %r0(%r25) /* r14 */
2332 bv %r0(%r25) /* r15 */
2334 bv %r0(%r25) /* r16 - shadowed */
2336 bv %r0(%r25) /* r17 - shadowed */
2338 bv %r0(%r25) /* r18 */
2340 bv %r0(%r25) /* r19 */
2342 bv %r0(%r25) /* r20 */
2344 bv %r0(%r25) /* r21 */
2346 bv %r0(%r25) /* r22 */
2348 bv %r0(%r25) /* r23 */
2350 bv %r0(%r25) /* r24 - shadowed */
2352 bv %r0(%r25) /* r25 - shadowed */
2354 bv %r0(%r25) /* r26 */
2356 bv %r0(%r25) /* r27 */
2358 bv %r0(%r25) /* r28 */
2360 bv %r0(%r25) /* r29 */
2362 bv %r0(%r25) /* r30 */
2364 bv %r0(%r25) /* r31 */
2368 * set_register is used by the non access tlb miss handlers to
2369 * copy the value of r1 into the general register specified in
2376 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2378 bv %r0(%r25) /* r1 */
2380 bv %r0(%r25) /* r2 */
2382 bv %r0(%r25) /* r3 */
2384 bv %r0(%r25) /* r4 */
2386 bv %r0(%r25) /* r5 */
2388 bv %r0(%r25) /* r6 */
2390 bv %r0(%r25) /* r7 */
2392 bv %r0(%r25) /* r8 */
2394 bv %r0(%r25) /* r9 */
2396 bv %r0(%r25) /* r10 */
2398 bv %r0(%r25) /* r11 */
2400 bv %r0(%r25) /* r12 */
2402 bv %r0(%r25) /* r13 */
2404 bv %r0(%r25) /* r14 */
2406 bv %r0(%r25) /* r15 */
2408 bv %r0(%r25) /* r16 */
2410 bv %r0(%r25) /* r17 */
2412 bv %r0(%r25) /* r18 */
2414 bv %r0(%r25) /* r19 */
2416 bv %r0(%r25) /* r20 */
2418 bv %r0(%r25) /* r21 */
2420 bv %r0(%r25) /* r22 */
2422 bv %r0(%r25) /* r23 */
2424 bv %r0(%r25) /* r24 */
2426 bv %r0(%r25) /* r25 */
2428 bv %r0(%r25) /* r26 */
2430 bv %r0(%r25) /* r27 */
2432 bv %r0(%r25) /* r28 */
2434 bv %r0(%r25) /* r29 */
2436 bv %r0(%r25) /* r30 */
2438 bv %r0(%r25) /* r31 */