2 * Parisc performance counters
3 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
5 * This code is derived, with permission, from HP/UX sources.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Edited comment from original sources:
25 * This driver programs the PCX-U/PCX-W performance counters
26 * on the PA-RISC 2.0 chips. The driver keeps all images now
27 * internally to the kernel to hopefully eliminate the possiblity
28 * of a bad image halting the CPU. Also, there are different
29 * images for the PCX-W and later chips vs the PCX-U chips.
31 * Only 1 process is allowed to access the driver at any time,
32 * so the only protection that is needed is at open and close.
33 * A variable "perf_enabled" is used to hold the state of the
34 * driver. The spinlock "perf_lock" is used to protect the
35 * modification of the state during open/close operations so
36 * multiple processes don't get into the driver simultaneously.
38 * This driver accesses the processor directly vs going through
39 * the PDC INTRIGUE calls. This is done to eliminate bugs introduced
40 * in various PDC revisions. The code is much more maintainable
41 * and reliable this way vs having to debug on every version of PDC
45 #include <linux/config.h>
46 #include <linux/init.h>
47 #include <linux/proc_fs.h>
48 #include <linux/miscdevice.h>
49 #include <linux/spinlock.h>
51 #include <asm/uaccess.h>
53 #include <asm/parisc-device.h>
54 #include <asm/processor.h>
55 #include <asm/runway.h>
56 #include <asm/io.h> /* for __raw_read() */
58 #include "perf_images.h"
60 #define MAX_RDR_WORDS 24
61 #define PERF_VERSION 2 /* derived from hpux's PI v2 interface */
63 /* definition of RDR regs */
67 uint8_t write_control;
70 static int perf_processor_interface = UNKNOWN_INTF;
71 static int perf_enabled = 0;
72 static spinlock_t perf_lock;
73 struct parisc_device *cpu_device = NULL;
75 /* RDRs to write for PCX-W */
76 static int perf_rdrs_W[] =
77 { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
79 /* RDRs to write for PCX-U */
80 static int perf_rdrs_U[] =
81 { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
83 /* RDR register descriptions for PCX-W */
84 static struct rdr_tbl_ent perf_rdr_tbl_W[] = {
85 { 19, 1, 8 }, /* RDR 0 */
86 { 16, 1, 16 }, /* RDR 1 */
87 { 72, 2, 0 }, /* RDR 2 */
88 { 81, 2, 0 }, /* RDR 3 */
89 { 328, 6, 0 }, /* RDR 4 */
90 { 160, 3, 0 }, /* RDR 5 */
91 { 336, 6, 0 }, /* RDR 6 */
92 { 164, 3, 0 }, /* RDR 7 */
93 { 0, 0, 0 }, /* RDR 8 */
94 { 35, 1, 0 }, /* RDR 9 */
95 { 6, 1, 0 }, /* RDR 10 */
96 { 18, 1, 0 }, /* RDR 11 */
97 { 13, 1, 0 }, /* RDR 12 */
98 { 8, 1, 0 }, /* RDR 13 */
99 { 8, 1, 0 }, /* RDR 14 */
100 { 8, 1, 0 }, /* RDR 15 */
101 { 1530, 24, 0 }, /* RDR 16 */
102 { 16, 1, 0 }, /* RDR 17 */
103 { 4, 1, 0 }, /* RDR 18 */
104 { 0, 0, 0 }, /* RDR 19 */
105 { 152, 3, 24 }, /* RDR 20 */
106 { 152, 3, 24 }, /* RDR 21 */
107 { 233, 4, 48 }, /* RDR 22 */
108 { 233, 4, 48 }, /* RDR 23 */
109 { 71, 2, 0 }, /* RDR 24 */
110 { 71, 2, 0 }, /* RDR 25 */
111 { 11, 1, 0 }, /* RDR 26 */
112 { 18, 1, 0 }, /* RDR 27 */
113 { 128, 2, 0 }, /* RDR 28 */
114 { 0, 0, 0 }, /* RDR 29 */
115 { 16, 1, 0 }, /* RDR 30 */
116 { 16, 1, 0 }, /* RDR 31 */
119 /* RDR register descriptions for PCX-U */
120 static struct rdr_tbl_ent perf_rdr_tbl_U[] = {
121 { 19, 1, 8 }, /* RDR 0 */
122 { 32, 1, 16 }, /* RDR 1 */
123 { 20, 1, 0 }, /* RDR 2 */
124 { 0, 0, 0 }, /* RDR 3 */
125 { 344, 6, 0 }, /* RDR 4 */
126 { 176, 3, 0 }, /* RDR 5 */
127 { 336, 6, 0 }, /* RDR 6 */
128 { 0, 0, 0 }, /* RDR 7 */
129 { 0, 0, 0 }, /* RDR 8 */
130 { 0, 0, 0 }, /* RDR 9 */
131 { 28, 1, 0 }, /* RDR 10 */
132 { 33, 1, 0 }, /* RDR 11 */
133 { 0, 0, 0 }, /* RDR 12 */
134 { 230, 4, 0 }, /* RDR 13 */
135 { 32, 1, 0 }, /* RDR 14 */
136 { 128, 2, 0 }, /* RDR 15 */
137 { 1494, 24, 0 }, /* RDR 16 */
138 { 18, 1, 0 }, /* RDR 17 */
139 { 4, 1, 0 }, /* RDR 18 */
140 { 0, 0, 0 }, /* RDR 19 */
141 { 158, 3, 24 }, /* RDR 20 */
142 { 158, 3, 24 }, /* RDR 21 */
143 { 194, 4, 48 }, /* RDR 22 */
144 { 194, 4, 48 }, /* RDR 23 */
145 { 71, 2, 0 }, /* RDR 24 */
146 { 71, 2, 0 }, /* RDR 25 */
147 { 28, 1, 0 }, /* RDR 26 */
148 { 33, 1, 0 }, /* RDR 27 */
149 { 88, 2, 0 }, /* RDR 28 */
150 { 32, 1, 0 }, /* RDR 29 */
151 { 24, 1, 0 }, /* RDR 30 */
152 { 16, 1, 0 }, /* RDR 31 */
156 * A non-zero write_control in the above tables is a byte offset into
159 static uint64_t perf_bitmasks[] = {
160 0x0000000000000000, /* first dbl word must be zero */
161 0xfdffe00000000000, /* RDR0 bitmask */
162 0x003f000000000000, /* RDR1 bitmask */
163 0x00ffffffffffffff, /* RDR20-RDR21 bitmask (152 bits) */
166 0xffffffffffffffff, /* RDR22-RDR23 bitmask (233 bits) */
173 * Write control bitmasks for Pa-8700 processor given
174 * somethings have changed slightly.
176 static uint64_t perf_bitmasks_piranha[] = {
177 0x0000000000000000, /* first dbl word must be zero */
178 0xfdffe00000000000, /* RDR0 bitmask */
179 0x003f000000000000, /* RDR1 bitmask */
180 0x00ffffffffffffff, /* RDR20-RDR21 bitmask (158 bits) */
183 0xffffffffffffffff, /* RDR22-RDR23 bitmask (210 bits) */
189 static uint64_t *bitmask_array; /* array of bitmasks to use */
191 /******************************************************************************
192 * Function Prototypes
193 *****************************************************************************/
194 static int perf_config(uint32_t *image_ptr);
195 static int perf_release(struct inode *inode, struct file *file);
196 static int perf_open(struct inode *inode, struct file *file);
197 static ssize_t perf_read(struct file *file, char *buf, size_t cnt, loff_t *ppos);
198 static ssize_t perf_write(struct file *file, const char *buf, size_t count,
200 static int perf_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
202 static void perf_start_counters(void);
203 static int perf_stop_counters(uint32_t *raddr);
204 static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
205 static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);
206 static int perf_rdr_clear(uint32_t rdr_num);
207 static int perf_write_image(uint64_t *memaddr);
208 static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
210 /* External Assembly Routines */
211 extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
212 extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);
213 extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer);
214 extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer);
215 extern void perf_intrigue_enable_perf_counters (void);
216 extern void perf_intrigue_disable_perf_counters (void);
218 /******************************************************************************
219 * Function Definitions
220 *****************************************************************************/
226 * Configure the cpu with a given data image. First turn off the counters,
227 * then download the image, then turn the counters back on.
229 static int perf_config(uint32_t *image_ptr)
234 /* Stop the counters*/
235 error = perf_stop_counters(raddr);
237 printk("perf_config: perf_stop_counters = %ld\n", error);
241 printk("Preparing to write image\n");
242 /* Write the image to the chip */
243 error = perf_write_image((uint64_t *)image_ptr);
245 printk("perf_config: DOWNLOAD = %ld\n", error);
249 printk("Preparing to start counters\n");
251 /* Start the counters */
252 perf_start_counters();
254 return sizeof(uint32_t);
258 * Open the device and initialize all of its memory. The device is only
259 * opened once, but can be "queried" by multiple processes that know its
262 static int perf_open(struct inode *inode, struct file *file)
264 spin_lock(&perf_lock);
266 spin_unlock(&perf_lock);
270 spin_unlock(&perf_lock);
278 static int perf_release(struct inode *inode, struct file *file)
280 spin_lock(&perf_lock);
282 spin_unlock(&perf_lock);
288 * Read does nothing for this driver
290 static ssize_t perf_read(struct file *file, char *buf, size_t cnt, loff_t *ppos)
298 * This routine downloads the image to the chip. It must be
299 * called on the processor that the download should happen
302 static ssize_t perf_write(struct file *file, const char *buf, size_t count,
308 uint32_t interface_type;
311 if (perf_processor_interface == ONYX_INTF)
312 image_size = PCXU_IMAGE_SIZE;
313 else if (perf_processor_interface == CUDA_INTF)
314 image_size = PCXW_IMAGE_SIZE;
318 if (!capable(CAP_SYS_ADMIN))
321 if (count != sizeof(uint32_t))
324 if ((err = copy_from_user(&image_type, buf, sizeof(uint32_t))) != 0)
327 /* Get the interface type and test type */
328 interface_type = (image_type >> 16) & 0xffff;
329 test = (image_type & 0xffff);
331 /* Make sure everything makes sense */
333 /* First check the machine type is correct for
334 the requested image */
335 if (((perf_processor_interface == CUDA_INTF) &&
336 (interface_type != CUDA_INTF)) ||
337 ((perf_processor_interface == ONYX_INTF) &&
338 (interface_type != ONYX_INTF)))
341 /* Next check to make sure the requested image
343 if (((interface_type == CUDA_INTF) &&
344 (test >= MAX_CUDA_IMAGES)) ||
345 ((interface_type == ONYX_INTF) &&
346 (test >= MAX_ONYX_IMAGES)))
349 /* Copy the image into the processor */
350 if (interface_type == CUDA_INTF)
351 return perf_config(cuda_images[test]);
353 return perf_config(onyx_images[test]);
359 * Patch the images that need to know the IVA addresses.
361 static void perf_patch_images(void)
365 * NOTE: this routine is VERY specific to the current TLB image.
366 * If the image is changed, this routine might also need to be changed.
368 extern void $i_itlb_miss_2_0();
369 extern void $i_dtlb_miss_2_0();
370 extern void PA2_0_iva();
373 * We can only use the lower 32-bits, the upper 32-bits should be 0
374 * anyway given this is in the kernel
376 uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0);
377 uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0);
378 uint32_t IVAaddress = (uint32_t)&PA2_0_iva;
380 if (perf_processor_interface == ONYX_INTF) {
381 /* clear last 2 bytes */
382 onyx_images[TLBMISS][15] &= 0xffffff00;
384 onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
385 onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00;
386 onyx_images[TLBMISS][17] = itlb_addr;
388 /* clear last 2 bytes */
389 onyx_images[TLBHANDMISS][15] &= 0xffffff00;
391 onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
392 onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00;
393 onyx_images[TLBHANDMISS][17] = itlb_addr;
395 /* clear last 2 bytes */
396 onyx_images[BIG_CPI][15] &= 0xffffff00;
398 onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24));
399 onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00;
400 onyx_images[BIG_CPI][17] = itlb_addr;
402 onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */
403 onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */
404 onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00;
407 } else if (perf_processor_interface == CUDA_INTF) {
409 cuda_images[TLBMISS][16] =
410 (cuda_images[TLBMISS][16]&0xffff0000) |
411 ((dtlb_addr >> 8)&0x0000ffff);
412 cuda_images[TLBMISS][17] =
413 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
414 cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000;
416 cuda_images[TLBHANDMISS][16] =
417 (cuda_images[TLBHANDMISS][16]&0xffff0000) |
418 ((dtlb_addr >> 8)&0x0000ffff);
419 cuda_images[TLBHANDMISS][17] =
420 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
421 cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000;
423 cuda_images[BIG_CPI][16] =
424 (cuda_images[BIG_CPI][16]&0xffff0000) |
425 ((dtlb_addr >> 8)&0x0000ffff);
426 cuda_images[BIG_CPI][17] =
427 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
428 cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000;
438 * All routines effect the processor that they are executed on. Thus you
439 * must be running on the processor that you wish to change.
442 static int perf_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
451 /* Start the counters */
452 perf_start_counters();
456 error_start = perf_stop_counters(raddr);
457 if (error_start != 0) {
458 printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start);
462 /* copy out the Counters */
463 if (copy_to_user((void *)arg, raddr,
464 sizeof (raddr)) != 0) {
469 case PA_PERF_VERSION:
470 /* Return the version # */
471 return put_user(PERF_VERSION, (int *)arg);
479 static struct file_operations perf_fops = {
485 .release = perf_release
488 static struct miscdevice perf_dev = {
495 * Initialize the module
497 static int __init perf_init(void)
501 /* Determine correct processor interface to use */
502 bitmask_array = perf_bitmasks;
504 if (boot_cpu_data.cpu_type == pcxu ||
505 boot_cpu_data.cpu_type == pcxu_) {
506 perf_processor_interface = ONYX_INTF;
507 } else if (boot_cpu_data.cpu_type == pcxw ||
508 boot_cpu_data.cpu_type == pcxw_ ||
509 boot_cpu_data.cpu_type == pcxw2) {
510 perf_processor_interface = CUDA_INTF;
511 if (boot_cpu_data.cpu_type == pcxw2)
512 bitmask_array = perf_bitmasks_piranha;
514 perf_processor_interface = UNKNOWN_INTF;
515 printk("Performance monitoring counters not supported on this processor\n");
519 ret = misc_register(&perf_dev);
521 printk(KERN_ERR "Performance monitoring counters: "
522 "cannot register misc device.\n");
526 /* Patch the images to match the system */
529 spin_lock_init(&perf_lock);
531 /* TODO: this only lets us access the first cpu.. what to do for SMP? */
532 cpu_device = cpu_data[0].dev;
533 printk("Performance monitoring counters enabled for %s\n",
534 cpu_data[0].dev->name);
540 * perf_start_counters(void)
542 * Start the counters.
544 static void perf_start_counters(void)
546 /* Enable performance monitor counters */
547 perf_intrigue_enable_perf_counters();
553 * Stop the performance counters and save counts
554 * in a per_processor array.
556 static int perf_stop_counters(uint32_t *raddr)
558 uint64_t userbuf[MAX_RDR_WORDS];
560 /* Disable performance counters */
561 perf_intrigue_disable_perf_counters();
563 if (perf_processor_interface == ONYX_INTF) {
568 if (!perf_rdr_read_ubuf(16, userbuf))
571 /* Counter0 is bits 1398 thru 1429 */
572 tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000;
573 tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff;
574 /* OR sticky0 (bit 1430) to counter0 bit 32 */
575 tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000;
576 raddr[0] = (uint32_t)tmp64;
578 /* Counter1 is bits 1431 thru 1462 */
579 tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff;
580 /* OR sticky1 (bit 1463) to counter1 bit 32 */
581 tmp64 |= (userbuf[22] << 23) & 0x0000000080000000;
582 raddr[1] = (uint32_t)tmp64;
584 /* Counter2 is bits 1464 thru 1495 */
585 tmp64 = (userbuf[22] << 24) & 0x00000000ff000000;
586 tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff;
587 /* OR sticky2 (bit 1496) to counter2 bit 32 */
588 tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000;
589 raddr[2] = (uint32_t)tmp64;
591 /* Counter3 is bits 1497 thru 1528 */
592 tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff;
593 /* OR sticky3 (bit 1529) to counter3 bit 32 */
594 tmp64 |= (userbuf[23] << 25) & 0x0000000080000000;
595 raddr[3] = (uint32_t)tmp64;
598 * Zero out the counters
602 * The counters and sticky-bits comprise the last 132 bits
603 * (1398 - 1529) of RDR16 on a U chip. We'll zero these
604 * out the easy way: zero out last 10 bits of dword 21,
605 * all of dword 22 and 58 bits (plus 6 don't care bits) of
608 userbuf[21] &= 0xfffffffffffffc00; /* 0 to last 10 bits */
613 * Write back the zero'ed bytes + the image given
614 * the read was destructive.
616 perf_rdr_write(16, userbuf);
620 * Read RDR-15 which contains the counters and sticky bits
622 if (!perf_rdr_read_ubuf(15, userbuf)) {
627 * Clear out the counters
634 raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL);
635 raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL);
636 raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL);
637 raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL);
646 * Retrieve a pointer to the description of what this
649 static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)
651 if (perf_processor_interface == ONYX_INTF) {
652 return &perf_rdr_tbl_U[rdr_num];
654 return &perf_rdr_tbl_W[rdr_num];
661 * Read the RDR value into the buffer specified.
663 static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer)
665 uint64_t data, data_mask = 0;
666 uint32_t width, xbits, i;
667 struct rdr_tbl_ent *tentry;
669 tentry = perf_rdr_get_entry(rdr_num);
670 if ((width = tentry->width) == 0)
673 /* Clear out buffer */
674 i = tentry->num_words;
679 /* Check for bits an even number of 64 */
680 if ((xbits = width & 0x03f) != 0) {
682 data_mask <<= (64 - xbits);
686 /* Grab all of the data */
687 i = tentry->num_words;
690 if (perf_processor_interface == ONYX_INTF) {
691 data = perf_rdr_shift_in_U(rdr_num, width);
693 data = perf_rdr_shift_in_W(rdr_num, width);
696 buffer[i] |= (data << (64 - xbits));
698 buffer[i-1] |= ((data >> xbits) & data_mask);
711 * Zero out the given RDR register
713 static int perf_rdr_clear(uint32_t rdr_num)
715 struct rdr_tbl_ent *tentry;
718 tentry = perf_rdr_get_entry(rdr_num);
720 if (tentry->width == 0) {
724 i = tentry->num_words;
726 if (perf_processor_interface == ONYX_INTF) {
727 perf_rdr_shift_out_U(rdr_num, 0UL);
729 perf_rdr_shift_out_W(rdr_num, 0UL);
740 * Write the given image out to the processor
742 static int perf_write_image(uint64_t *memaddr)
744 uint64_t buffer[MAX_RDR_WORDS];
747 uint32_t *intrigue_rdr;
748 uint64_t *intrigue_bitmask, tmp64, proc_hpa;
749 struct rdr_tbl_ent *tentry;
752 /* Clear out counters */
753 if (perf_processor_interface == ONYX_INTF) {
757 /* Toggle performance monitor */
758 perf_intrigue_enable_perf_counters();
759 perf_intrigue_disable_perf_counters();
761 intrigue_rdr = perf_rdrs_U;
764 intrigue_rdr = perf_rdrs_W;
768 while (*intrigue_rdr != -1) {
769 tentry = perf_rdr_get_entry(*intrigue_rdr);
770 perf_rdr_read_ubuf(*intrigue_rdr, buffer);
772 dwords = tentry->num_words;
773 if (tentry->write_control) {
774 intrigue_bitmask = &bitmask_array[tentry->write_control >> 3];
776 tmp64 = *intrigue_bitmask & *memaddr++;
777 tmp64 |= (~(*intrigue_bitmask++)) & *bptr;
782 *bptr++ = *memaddr++;
786 perf_rdr_write(*intrigue_rdr, buffer);
791 * Now copy out the Runway stuff which is not in RDRs
794 if (cpu_device == NULL)
796 printk(KERN_ERR "write_image: cpu_device not yet initialized!\n");
800 proc_hpa = cpu_device->hpa;
802 /* Merge intrigue bits into Runway STATUS 0 */
803 tmp64 = __raw_readq(proc_hpa + RUNWAY_STATUS) & 0xffecffffffffffff;
804 __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000), proc_hpa + RUNWAY_STATUS);
806 /* Write RUNWAY DEBUG registers */
807 for (i = 0; i < 8; i++) {
808 __raw_writeq(*memaddr++, proc_hpa + RUNWAY_DEBUG + i);
817 * Write the given RDR register with the contents
818 * of the given buffer.
820 static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)
822 struct rdr_tbl_ent *tentry;
825 printk("perf_rdr_write\n");
826 tentry = perf_rdr_get_entry(rdr_num);
827 if (tentry->width == 0) { return; }
829 i = tentry->num_words;
831 if (perf_processor_interface == ONYX_INTF) {
832 perf_rdr_shift_out_U(rdr_num, buffer[i]);
834 perf_rdr_shift_out_W(rdr_num, buffer[i]);
837 printk("perf_rdr_write done\n");
840 module_init(perf_init);