2 * Unaligned memory access handler
4 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
5 * Significantly tweaked by LaMont Jones <lamont@debian.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
27 /* #define DEBUG_UNALIGNED 1 */
29 #ifdef DEBUG_UNALIGNED
30 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __FUNCTION__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
32 #define DPRINTF(fmt, args...)
41 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
42 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
43 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
44 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
45 #define OPCODE4(a) ((a)<<26)
46 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
47 #define OPCODE2_MASK OPCODE2(0x3f,1)
48 #define OPCODE3_MASK OPCODE3(0x3f,1)
49 #define OPCODE4_MASK OPCODE4(0x3f)
51 /* skip LDB - never unaligned (index) */
52 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
53 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
54 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
55 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
56 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
57 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
58 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
59 /* skip LDB - never unaligned (short) */
60 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
61 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
62 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
63 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
64 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
65 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
66 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
67 /* skip STB - never unaligned */
68 #define OPCODE_STH OPCODE1(0x03,1,0x9)
69 #define OPCODE_STW OPCODE1(0x03,1,0xa)
70 #define OPCODE_STD OPCODE1(0x03,1,0xb)
71 /* skip STBY - never unaligned */
72 /* skip STDBY - never unaligned */
73 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
74 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
76 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
77 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
78 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
79 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
80 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
81 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
82 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
83 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
84 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
85 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
86 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
87 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
89 #define OPCODE_LDD_L OPCODE2(0x14,0)
90 #define OPCODE_FLDD_L OPCODE2(0x14,1)
91 #define OPCODE_STD_L OPCODE2(0x1c,0)
92 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
94 #define OPCODE_LDW_M OPCODE3(0x17,1)
95 #define OPCODE_FLDW_L OPCODE3(0x17,0)
96 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
97 #define OPCODE_STW_M OPCODE3(0x1f,1)
99 #define OPCODE_LDH_L OPCODE4(0x11)
100 #define OPCODE_LDW_L OPCODE4(0x12)
101 #define OPCODE_LDWM OPCODE4(0x13)
102 #define OPCODE_STH_L OPCODE4(0x19)
103 #define OPCODE_STW_L OPCODE4(0x1A)
104 #define OPCODE_STWM OPCODE4(0x1B)
106 #define MAJOR_OP(i) (((i)>>26)&0x3f)
107 #define R1(i) (((i)>>21)&0x1f)
108 #define R2(i) (((i)>>16)&0x1f)
109 #define R3(i) ((i)&0x1f)
110 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
111 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
112 #define IM5_2(i) IM((i)>>16,5)
113 #define IM5_3(i) IM((i),5)
114 #define IM14(i) IM((i),14)
116 #define ERR_NOTHANDLED -1
117 #define ERR_PAGEFAULT -2
119 int unaligned_enabled = 1;
121 void die_if_kernel (char *str, struct pt_regs *regs, long err);
123 static int emulate_ldh(struct pt_regs *regs, int toreg)
125 unsigned long saddr = regs->ior;
126 unsigned long val = 0;
129 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
130 regs->isr, regs->ior, toreg);
132 __asm__ __volatile__ (
134 "1: ldbs 0(%%sr1,%3), %%r20\n"
135 "2: ldbs 1(%%sr1,%3), %0\n"
136 " depw %%r20, 23, 24, %0\n"
137 " cmpclr,= %%r0, %%r0, %1\n"
138 "3: ldo -2(%%r0), %1\n"
139 " .section __ex_table,\"a\"\n"
141 " .dword 1b,(3b-1b)\n"
142 " .dword 2b,(3b-2b)\n"
144 " .word 1b,(3b-1b)\n"
145 " .word 2b,(3b-2b)\n"
148 : "=r" (val), "=r" (ret)
149 : "0" (val), "r" (saddr), "r" (regs->isr)
152 DPRINTF("val = 0x" RFMT "\n", val);
155 regs->gr[toreg] = val;
160 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
162 unsigned long saddr = regs->ior;
163 unsigned long val = 0;
166 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
167 regs->isr, regs->ior, toreg);
169 __asm__ __volatile__ (
170 " zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */
172 " depw %%r0,31,2,%3\n"
173 "1: ldw 0(%%sr1,%3),%0\n"
174 "2: ldw 4(%%sr1,%3),%%r20\n"
175 " subi 32,%%r19,%%r19\n"
177 " vshd %0,%%r20,%0\n"
178 " cmpclr,= %%r0, %%r0, %1\n"
179 "3: ldo -2(%%r0), %1\n"
180 " .section __ex_table,\"a\"\n"
182 " .dword 1b,(3b-1b)\n"
183 " .dword 2b,(3b-2b)\n"
185 " .word 1b,(3b-1b)\n"
186 " .word 2b,(3b-2b)\n"
189 : "=r" (val), "=r" (ret)
190 : "0" (val), "r" (saddr), "r" (regs->isr)
193 DPRINTF("val = 0x" RFMT "\n", val);
196 ((__u32*)(regs->fr))[toreg] = val;
198 regs->gr[toreg] = val;
202 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
204 unsigned long saddr = regs->ior;
208 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
209 regs->isr, regs->ior, toreg);
216 __asm__ __volatile__ (
217 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
219 " depd %%r0,63,3,%3\n"
220 "1: ldd 0(%%sr1,%3),%0\n"
221 "2: ldd 8(%%sr1,%3),%%r20\n"
222 " subi 64,%%r19,%%r19\n"
224 " shrpd %0,%%r20,%%sar,%0\n"
225 " cmpclr,= %%r0, %%r0, %1\n"
226 "3: ldo -2(%%r0), %1\n"
227 " .section __ex_table,\"a\"\n"
229 " .dword 1b,(3b-1b)\n"
230 " .dword 2b,(3b-2b)\n"
232 " .word 1b,(3b-1b)\n"
233 " .word 2b,(3b-2b)\n"
236 : "=r" (val), "=r" (ret)
237 : "0" (val), "r" (saddr), "r" (regs->isr)
241 unsigned long valh=0,vall=0;
242 __asm__ __volatile__ (
243 " zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */
245 " dep %%r0,31,2,%5\n"
246 "1: ldw 0(%%sr1,%5),%0\n"
247 "2: ldw 4(%%sr1,%5),%1\n"
248 "3: ldw 8(%%sr1,%5),%%r20\n"
249 " subi 32,%%r19,%%r19\n"
252 " vshd %1,%%r20,%1\n"
253 " cmpclr,= %%r0, %%r0, %2\n"
254 "4: ldo -2(%%r0), %2\n"
255 " .section __ex_table,\"a\"\n"
257 " .dword 1b,(4b-1b)\n"
258 " .dword 2b,(4b-2b)\n"
259 " .dword 3b,(4b-3b)\n"
261 " .word 1b,(4b-1b)\n"
262 " .word 2b,(4b-2b)\n"
263 " .word 3b,(4b-3b)\n"
266 : "=r" (valh), "=r" (vall), "=r" (ret)
267 : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr)
269 val=((__u64)valh<<32)|(__u64)vall;
273 DPRINTF("val = 0x%llx\n", val);
276 regs->fr[toreg] = val;
278 regs->gr[toreg] = val;
283 static int emulate_sth(struct pt_regs *regs, int frreg)
285 unsigned long val = regs->gr[frreg];
291 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
292 val, regs->isr, regs->ior);
294 __asm__ __volatile__ (
296 " extrw,u %1, 23, 8, %%r19\n"
297 "1: stb %1, 1(%%sr1, %2)\n"
298 "2: stb %%r19, 0(%%sr1, %2)\n"
299 " cmpclr,= %%r0, %%r0, %0\n"
300 "3: ldo -2(%%r0), %0\n"
301 " .section __ex_table,\"a\"\n"
303 " .dword 1b,(3b-1b)\n"
304 " .dword 2b,(3b-2b)\n"
306 " .word 1b,(3b-1b)\n"
307 " .word 2b,(3b-2b)\n"
311 : "r" (val), "r" (regs->ior), "r" (regs->isr)
317 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
323 val = ((__u32*)(regs->fr))[frreg];
325 val = regs->gr[frreg];
329 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
330 val, regs->isr, regs->ior);
333 __asm__ __volatile__ (
335 " zdep %2, 28, 2, %%r19\n"
336 " dep %%r0, 31, 2, %2\n"
338 " depwi,z -2, %%sar, 32, %%r19\n"
339 "1: ldw 0(%%sr1,%2),%%r20\n"
340 "2: ldw 4(%%sr1,%2),%%r21\n"
341 " vshd %%r0, %1, %%r22\n"
342 " vshd %1, %%r0, %%r1\n"
343 " and %%r20, %%r19, %%r20\n"
344 " andcm %%r21, %%r19, %%r21\n"
345 " or %%r22, %%r20, %%r20\n"
346 " or %%r1, %%r21, %%r21\n"
347 " stw %%r20,0(%%sr1,%2)\n"
348 " stw %%r21,4(%%sr1,%2)\n"
349 " cmpclr,= %%r0, %%r0, %0\n"
350 "3: ldo -2(%%r0), %0\n"
351 " .section __ex_table,\"a\"\n"
353 " .dword 1b,(3b-1b)\n"
354 " .dword 2b,(3b-2b)\n"
356 " .word 1b,(3b-1b)\n"
357 " .word 2b,(3b-2b)\n"
361 : "r" (val), "r" (regs->ior), "r" (regs->isr)
362 : "r19", "r20", "r21", "r22", "r1" );
366 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
372 val = regs->fr[frreg];
374 val = regs->gr[frreg];
378 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
379 val, regs->isr, regs->ior);
386 __asm__ __volatile__ (
388 " depd,z %2, 60, 3, %%r19\n"
389 " depd %%r0, 63, 3, %2\n"
391 " depdi,z -2, %%sar, 64, %%r19\n"
392 "1: ldd 0(%%sr1,%2),%%r20\n"
393 "2: ldd 8(%%sr1,%2),%%r21\n"
394 " shrpd %%r0, %1, %%sar, %%r22\n"
395 " shrpd %1, %%r0, %%sar, %%r1\n"
396 " and %%r20, %%r19, %%r20\n"
397 " andcm %%r21, %%r19, %%r21\n"
398 " or %%r22, %%r20, %%r20\n"
399 " or %%r1, %%r21, %%r21\n"
400 "3: std %%r20,0(%%sr1,%2)\n"
401 "4: std %%r21,8(%%sr1,%2)\n"
402 " cmpclr,= %%r0, %%r0, %0\n"
403 "5: ldo -2(%%r0), %0\n"
404 " .section __ex_table,\"a\"\n"
406 " .dword 1b,(5b-1b)\n"
407 " .dword 2b,(5b-2b)\n"
408 " .dword 3b,(5b-3b)\n"
409 " .dword 4b,(5b-4b)\n"
411 " .word 1b,(5b-1b)\n"
412 " .word 2b,(5b-2b)\n"
413 " .word 3b,(5b-3b)\n"
414 " .word 4b,(5b-4b)\n"
418 : "r" (val), "r" (regs->ior), "r" (regs->isr)
419 : "r19", "r20", "r21", "r22", "r1" );
422 unsigned long valh=(val>>32),vall=(val&0xffffffffl);
423 __asm__ __volatile__ (
425 " zdep %2, 29, 2, %%r19\n"
426 " dep %%r0, 31, 2, %2\n"
428 " zvdepi -2, 32, %%r19\n"
429 "1: ldw 0(%%sr1,%3),%%r20\n"
430 "2: ldw 8(%%sr1,%3),%%r21\n"
431 " vshd %1, %2, %%r1\n"
432 " vshd %%r0, %1, %1\n"
433 " vshd %2, %%r0, %2\n"
434 " and %%r20, %%r19, %%r20\n"
435 " andcm %%r21, %%r19, %%r21\n"
436 " or %1, %%r20, %1\n"
437 " or %2, %%r21, %2\n"
438 "3: stw %1,0(%%sr1,%1)\n"
439 "4: stw %%r1,4(%%sr1,%3)\n"
440 "5: stw %2,8(%%sr1,%3)\n"
441 " cmpclr,= %%r0, %%r0, %0\n"
442 "6: ldo -2(%%r0), %0\n"
443 " .section __ex_table,\"a\"\n"
445 " .dword 1b,(6b-1b)\n"
446 " .dword 2b,(6b-2b)\n"
447 " .dword 3b,(6b-3b)\n"
448 " .dword 4b,(6b-4b)\n"
449 " .dword 5b,(6b-5b)\n"
451 " .word 1b,(6b-1b)\n"
452 " .word 2b,(6b-2b)\n"
453 " .word 3b,(6b-3b)\n"
454 " .word 4b,(6b-4b)\n"
455 " .word 5b,(6b-5b)\n"
459 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
460 : "r19", "r20", "r21", "r1" );
467 void handle_unaligned(struct pt_regs *regs)
469 static unsigned long unaligned_count = 0;
470 static unsigned long last_time = 0;
471 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
473 int ret = ERR_NOTHANDLED;
475 register int flop=0; /* true if this is a flop */
477 /* log a message with pacing */
480 if (unaligned_count > 5 && jiffies - last_time > 5*HZ)
485 if (++unaligned_count < 5)
488 sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n",
489 current->comm, current->pid, regs->ior, regs->iaoq[0]);
490 printk(KERN_WARNING "%s", buf);
491 #ifdef DEBUG_UNALIGNED
496 if (!unaligned_enabled)
500 /* handle modification - OK, it's ugly, see the instruction manual */
501 switch (MAJOR_OP(regs->iir))
509 if (regs->iir&0x1000) /* short loads */
511 newbase += IM5_3(regs->iir);
513 newbase += IM5_2(regs->iir);
514 else if (regs->iir&0x2000) /* scaled indexed */
517 switch (regs->iir & OPCODE1_MASK)
527 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
528 } else /* simple indexed */
529 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
535 newbase += IM14(regs->iir);
542 newbase += IM14(regs->iir&~0xe);
548 newbase += IM14(regs->iir&6);
555 newbase += IM14(regs->iir&~4);
560 if (regs->isr != regs->sr[7])
562 printk(KERN_CRIT "isr verification failed (isr: " RFMT ", sr7: " RFMT "\n",
563 regs->isr, regs->sr[7]);
565 /* don't kill him though, since he has appropriate access to the page, or we
566 * would never have gotten here.
570 /* TODO: make this cleaner... */
571 switch (regs->iir & OPCODE1_MASK)
575 ret = emulate_ldh(regs, R3(regs->iir));
582 ret = emulate_ldw(regs, R3(regs->iir),0);
586 ret = emulate_sth(regs, R2(regs->iir));
591 ret = emulate_stw(regs, R2(regs->iir),0);
599 ret = emulate_ldd(regs, R3(regs->iir),0);
604 ret = emulate_std(regs, R2(regs->iir),0);
613 ret = emulate_ldw(regs,FR3(regs->iir),1);
619 ret = emulate_ldd(regs,R3(regs->iir),1);
627 ret = emulate_stw(regs,FR3(regs->iir),1);
633 ret = emulate_std(regs,R3(regs->iir),1);
640 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
644 switch (regs->iir & OPCODE2_MASK)
648 ret = emulate_ldd(regs,R2(regs->iir),1);
652 ret = emulate_std(regs, R2(regs->iir),1);
657 ret = emulate_ldd(regs, R2(regs->iir),0);
660 ret = emulate_std(regs, R2(regs->iir),0);
665 switch (regs->iir & OPCODE3_MASK)
669 ret = emulate_ldw(regs, R2(regs->iir),0);
672 ret = emulate_ldw(regs, R2(regs->iir),1);
677 ret = emulate_stw(regs, R2(regs->iir),1);
680 ret = emulate_stw(regs, R2(regs->iir),0);
683 switch (regs->iir & OPCODE4_MASK)
686 ret = emulate_ldh(regs, R2(regs->iir));
690 ret = emulate_ldw(regs, R2(regs->iir),0);
693 ret = emulate_sth(regs, R2(regs->iir));
697 ret = emulate_stw(regs, R2(regs->iir),0);
701 if (modify && R1(regs->iir))
702 regs->gr[R1(regs->iir)] = newbase;
705 if (ret == ERR_NOTHANDLED)
706 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
708 DPRINTF("ret = %d\n", ret);
712 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
713 die_if_kernel("Unaligned data reference", regs, 28);
715 if (ret == ERR_PAGEFAULT)
717 si.si_signo = SIGSEGV;
719 si.si_code = SEGV_MAPERR;
720 si.si_addr = (void *)regs->ior;
721 force_sig_info(SIGSEGV, &si, current);
726 /* couldn't handle it ... */
727 si.si_signo = SIGBUS;
729 si.si_code = BUS_ADRALN;
730 si.si_addr = (void *)regs->ior;
731 force_sig_info(SIGBUS, &si, current);
737 /* else we handled it, let life go on. */
742 * NB: check_unaligned() is only used for PCXS processors right
743 * now, so we only check for PA1.1 encodings at this point.
747 check_unaligned(struct pt_regs *regs)
749 unsigned long align_mask;
751 /* Get alignment mask */
754 switch (regs->iir & OPCODE1_MASK) {
772 switch (regs->iir & OPCODE4_MASK) {
787 return (int)(regs->ior & align_mask);