2 * Fast Ethernet Controller (FCC) driver for Motorola MPC8260.
3 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
5 * This version of the driver is a combination of the 8xx fec and
6 * 8260 SCC Ethernet drivers. This version has some additional
7 * configuration options, which should probably be moved out of
8 * here. This driver currently works for the EST SBC8260,
9 * SBS Diablo/BCM, Embedded Planet RPX6, TQM8260, and others.
11 * Right now, I am very watseful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets. Since this is a cache coherent processor and CPM,
17 * I could also preallocate SKB's and use them directly on the interface.
21 #include <linux/config.h>
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/bitops.h>
39 #include <asm/immap_cpm2.h>
40 #include <asm/pgtable.h>
41 #include <asm/mpc8260.h>
43 #include <asm/uaccess.h>
46 /* The transmitter timeout
48 #define TX_TIMEOUT (2*HZ)
50 #ifdef CONFIG_USE_MDIO
51 /* Forward declarations of some structures to support different PHYs */
55 void (*funct)(uint mii_reg, struct net_device *dev);
62 const phy_cmd_t *config;
63 const phy_cmd_t *startup;
64 const phy_cmd_t *ack_int;
65 const phy_cmd_t *shutdown;
68 /* Register definitions for the PHY. */
70 #define MII_REG_CR 0 /* Control Register */
71 #define MII_REG_SR 1 /* Status Register */
72 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
73 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
74 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
75 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
76 #define MII_REG_ANER 6 /* A-N Expansion Register */
77 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
78 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
80 /* values for phy_status */
82 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
83 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
84 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
85 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
86 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
87 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
88 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
90 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
91 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
92 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
93 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
94 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
95 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
96 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
97 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
98 #endif /* CONFIG_USE_MDIO */
100 /* The number of Tx and Rx buffers. These are allocated from the page
101 * pool. The code may assume these are power of two, so it is best
102 * to keep them that size.
103 * We don't need to allocate pages for the transmitter. We just use
104 * the skbuffer directly.
106 #define FCC_ENET_RX_PAGES 16
107 #define FCC_ENET_RX_FRSIZE 2048
108 #define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE)
109 #define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES)
110 #define TX_RING_SIZE 16 /* Must be power of two */
111 #define TX_RING_MOD_MASK 15 /* for this to work */
113 /* The FCC stores dest/src/type, data, and checksum for receive packets.
115 #define PKT_MAXBUF_SIZE 1518
116 #define PKT_MINBUF_SIZE 64
118 /* Maximum input DMA size. Must be a should(?) be a multiple of 4.
120 #define PKT_MAXDMA_SIZE 1520
122 /* Maximum input buffer size. Must be a multiple of 32.
124 #define PKT_MAXBLR_SIZE 1536
126 static int fcc_enet_open(struct net_device *dev);
127 static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
128 static int fcc_enet_rx(struct net_device *dev);
129 static irqreturn_t fcc_enet_interrupt(int irq, void *dev_id, struct pt_regs *);
130 static int fcc_enet_close(struct net_device *dev);
131 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev);
132 static void set_multicast_list(struct net_device *dev);
133 static void fcc_restart(struct net_device *dev, int duplex);
134 static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
136 /* These will be configurable for the FCC choice.
137 * Multiple ports can be configured. There is little choice among the
138 * I/O pins to the PHY, except the clocks. We will need some board
139 * dependent clock selection.
140 * Why in the hell did I put these inside #ifdef's? I dunno, maybe to
141 * help show what pins are used for each device.
144 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
145 * but there is little variation among the choices.
147 #define PA1_COL ((uint)0x00000001)
148 #define PA1_CRS ((uint)0x00000002)
149 #define PA1_TXER ((uint)0x00000004)
150 #define PA1_TXEN ((uint)0x00000008)
151 #define PA1_RXDV ((uint)0x00000010)
152 #define PA1_RXER ((uint)0x00000020)
153 #define PA1_TXDAT ((uint)0x00003c00)
154 #define PA1_RXDAT ((uint)0x0003c000)
155 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
156 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
158 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
159 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
161 #ifdef CONFIG_SBC82xx
162 /* rx is clk9, tx is clk10 */
163 #define PC_F1RXCLK ((uint)0x00000100)
164 #define PC_F1TXCLK ((uint)0x00000200)
165 #define CMX1_CLK_ROUTE ((uint)0x25000000)
166 #define CMX1_CLK_MASK ((uint)0xff000000)
167 #elif defined(CONFIG_ADS8272)
168 #define PC_F1RXCLK ((uint)0x00000400)
169 #define PC_F1TXCLK ((uint)0x00000200)
170 #define CMX1_CLK_ROUTE ((uint)0x36000000)
171 #define CMX1_CLK_MASK ((uint)0xff000000)
172 #else /* other boards */
173 /* CLK12 is receive, CLK11 is transmit. These are board specific. */
174 #define PC_F1RXCLK ((uint)0x00000800)
175 #define PC_F1TXCLK ((uint)0x00000400)
176 #define CMX1_CLK_ROUTE ((uint)0x3e000000)
177 #define CMX1_CLK_MASK ((uint)0xff000000)
180 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
181 * but there is little variation among the choices.
183 #define PB2_TXER ((uint)0x00000001)
184 #define PB2_RXDV ((uint)0x00000002)
185 #define PB2_TXEN ((uint)0x00000004)
186 #define PB2_RXER ((uint)0x00000008)
187 #define PB2_COL ((uint)0x00000010)
188 #define PB2_CRS ((uint)0x00000020)
189 #define PB2_TXDAT ((uint)0x000003c0)
190 #define PB2_RXDAT ((uint)0x00003c00)
191 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
192 PB2_RXER | PB2_RXDV | PB2_TXER)
193 #define PB2_PSORB1 (PB2_TXEN)
194 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
195 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
197 /* CLK13 is receive, CLK14 is transmit. These are board dependent.
199 #ifdef CONFIG_ADS8272
200 #define PC_F2RXCLK ((uint)0x00004000)
201 #define PC_F2TXCLK ((uint)0x00008000)
202 #define CMX2_CLK_ROUTE ((uint)0x00370000)
203 #define CMX2_CLK_MASK ((uint)0x00ff0000)
205 #define PC_F2RXCLK ((uint)0x00001000)
206 #define PC_F2TXCLK ((uint)0x00002000)
207 #define CMX2_CLK_ROUTE ((uint)0x00250000)
208 #define CMX2_CLK_MASK ((uint)0x00ff0000)
211 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
212 * but there is little variation among the choices.
214 #define PB3_RXDV ((uint)0x00004000)
215 #define PB3_RXER ((uint)0x00008000)
216 #define PB3_TXER ((uint)0x00010000)
217 #define PB3_TXEN ((uint)0x00020000)
218 #define PB3_COL ((uint)0x00040000)
219 #define PB3_CRS ((uint)0x00080000)
220 #define PB3_TXDAT ((uint)0x0f000000)
221 #define PB3_RXDAT ((uint)0x00f00000)
222 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
223 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
224 #define PB3_PSORB1 (0)
225 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
226 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
228 /* CLK15 is receive, CLK16 is transmit. These are board dependent.
230 #define PC_F3RXCLK ((uint)0x00004000)
231 #define PC_F3TXCLK ((uint)0x00008000)
232 #define CMX3_CLK_ROUTE ((uint)0x00003700)
233 #define CMX3_CLK_MASK ((uint)0x0000ff00)
235 /* MII status/control serial interface.
237 #ifdef CONFIG_TQM8260
238 /* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
239 #define PC_MDIO ((uint)0x00000002)
240 #define PC_MDCK ((uint)0x00000001)
241 #elif defined(CONFIG_ADS8272)
242 #define PC_MDIO ((uint)0x00002000)
243 #define PC_MDCK ((uint)0x00001000)
245 #define PC_MDIO ((uint)0x00000004)
246 #define PC_MDCK ((uint)0x00000020)
249 /* A table of information for supporting FCCs. This does two things.
250 * First, we know how many FCCs we have and they are always externally
251 * numbered from zero. Second, it holds control register and I/O
252 * information that could be different among board designs.
254 typedef struct fcc_info {
267 static fcc_info_t fcc_ports[] = {
268 #ifdef CONFIG_FCC1_ENET
269 { 0, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
270 (PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
271 # if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
274 0x00000004, 0x00000100 },
277 #ifdef CONFIG_FCC2_ENET
278 { 1, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
279 (PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
280 # if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
282 # elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260)
283 0x00400000, 0x00200000 },
285 0x00000002, 0x00000080 },
288 #ifdef CONFIG_FCC3_ENET
289 { 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
290 (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
291 # if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
294 0x00000001, 0x00000040 },
299 /* The FCC buffer descriptors track the ring buffers. The rx_bd_base and
300 * tx_bd_base always point to the base of the buffer descriptors. The
301 * cur_rx and cur_tx point to the currently available buffer.
302 * The dirty_tx tracks the current buffer that is being sent by the
303 * controller. The cur_tx and dirty_tx are equal under both completely
304 * empty and completely full conditions. The empty/ready indicator in
305 * the buffer descriptor determines the actual condition.
307 struct fcc_enet_private {
308 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
309 struct sk_buff* tx_skbuff[TX_RING_SIZE];
313 atomic_t n_pkts; /* Number of packets in tx ring */
315 /* CPM dual port RAM relative addresses.
317 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
319 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
320 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
321 volatile fcc_t *fccp;
322 volatile fcc_enet_t *ep;
323 struct net_device_stats stats;
327 #ifdef CONFIG_USE_MDIO
332 struct tq_struct phy_task;
337 #endif /* CONFIG_USE_MDIO */
346 static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
347 volatile cpm2_map_t *immap);
348 static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
349 static void init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
350 volatile cpm2_map_t *immap);
351 static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
352 volatile cpm2_map_t *immap);
354 #ifdef CONFIG_USE_MDIO
355 static int mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *));
356 static uint mii_send_receive(fcc_info_t *fip, uint cmd);
358 static void fcc_stop(struct net_device *dev);
360 /* Make MII read/write commands for the FCC.
362 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
363 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
366 #endif /* CONFIG_USE_MDIO */
370 fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
372 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
377 /* Link is down or autonegotiation is in progress. */
381 /* Fill in a Tx ring entry */
384 #ifndef final_version
385 if (bdp->cbd_sc & BD_ENET_TX_READY) {
386 /* Ooops. All transmit buffers are full. Bail out.
387 * This should not happen, since cep->tx_full should be set.
389 printk("%s: tx queue full!.\n", dev->name);
394 /* Clear all of the status flags. */
395 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
397 /* If the frame is short, tell CPM to pad it. */
398 if (skb->len <= ETH_ZLEN)
399 bdp->cbd_sc |= BD_ENET_TX_PAD;
401 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
403 /* Set buffer length and buffer pointer. */
404 bdp->cbd_datlen = skb->len;
405 bdp->cbd_bufaddr = __pa(skb->data);
407 spin_lock_irq(&cep->lock);
409 /* Save skb pointer. */
410 idx = cep->skb_cur & TX_RING_MOD_MASK;
411 if (cep->tx_skbuff[idx]) {
412 /* This should never happen (any more).
413 Leave the sanity check in for now... */
414 printk(KERN_ERR "EEP. cep->tx_skbuff[%d] is %p not NULL in %s\n",
415 idx, cep->tx_skbuff[idx], __func__);
416 printk(KERN_ERR "Expect to lose %d bytes of sock space",
417 cep->tx_skbuff[idx]->truesize);
419 cep->tx_skbuff[idx] = skb;
421 cep->stats.tx_bytes += skb->len;
424 atomic_inc(&cep->n_pkts);
426 /* Send it on its way. Tell CPM its ready, interrupt when done,
427 * its the last BD of the frame, and to put the CRC on the end.
429 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
432 /* Errata says don't do this. */
433 cep->fccp->fcc_ftodr = 0x8000;
435 dev->trans_start = jiffies;
437 /* If this was the last BD in the ring, start at the beginning again. */
438 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
439 bdp = cep->tx_bd_base;
444 /* If the tx_ring is full, stop the queue */
445 if (atomic_read(&cep->n_pkts) >= (TX_RING_SIZE-1)) {
446 if (!netif_queue_stopped(dev)) {
447 netif_stop_queue(dev);
452 cep->cur_tx = (cbd_t *)bdp;
454 spin_unlock_irq(&cep->lock);
461 fcc_enet_timeout(struct net_device *dev)
463 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
465 printk("%s: transmit timed out.\n", dev->name);
466 cep->stats.tx_errors++;
467 #ifndef final_version
471 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
472 cep->cur_tx, cep->tx_full ? " (full)" : "",
474 bdp = cep->tx_bd_base;
475 printk(" Tx @base %p :\n", bdp);
476 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
477 printk("%04x %04x %08x\n",
481 bdp = cep->rx_bd_base;
482 printk(" Rx @base %p :\n", bdp);
483 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
484 printk("%04x %04x %08x\n",
491 netif_wake_queue(dev);
494 /* The interrupt handler. */
496 fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
498 struct net_device *dev = dev_id;
499 volatile struct fcc_enet_private *cep;
505 cep = (struct fcc_enet_private *)dev->priv;
507 /* Get the interrupt events that caused us to be here.
509 int_events = cep->fccp->fcc_fcce;
510 cep->fccp->fcc_fcce = int_events;
513 /* Handle receive event in its own function.
515 if (int_events & FCC_ENET_RXF)
518 /* Check for a transmit error. The manual is a little unclear
519 * about this, so the debug code until I get it figured out. It
520 * appears that if TXE is set, then TXB is not set. However,
521 * if carrier sense is lost during frame transmission, the TXE
522 * bit is set, "and continues the buffer transmission normally."
523 * I don't know if "normally" implies TXB is set when the buffer
524 * descriptor is closed.....trial and error :-).
527 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
529 if (int_events & (FCC_ENET_TXE | FCC_ENET_TXB)) {
530 spin_lock(&cep->lock);
532 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
533 if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
536 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
537 cep->stats.tx_heartbeat_errors++;
538 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
539 cep->stats.tx_window_errors++;
540 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
541 cep->stats.tx_aborted_errors++;
542 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
543 cep->stats.tx_fifo_errors++;
544 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
545 cep->stats.tx_carrier_errors++;
548 /* No heartbeat or Lost carrier are not really bad errors.
549 * The others require a restart transmit command.
552 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
554 cep->stats.tx_errors++;
557 cep->stats.tx_packets++;
559 /* Deferred means some collisions occurred during transmit,
560 * but we eventually sent the packet OK.
562 if (bdp->cbd_sc & BD_ENET_TX_DEF)
563 cep->stats.collisions++;
565 /* Free the sk buffer associated with this last transmit. */
566 idx = cep->skb_dirty & TX_RING_MOD_MASK;
567 dev_kfree_skb_irq(cep->tx_skbuff[idx]);
568 cep->tx_skbuff[idx] = NULL;
571 atomic_dec(&cep->n_pkts);
573 /* Update pointer to next buffer descriptor to be transmitted. */
574 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
575 bdp = cep->tx_bd_base;
579 /* I don't know if we can be held off from processing these
580 * interrupts for more than one frame time. I really hope
581 * not. In such a case, we would now want to check the
582 * currently available BD (cur_tx) and determine if any
583 * buffers between the dirty_tx and cur_tx have also been
584 * sent. We would want to process anything in between that
585 * does not have BD_ENET_TX_READY set.
588 /* Since we have freed up a buffer, the ring is no longer
593 if (netif_queue_stopped(dev)) {
594 netif_wake_queue(dev);
598 cep->dirty_tx = (cbd_t *)bdp;
602 volatile cpm_cpm2_t *cp;
604 /* Some transmit errors cause the transmitter to shut
605 * down. We now issue a restart transmit. Since the
606 * errors close the BD and update the pointers, the restart
607 * _should_ pick up without having to reset any of our
608 * pointers either. Also, To workaround 8260 device erratum
609 * CPM37, we must disable and then re-enable the transmitter
610 * following a Late Collision, Underrun, or Retry Limit error.
612 cep->fccp->fcc_gfmr &= ~FCC_GFMR_ENT;
613 udelay(10); /* wait a few microseconds just on principle */
614 cep->fccp->fcc_gfmr |= FCC_GFMR_ENT;
618 mk_cr_cmd(cep->fip->fc_cpmpage, cep->fip->fc_cpmblock,
619 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG;
620 while (cp->cp_cpcr & CPM_CR_FLG);
622 spin_unlock(&cep->lock);
625 /* Check for receive busy, i.e. packets coming but no place to
628 if (int_events & FCC_ENET_BSY) {
629 cep->stats.rx_dropped++;
634 /* During a receive, the cur_rx points to the current incoming buffer.
635 * When we update through the ring, if the next incoming buffer has
636 * not been given to the system, we just set the empty indicator,
637 * effectively tossing the packet.
640 fcc_enet_rx(struct net_device *dev)
642 struct fcc_enet_private *cep;
647 cep = (struct fcc_enet_private *)dev->priv;
649 /* First, grab all of the stats for the incoming packet.
650 * These get messed up if we get called due to a busy condition.
655 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
658 #ifndef final_version
659 /* Since we have allocated space to hold a complete frame, both
660 * the first and last indicators should be set.
662 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
663 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
664 printk("CPM ENET: rcv is not first+last\n");
667 /* Frame too long or too short. */
668 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
669 cep->stats.rx_length_errors++;
670 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
671 cep->stats.rx_frame_errors++;
672 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
673 cep->stats.rx_crc_errors++;
674 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
675 cep->stats.rx_crc_errors++;
676 if (bdp->cbd_sc & BD_ENET_RX_CL) /* Late Collision */
677 cep->stats.rx_frame_errors++;
680 (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | BD_ENET_RX_CR
681 | BD_ENET_RX_OV | BD_ENET_RX_CL)))
683 /* Process the incoming frame. */
684 cep->stats.rx_packets++;
686 /* Remove the FCS from the packet length. */
687 pkt_len = bdp->cbd_datlen - 4;
688 cep->stats.rx_bytes += pkt_len;
690 /* This does 16 byte alignment, much more than we need. */
691 skb = dev_alloc_skb(pkt_len);
694 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
695 cep->stats.rx_dropped++;
699 skb_put(skb,pkt_len); /* Make room */
700 eth_copy_and_sum(skb,
701 (unsigned char *)__va(bdp->cbd_bufaddr),
703 skb->protocol=eth_type_trans(skb,dev);
708 /* Clear the status flags for this buffer. */
709 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
711 /* Mark the buffer empty. */
712 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
714 /* Update BD pointer to next entry. */
715 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
716 bdp = cep->rx_bd_base;
721 cep->cur_rx = (cbd_t *)bdp;
727 fcc_enet_close(struct net_device *dev)
729 /* Don't know what to do yet. */
730 netif_stop_queue(dev);
735 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev)
737 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
742 #ifdef CONFIG_USE_MDIO
744 /* NOTE: Most of the following comes from the FEC driver for 860. The
745 * overall structure of MII code has been retained (as it's proved stable
746 * and well-tested), but actual transfer requests are processed "at once"
747 * instead of being queued (there's no interrupt-driven MII transfer
748 * mechanism, one has to toggle the data/clock bits manually).
751 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
753 struct fcc_enet_private *fep;
756 /* Add PHY address to register command. */
758 regval |= fep->phy_addr << 23;
762 tmp = mii_send_receive(fep->fip, regval);
769 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
776 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
777 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
780 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
782 volatile struct fcc_enet_private *fep = dev->priv;
783 uint s = fep->phy_status;
785 s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
787 if (mii_reg & 0x0004)
789 if (mii_reg & 0x0010)
791 if (mii_reg & 0x0020)
795 fep->link = (s & PHY_STAT_LINK) ? 1 : 0;
798 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
800 volatile struct fcc_enet_private *fep = dev->priv;
801 uint s = fep->phy_status;
803 s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
805 if (mii_reg & 0x1000)
807 if (mii_reg & 0x4000)
813 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
815 volatile struct fcc_enet_private *fep = dev->priv;
816 uint s = fep->phy_status;
818 s &= ~(PHY_CONF_SPMASK);
820 if (mii_reg & 0x0020)
822 if (mii_reg & 0x0040)
824 if (mii_reg & 0x0080)
825 s |= PHY_CONF_100HDX;
826 if (mii_reg & 0x00100)
827 s |= PHY_CONF_100FDX;
831 /* ------------------------------------------------------------------------- */
832 /* The Level one LXT970 is used by many boards */
834 #ifdef CONFIG_FCC_LXT970
836 #define MII_LXT970_MIRROR 16 /* Mirror register */
837 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
838 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
839 #define MII_LXT970_CONFIG 19 /* Configuration Register */
840 #define MII_LXT970_CSR 20 /* Chip Status Register */
842 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
844 volatile struct fcc_enet_private *fep = dev->priv;
845 uint s = fep->phy_status;
847 s &= ~(PHY_STAT_SPMASK);
849 if (mii_reg & 0x0800) {
850 if (mii_reg & 0x1000)
851 s |= PHY_STAT_100FDX;
853 s |= PHY_STAT_100HDX;
855 if (mii_reg & 0x1000)
864 static phy_info_t phy_info_lxt970 = {
868 (const phy_cmd_t []) { /* config */
870 // { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
872 /* Set default operation of 100-TX....for some reason
873 * some of these bits are set on power up, which is wrong.
875 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
877 { mk_mii_read(MII_REG_CR), mii_parse_cr },
878 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
881 (const phy_cmd_t []) { /* startup - enable interrupts */
882 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
883 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
886 (const phy_cmd_t []) { /* ack_int */
887 /* read SR and ISR to acknowledge */
889 { mk_mii_read(MII_REG_SR), mii_parse_sr },
890 { mk_mii_read(MII_LXT970_ISR), NULL },
892 /* find out the current status */
894 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
897 (const phy_cmd_t []) { /* shutdown - disable interrupts */
898 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
903 #endif /* CONFIG_FEC_LXT970 */
905 /* ------------------------------------------------------------------------- */
906 /* The Level one LXT971 is used on some of my custom boards */
908 #ifdef CONFIG_FCC_LXT971
910 /* register definitions for the 971 */
912 #define MII_LXT971_PCR 16 /* Port Control Register */
913 #define MII_LXT971_SR2 17 /* Status Register 2 */
914 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
915 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
916 #define MII_LXT971_LCR 20 /* LED Control Register */
917 #define MII_LXT971_TCR 30 /* Transmit Control Register */
920 * I had some nice ideas of running the MDIO faster...
921 * The 971 should support 8MHz and I tried it, but things acted really
922 * weird, so 2.5 MHz ought to be enough for anyone...
925 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
927 volatile struct fcc_enet_private *fep = dev->priv;
928 uint s = fep->phy_status;
930 s &= ~(PHY_STAT_SPMASK);
932 if (mii_reg & 0x4000) {
933 if (mii_reg & 0x0200)
934 s |= PHY_STAT_100FDX;
936 s |= PHY_STAT_100HDX;
938 if (mii_reg & 0x0200)
943 if (mii_reg & 0x0008)
949 static phy_info_t phy_info_lxt971 = {
953 (const phy_cmd_t []) { /* config */
954 // { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
955 { mk_mii_read(MII_REG_CR), mii_parse_cr },
956 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
959 (const phy_cmd_t []) { /* startup - enable interrupts */
960 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
961 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
963 /* Somehow does the 971 tell me that the link is down
964 * the first read after power-up.
965 * read here to get a valid value in ack_int */
967 { mk_mii_read(MII_REG_SR), mii_parse_sr },
970 (const phy_cmd_t []) { /* ack_int */
971 /* find out the current status */
973 { mk_mii_read(MII_REG_SR), mii_parse_sr },
974 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
976 /* we only need to read ISR to acknowledge */
978 { mk_mii_read(MII_LXT971_ISR), NULL },
981 (const phy_cmd_t []) { /* shutdown - disable interrupts */
982 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
987 #endif /* CONFIG_FEC_LXT970 */
990 /* ------------------------------------------------------------------------- */
991 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
993 #ifdef CONFIG_FCC_QS6612
995 /* register definitions */
997 #define MII_QS6612_MCR 17 /* Mode Control Register */
998 #define MII_QS6612_FTR 27 /* Factory Test Register */
999 #define MII_QS6612_MCO 28 /* Misc. Control Register */
1000 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
1001 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
1002 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
1004 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1006 volatile struct fcc_enet_private *fep = dev->priv;
1007 uint s = fep->phy_status;
1009 s &= ~(PHY_STAT_SPMASK);
1011 switch((mii_reg >> 2) & 7) {
1012 case 1: s |= PHY_STAT_10HDX; break;
1013 case 2: s |= PHY_STAT_100HDX; break;
1014 case 5: s |= PHY_STAT_10FDX; break;
1015 case 6: s |= PHY_STAT_100FDX; break;
1018 fep->phy_status = s;
1021 static phy_info_t phy_info_qs6612 = {
1025 (const phy_cmd_t []) { /* config */
1026 // { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
1028 /* The PHY powers up isolated on the RPX,
1029 * so send a command to allow operation.
1032 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1034 /* parse cr and anar to get some info */
1036 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1037 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1040 (const phy_cmd_t []) { /* startup - enable interrupts */
1041 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1042 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1045 (const phy_cmd_t []) { /* ack_int */
1047 /* we need to read ISR, SR and ANER to acknowledge */
1049 { mk_mii_read(MII_QS6612_ISR), NULL },
1050 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1051 { mk_mii_read(MII_REG_ANER), NULL },
1053 /* read pcr to get info */
1055 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1058 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1059 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1065 #endif /* CONFIG_FEC_QS6612 */
1068 /* ------------------------------------------------------------------------- */
1069 /* The Davicom DM9131 is used on the HYMOD board */
1071 #ifdef CONFIG_FCC_DM9131
1073 /* register definitions */
1075 #define MII_DM9131_ACR 16 /* Aux. Config Register */
1076 #define MII_DM9131_ACSR 17 /* Aux. Config/Status Register */
1077 #define MII_DM9131_10TCSR 18 /* 10BaseT Config/Status Reg. */
1078 #define MII_DM9131_INTR 21 /* Interrupt Register */
1079 #define MII_DM9131_RECR 22 /* Receive Error Counter Reg. */
1080 #define MII_DM9131_DISCR 23 /* Disconnect Counter Register */
1082 static void mii_parse_dm9131_acsr(uint mii_reg, struct net_device *dev)
1084 volatile struct fcc_enet_private *fep = dev->priv;
1085 uint s = fep->phy_status;
1087 s &= ~(PHY_STAT_SPMASK);
1089 switch ((mii_reg >> 12) & 0xf) {
1090 case 1: s |= PHY_STAT_10HDX; break;
1091 case 2: s |= PHY_STAT_10FDX; break;
1092 case 4: s |= PHY_STAT_100HDX; break;
1093 case 8: s |= PHY_STAT_100FDX; break;
1096 fep->phy_status = s;
1099 static phy_info_t phy_info_dm9131 = {
1103 (const phy_cmd_t []) { /* config */
1104 /* parse cr and anar to get some info */
1105 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1106 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1109 (const phy_cmd_t []) { /* startup - enable interrupts */
1110 { mk_mii_write(MII_DM9131_INTR, 0x0002), NULL },
1111 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1114 (const phy_cmd_t []) { /* ack_int */
1116 /* we need to read INTR, SR and ANER to acknowledge */
1118 { mk_mii_read(MII_DM9131_INTR), NULL },
1119 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1120 { mk_mii_read(MII_REG_ANER), NULL },
1122 /* read acsr to get info */
1124 { mk_mii_read(MII_DM9131_ACSR), mii_parse_dm9131_acsr },
1127 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1128 { mk_mii_write(MII_DM9131_INTR, 0x0f00), NULL },
1134 #endif /* CONFIG_FEC_DM9131 */
1137 static phy_info_t *phy_info[] = {
1139 #ifdef CONFIG_FCC_LXT970
1141 #endif /* CONFIG_FEC_LXT970 */
1143 #ifdef CONFIG_FCC_LXT971
1145 #endif /* CONFIG_FEC_LXT971 */
1147 #ifdef CONFIG_FCC_QS6612
1149 #endif /* CONFIG_FEC_QS6612 */
1151 #ifdef CONFIG_FCC_DM9131
1153 #endif /* CONFIG_FEC_DM9131 */
1158 static void mii_display_status(struct net_device *dev)
1160 volatile struct fcc_enet_private *fep = dev->priv;
1161 uint s = fep->phy_status;
1163 if (!fep->link && !fep->old_link) {
1164 /* Link is still down - don't print anything */
1168 printk("%s: status: ", dev->name);
1171 printk("link down");
1175 switch(s & PHY_STAT_SPMASK) {
1176 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1177 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1178 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1179 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1181 printk(", Unknown speed/duplex");
1184 if (s & PHY_STAT_ANC)
1185 printk(", auto-negotiation complete");
1188 if (s & PHY_STAT_FAULT)
1189 printk(", remote fault");
1194 static void mii_display_config(struct net_device *dev)
1196 volatile struct fcc_enet_private *fep = dev->priv;
1197 uint s = fep->phy_status;
1199 printk("%s: config: auto-negotiation ", dev->name);
1201 if (s & PHY_CONF_ANE)
1206 if (s & PHY_CONF_100FDX)
1208 if (s & PHY_CONF_100HDX)
1210 if (s & PHY_CONF_10FDX)
1212 if (s & PHY_CONF_10HDX)
1214 if (!(s & PHY_CONF_SPMASK))
1215 printk(", No speed/duplex selected?");
1217 if (s & PHY_CONF_LOOP)
1218 printk(", loopback enabled");
1222 fep->sequence_done = 1;
1225 static void mii_relink(struct net_device *dev)
1227 struct fcc_enet_private *fep = dev->priv;
1230 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1231 mii_display_status(dev);
1232 fep->old_link = fep->link;
1237 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1239 fcc_restart(dev, duplex);
1245 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1247 struct fcc_enet_private *fep = dev->priv;
1249 fep->phy_task.routine = (void *)mii_relink;
1250 fep->phy_task.data = dev;
1251 schedule_task(&fep->phy_task);
1254 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1256 struct fcc_enet_private *fep = dev->priv;
1258 fep->phy_task.routine = (void *)mii_display_config;
1259 fep->phy_task.data = dev;
1260 schedule_task(&fep->phy_task);
1265 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1267 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1271 /* Read remainder of PHY ID.
1274 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1276 struct fcc_enet_private *fep;
1280 fep->phy_id |= (mii_reg & 0xffff);
1282 for(i = 0; phy_info[i]; i++)
1283 if(phy_info[i]->id == (fep->phy_id >> 4))
1287 panic("%s: PHY id 0x%08x is not supported!\n",
1288 dev->name, fep->phy_id);
1290 fep->phy = phy_info[i];
1292 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1293 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1296 /* Scan all of the MII PHY addresses looking for someone to respond
1297 * with a valid ID. This usually happens quickly.
1300 mii_discover_phy(uint mii_reg, struct net_device *dev)
1302 struct fcc_enet_private *fep;
1307 if ((phytype = (mii_reg & 0xfff)) != 0xfff) {
1309 /* Got first part of ID, now get remainder. */
1310 fep->phy_id = phytype << 16;
1311 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1314 if (fep->phy_addr < 32) {
1315 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1318 printk("fec: No PHY device found.\n");
1323 /* This interrupt occurs when the PHY detects a link change. */
1325 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1327 struct net_device *dev = dev_id;
1328 struct fcc_enet_private *fep = dev->priv;
1330 mii_do_cmd(dev, fep->phy->ack_int);
1331 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1335 #endif /* CONFIG_USE_MDIO */
1337 /* Set or clear the multicast filter for this adaptor.
1338 * Skeleton taken from sunlance driver.
1339 * The CPM Ethernet implementation allows Multicast as well as individual
1340 * MAC address filtering. Some of the drivers check to make sure it is
1341 * a group multicast address, and discard those that are not. I guess I
1342 * will do the same for now, but just remove the test if you want
1343 * individual filtering as well (do the upper net layers want or support
1344 * this kind of feature?).
1347 set_multicast_list(struct net_device *dev)
1349 struct fcc_enet_private *cep;
1350 struct dev_mc_list *dmi;
1351 u_char *mcptr, *tdptr;
1352 volatile fcc_enet_t *ep;
1355 cep = (struct fcc_enet_private *)dev->priv;
1358 /* Get pointer to FCC area in parameter RAM.
1360 ep = (fcc_enet_t *)dev->base_addr;
1362 if (dev->flags&IFF_PROMISC) {
1364 /* Log any net taps. */
1365 printk("%s: Promiscuous mode enabled.\n", dev->name);
1366 cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
1369 cep->fccp->fcc_fpsmr &= ~FCC_PSMR_PRO;
1371 if (dev->flags & IFF_ALLMULTI) {
1372 /* Catch all multicast addresses, so set the
1373 * filter to all 1's.
1375 ep->fen_gaddrh = 0xffffffff;
1376 ep->fen_gaddrl = 0xffffffff;
1379 /* Clear filter and add the addresses in the list.
1386 for (i=0; i<dev->mc_count; i++) {
1388 /* Only support group multicast for now.
1390 if (!(dmi->dmi_addr[0] & 1))
1393 /* The address in dmi_addr is LSB first,
1394 * and taddr is MSB first. We have to
1395 * copy bytes MSB first from dmi_addr.
1397 mcptr = (u_char *)dmi->dmi_addr + 5;
1398 tdptr = (u_char *)&ep->fen_taddrh;
1400 *tdptr++ = *mcptr--;
1402 /* Ask CPM to run CRC and set bit in
1405 cpmp->cp_cpcr = mk_cr_cmd(cep->fip->fc_cpmpage,
1406 cep->fip->fc_cpmblock, 0x0c,
1407 CPM_CR_SET_GADDR) | CPM_CR_FLG;
1409 while (cpmp->cp_cpcr & CPM_CR_FLG);
1416 /* Set the individual MAC address.
1418 int fcc_enet_set_mac_address(struct net_device *dev, void *p)
1420 struct sockaddr *addr= (struct sockaddr *) p;
1421 struct fcc_enet_private *cep;
1422 volatile fcc_enet_t *ep;
1426 cep = (struct fcc_enet_private *)(dev->priv);
1429 if (netif_running(dev))
1432 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1434 eap = (unsigned char *) &(ep->fen_paddrh);
1435 for (i=5; i>=0; i--)
1436 *eap++ = addr->sa_data[i];
1442 /* Initialize the CPM Ethernet on FCC.
1444 static int __init fec_enet_init(void)
1446 struct net_device *dev;
1447 struct fcc_enet_private *cep;
1450 volatile cpm2_map_t *immap;
1451 volatile iop_cpm2_t *io;
1453 immap = (cpm2_map_t *)CPM_MAP_ADDR; /* and to internal registers */
1454 io = &immap->im_ioport;
1456 np = sizeof(fcc_ports) / sizeof(fcc_info_t);
1460 /* Create an Ethernet device instance.
1462 dev = alloc_etherdev(sizeof(*cep));
1467 spin_lock_init(&cep->lock);
1470 init_fcc_shutdown(fip, cep, immap);
1471 init_fcc_ioports(fip, io, immap);
1472 init_fcc_param(fip, dev, immap);
1474 dev->base_addr = (unsigned long)(cep->ep);
1476 /* The CPM Ethernet specific entries in the device
1479 dev->open = fcc_enet_open;
1480 dev->hard_start_xmit = fcc_enet_start_xmit;
1481 dev->tx_timeout = fcc_enet_timeout;
1482 dev->watchdog_timeo = TX_TIMEOUT;
1483 dev->stop = fcc_enet_close;
1484 dev->get_stats = fcc_enet_get_stats;
1485 dev->set_multicast_list = set_multicast_list;
1486 dev->set_mac_address = fcc_enet_set_mac_address;
1488 init_fcc_startup(fip, dev);
1490 err = register_netdev(dev);
1496 printk("%s: FCC ENET Version 0.3, ", dev->name);
1498 printk("%02x:", dev->dev_addr[i]);
1499 printk("%02x\n", dev->dev_addr[5]);
1501 #ifdef CONFIG_USE_MDIO
1502 /* Queue up command to detect the PHY and initialize the
1503 * remainder of the interface.
1506 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1507 #endif /* CONFIG_USE_MDIO */
1514 module_init(fec_enet_init);
1516 /* Make sure the device is shut down during initialization.
1519 init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
1520 volatile cpm2_map_t *immap)
1522 volatile fcc_enet_t *ep;
1523 volatile fcc_t *fccp;
1525 /* Get pointer to FCC area in parameter RAM.
1527 ep = (fcc_enet_t *)(&immap->im_dprambase[fip->fc_proff]);
1529 /* And another to the FCC register area.
1531 fccp = (volatile fcc_t *)(&immap->im_fcc[fip->fc_fccnum]);
1532 cep->fccp = fccp; /* Keep the pointers handy */
1535 /* Disable receive and transmit in case someone left it running.
1537 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1540 /* Initialize the I/O pins for the FCC Ethernet.
1543 init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
1544 volatile cpm2_map_t *immap)
1547 /* FCC1 pins are on port A/C. FCC2/3 are port B/C.
1549 if (fip->fc_proff == PROFF_FCC1) {
1550 /* Configure port A and C pins for FCC1 Ethernet.
1552 io->iop_pdira &= ~PA1_DIRA0;
1553 io->iop_pdira |= PA1_DIRA1;
1554 io->iop_psora &= ~PA1_PSORA0;
1555 io->iop_psora |= PA1_PSORA1;
1556 io->iop_ppara |= (PA1_DIRA0 | PA1_DIRA1);
1558 if (fip->fc_proff == PROFF_FCC2) {
1559 /* Configure port B and C pins for FCC Ethernet.
1561 io->iop_pdirb &= ~PB2_DIRB0;
1562 io->iop_pdirb |= PB2_DIRB1;
1563 io->iop_psorb &= ~PB2_PSORB0;
1564 io->iop_psorb |= PB2_PSORB1;
1565 io->iop_pparb |= (PB2_DIRB0 | PB2_DIRB1);
1567 if (fip->fc_proff == PROFF_FCC3) {
1568 /* Configure port B and C pins for FCC Ethernet.
1570 io->iop_pdirb &= ~PB3_DIRB0;
1571 io->iop_pdirb |= PB3_DIRB1;
1572 io->iop_psorb &= ~PB3_PSORB0;
1573 io->iop_psorb |= PB3_PSORB1;
1574 io->iop_pparb |= (PB3_DIRB0 | PB3_DIRB1);
1577 /* Port C has clocks......
1579 io->iop_psorc &= ~(fip->fc_trxclocks);
1580 io->iop_pdirc &= ~(fip->fc_trxclocks);
1581 io->iop_pparc |= fip->fc_trxclocks;
1583 #ifdef CONFIG_USE_MDIO
1584 /* ....and the MII serial clock/data.
1586 io->iop_pdatc |= (fip->fc_mdio | fip->fc_mdck);
1587 io->iop_podrc &= ~(fip->fc_mdio | fip->fc_mdck);
1588 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1589 io->iop_pparc &= ~(fip->fc_mdio | fip->fc_mdck);
1590 #endif /* CONFIG_USE_MDIO */
1592 /* Configure Serial Interface clock routing.
1593 * First, clear all FCC bits to zero,
1594 * then set the ones we want.
1596 immap->im_cpmux.cmx_fcr &= ~(fip->fc_clockmask);
1597 immap->im_cpmux.cmx_fcr |= fip->fc_clockroute;
1601 init_fcc_param(fcc_info_t *fip, struct net_device *dev,
1602 volatile cpm2_map_t *immap)
1605 unsigned long mem_addr;
1608 struct fcc_enet_private *cep;
1609 volatile fcc_enet_t *ep;
1610 volatile cbd_t *bdp;
1611 volatile cpm_cpm2_t *cp;
1613 cep = (struct fcc_enet_private *)(dev->priv);
1619 /* Zero the whole thing.....I must have missed some individually.
1620 * It works when I do this.
1622 memset((char *)ep, 0, sizeof(fcc_enet_t));
1624 /* Allocate space for the buffer descriptors from regular memory.
1625 * Initialize base addresses for the buffer descriptors.
1627 cep->rx_bd_base = (cbd_t *)kmalloc(sizeof(cbd_t) * RX_RING_SIZE,
1628 GFP_KERNEL | GFP_DMA);
1629 ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
1630 cep->tx_bd_base = (cbd_t *)kmalloc(sizeof(cbd_t) * TX_RING_SIZE,
1631 GFP_KERNEL | GFP_DMA);
1632 ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
1634 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
1635 cep->cur_rx = cep->rx_bd_base;
1637 ep->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1638 ep->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1640 /* Set maximum bytes per receive buffer.
1641 * It must be a multiple of 32.
1643 ep->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
1645 /* Allocate space in the reserved FCC area of DPRAM for the
1646 * internal buffers. No one uses this space (yet), so we
1647 * can do this. Later, we will add resource management for
1650 mem_addr = CPM_FCC_SPECIAL_BASE + (fip->fc_fccnum * 128);
1651 ep->fen_genfcc.fcc_riptr = mem_addr;
1652 ep->fen_genfcc.fcc_tiptr = mem_addr+32;
1653 ep->fen_padptr = mem_addr+64;
1654 memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32);
1656 ep->fen_genfcc.fcc_rbptr = 0;
1657 ep->fen_genfcc.fcc_tbptr = 0;
1658 ep->fen_genfcc.fcc_rcrc = 0;
1659 ep->fen_genfcc.fcc_tcrc = 0;
1660 ep->fen_genfcc.fcc_res1 = 0;
1661 ep->fen_genfcc.fcc_res2 = 0;
1663 ep->fen_camptr = 0; /* CAM isn't used in this driver */
1665 /* Set CRC preset and mask.
1667 ep->fen_cmask = 0xdebb20e3;
1668 ep->fen_cpres = 0xffffffff;
1670 ep->fen_crcec = 0; /* CRC Error counter */
1671 ep->fen_alec = 0; /* alignment error counter */
1672 ep->fen_disfc = 0; /* discard frame counter */
1673 ep->fen_retlim = 15; /* Retry limit threshold */
1674 ep->fen_pper = 0; /* Normal persistence */
1676 /* Clear hash filter tables.
1683 /* Clear the Out-of-sequence TxBD.
1685 ep->fen_tfcstat = 0;
1689 ep->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
1690 ep->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
1692 /* Set Ethernet station address.
1694 * This is supplied in the board information structure, so we
1695 * copy that into the controller.
1696 * So, far we have only been given one Ethernet address. We make
1697 * it unique by setting a few bits in the upper byte of the
1698 * non-static part of the address.
1700 eap = (unsigned char *)&(ep->fen_paddrh);
1701 for (i=5; i>=0; i--) {
1702 #ifdef CONFIG_SBC82xx
1704 /* bd->bi_enetaddr holds the SCC0 address; the FCC
1705 devices count up from there */
1706 dev->dev_addr[i] = bd->bi_enetaddr[i] & ~3;
1707 dev->dev_addr[i] += 1 + fip->fc_fccnum;
1708 *eap++ = dev->dev_addr[i];
1712 dev->dev_addr[i] = bd->bi_enetaddr[i];
1713 dev->dev_addr[i] |= (1 << (7 - fip->fc_fccnum));
1714 *eap++ = dev->dev_addr[i];
1718 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
1726 ep->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
1727 ep->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
1729 /* Clear stat counters, in case we ever enable RMON.
1746 ep->fen_rfthr = 0; /* Suggested by manual */
1750 /* Now allocate the host memory pages and initialize the
1751 * buffer descriptors.
1753 bdp = cep->tx_bd_base;
1754 for (i=0; i<TX_RING_SIZE; i++) {
1756 /* Initialize the BD for every fragment in the page.
1759 bdp->cbd_datlen = 0;
1760 bdp->cbd_bufaddr = 0;
1764 /* Set the last buffer to wrap.
1767 bdp->cbd_sc |= BD_SC_WRAP;
1769 bdp = cep->rx_bd_base;
1770 for (i=0; i<FCC_ENET_RX_PAGES; i++) {
1774 mem_addr = __get_free_page(GFP_KERNEL);
1776 /* Initialize the BD for every fragment in the page.
1778 for (j=0; j<FCC_ENET_RX_FRPPG; j++) {
1779 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
1780 bdp->cbd_datlen = 0;
1781 bdp->cbd_bufaddr = __pa(mem_addr);
1782 mem_addr += FCC_ENET_RX_FRSIZE;
1787 /* Set the last buffer to wrap.
1790 bdp->cbd_sc |= BD_SC_WRAP;
1792 /* Let's re-initialize the channel now. We have to do it later
1793 * than the manual describes because we have just now finished
1794 * the BD initialization.
1796 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, 0x0c,
1797 CPM_CR_INIT_TRX) | CPM_CR_FLG;
1798 while (cp->cp_cpcr & CPM_CR_FLG);
1800 cep->skb_cur = cep->skb_dirty = 0;
1801 atomic_set(&cep->n_pkts, 0);
1807 init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
1809 volatile fcc_t *fccp;
1810 struct fcc_enet_private *cep;
1812 cep = (struct fcc_enet_private *)(dev->priv);
1815 fccp->fcc_fcce = 0xffff; /* Clear any pending events */
1817 /* Enable interrupts for transmit error, complete frame
1818 * received, and any transmit buffer we have also set the
1821 fccp->fcc_fccm = (FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
1823 /* Install our interrupt handler.
1825 if (request_irq(fip->fc_interrupt, fcc_enet_interrupt, 0,
1827 printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);
1829 #ifdef CONFIG_USE_MDIO
1830 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0,
1832 printk("Can't get MII IRQ %d\n", fip->fc_interrupt);
1833 #endif /* CONFIG_USE_MDIO */
1835 /* Set GFMR to enable Ethernet operating mode.
1837 fccp->fcc_gfmr = (FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
1839 /* Set sync/delimiters.
1841 fccp->fcc_fdsr = 0xd555;
1843 /* Set protocol specific processing mode for Ethernet.
1844 * This has to be adjusted for Full Duplex operation after we can
1845 * determine how to detect that.
1847 fccp->fcc_fpsmr = FCC_PSMR_ENCRC;
1849 #ifdef CONFIG_PQ2ADS
1852 *(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_FETHIEN;
1853 *(volatile uint *)(BCSR_ADDR + 4) |= BCSR1_FETH_RST;
1856 #if defined(CONFIG_USE_MDIO) || defined(CONFIG_TQM8260)
1857 /* start in full duplex mode, and negotiate speed
1859 fcc_restart (dev, 1);
1861 /* start in half duplex mode
1863 fcc_restart (dev, 0);
1867 #ifdef CONFIG_USE_MDIO
1868 /* MII command/status interface.
1869 * I'm not going to describe all of the details. You can find the
1870 * protocol definition in many other places, including the data sheet
1871 * of most PHY parts.
1872 * I wonder what "they" were thinking (maybe weren't) when they leave
1873 * the I2C in the CPM but I have to toggle these bits......
1876 #define FCC_PDATC_MDIO(bit) \
1878 io->iop_pdatc |= fip->fc_mdio; \
1880 io->iop_pdatc &= ~fip->fc_mdio;
1882 #define FCC_PDATC_MDC(bit) \
1884 io->iop_pdatc |= fip->fc_mdck; \
1886 io->iop_pdatc &= ~fip->fc_mdck;
1889 mii_send_receive(fcc_info_t *fip, uint cmd)
1892 int read_op, i, off;
1893 volatile cpm2_map_t *immap;
1894 volatile iop_cpm2_t *io;
1896 immap = (cpm2_map_t *)CPM_MAP_ADDR;
1897 io = &immap->im_ioport;
1899 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1901 read_op = ((cmd & 0xf0000000) == 0x60000000);
1905 for (i = 0; i < 32; i++)
1916 for (i = 0, off = 31; i < (read_op ? 14 : 32); i++, --off)
1919 FCC_PDATC_MDIO((cmd >> off) & 0x00000001);
1932 io->iop_pdirc &= ~fip->fc_mdio;
1939 for (i = 0, off = 15; i < 16; i++, off--)
1943 if (io->iop_pdatc & fip->fc_mdio)
1951 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1953 for (i = 0; i < 32; i++)
1966 fcc_stop(struct net_device *dev)
1968 volatile fcc_t *fccp;
1969 struct fcc_enet_private *fcp;
1971 fcp = (struct fcc_enet_private *)(dev->priv);
1974 /* Disable transmit/receive */
1975 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1977 #endif /* CONFIG_USE_MDIO */
1980 fcc_restart(struct net_device *dev, int duplex)
1982 volatile fcc_t *fccp;
1983 struct fcc_enet_private *fcp;
1985 fcp = (struct fcc_enet_private *)(dev->priv);
1989 fccp->fcc_fpsmr |= FCC_PSMR_FDE | FCC_PSMR_LPB;
1991 fccp->fcc_fpsmr &= ~(FCC_PSMR_FDE | FCC_PSMR_LPB);
1993 /* Enable transmit/receive */
1994 fccp->fcc_gfmr |= FCC_GFMR_ENR | FCC_GFMR_ENT;
1998 fcc_enet_open(struct net_device *dev)
2000 struct fcc_enet_private *fep = dev->priv;
2002 #ifdef CONFIG_USE_MDIO
2003 fep->sequence_done = 0;
2007 mii_do_cmd(dev, fep->phy->ack_int);
2008 mii_do_cmd(dev, fep->phy->config);
2009 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2010 while(!fep->sequence_done)
2013 mii_do_cmd(dev, fep->phy->startup);
2014 netif_start_queue(dev);
2015 return 0; /* Success */
2017 return -ENODEV; /* No PHY we understand */
2020 netif_start_queue(dev);
2021 return 0; /* Always succeed */
2022 #endif /* CONFIG_USE_MDIO */