2 * Fast Ethernet Controller (FCC) driver for Motorola MPC8260.
3 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
5 * This version of the driver is a combination of the 8xx fec and
6 * 8260 SCC Ethernet drivers. This version has some additional
7 * configuration options, which should probably be moved out of
8 * here. This driver currently works for the EST SBC8260,
9 * SBS Diablo/BCM, Embedded Planet RPX6, TQM8260, and others.
11 * Right now, I am very watseful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets. Since this is a cache coherent processor and CPM,
17 * I could also preallocate SKB's and use them directly on the interface.
21 #include <linux/config.h>
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
38 #include <asm/immap_8260.h>
39 #include <asm/pgtable.h>
40 #include <asm/mpc8260.h>
42 #include <asm/bitops.h>
43 #include <asm/uaccess.h>
44 #include <asm/cpm_8260.h>
46 /* The transmitter timeout
48 #define TX_TIMEOUT (2*HZ)
50 #ifdef CONFIG_USE_MDIO
51 /* Forward declarations of some structures to support different PHYs */
55 void (*funct)(uint mii_reg, struct net_device *dev);
62 const phy_cmd_t *config;
63 const phy_cmd_t *startup;
64 const phy_cmd_t *ack_int;
65 const phy_cmd_t *shutdown;
68 /* Register definitions for the PHY. */
70 #define MII_REG_CR 0 /* Control Register */
71 #define MII_REG_SR 1 /* Status Register */
72 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
73 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
74 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
75 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
76 #define MII_REG_ANER 6 /* A-N Expansion Register */
77 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
78 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
80 /* values for phy_status */
82 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
83 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
84 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
85 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
86 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
87 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
88 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
90 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
91 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
92 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
93 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
94 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
95 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
96 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
97 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
98 #endif /* CONFIG_USE_MDIO */
100 /* The number of Tx and Rx buffers. These are allocated from the page
101 * pool. The code may assume these are power of two, so it is best
102 * to keep them that size.
103 * We don't need to allocate pages for the transmitter. We just use
104 * the skbuffer directly.
106 #define FCC_ENET_RX_PAGES 16
107 #define FCC_ENET_RX_FRSIZE 2048
108 #define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE)
109 #define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES)
110 #define TX_RING_SIZE 16 /* Must be power of two */
111 #define TX_RING_MOD_MASK 15 /* for this to work */
113 /* The FCC stores dest/src/type, data, and checksum for receive packets.
115 #define PKT_MAXBUF_SIZE 1518
116 #define PKT_MINBUF_SIZE 64
118 /* Maximum input DMA size. Must be a should(?) be a multiple of 4.
120 #define PKT_MAXDMA_SIZE 1520
122 /* Maximum input buffer size. Must be a multiple of 32.
124 #define PKT_MAXBLR_SIZE 1536
126 static int fcc_enet_open(struct net_device *dev);
127 static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
128 static int fcc_enet_rx(struct net_device *dev);
129 static irqreturn_t fcc_enet_interrupt(int irq, void *dev_id, struct pt_regs *);
130 static int fcc_enet_close(struct net_device *dev);
131 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev);
132 static void set_multicast_list(struct net_device *dev);
133 static void fcc_restart(struct net_device *dev, int duplex);
134 static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
136 /* These will be configurable for the FCC choice.
137 * Multiple ports can be configured. There is little choice among the
138 * I/O pins to the PHY, except the clocks. We will need some board
139 * dependent clock selection.
140 * Why in the hell did I put these inside #ifdef's? I dunno, maybe to
141 * help show what pins are used for each device.
144 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
145 * but there is little variation among the choices.
147 #define PA1_COL ((uint)0x00000001)
148 #define PA1_CRS ((uint)0x00000002)
149 #define PA1_TXER ((uint)0x00000004)
150 #define PA1_TXEN ((uint)0x00000008)
151 #define PA1_RXDV ((uint)0x00000010)
152 #define PA1_RXER ((uint)0x00000020)
153 #define PA1_TXDAT ((uint)0x00003c00)
154 #define PA1_RXDAT ((uint)0x0003c000)
155 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
156 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
158 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
159 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
161 /* CLK12 is receive, CLK11 is transmit. These are board specific.
163 #define PC_F1RXCLK ((uint)0x00000800)
164 #define PC_F1TXCLK ((uint)0x00000400)
165 #define CMX1_CLK_ROUTE ((uint)0x3e000000)
166 #define CMX1_CLK_MASK ((uint)0xff000000)
168 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
169 * but there is little variation among the choices.
171 #define PB2_TXER ((uint)0x00000001)
172 #define PB2_RXDV ((uint)0x00000002)
173 #define PB2_TXEN ((uint)0x00000004)
174 #define PB2_RXER ((uint)0x00000008)
175 #define PB2_COL ((uint)0x00000010)
176 #define PB2_CRS ((uint)0x00000020)
177 #define PB2_TXDAT ((uint)0x000003c0)
178 #define PB2_RXDAT ((uint)0x00003c00)
179 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
180 PB2_RXER | PB2_RXDV | PB2_TXER)
181 #define PB2_PSORB1 (PB2_TXEN)
182 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
183 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
185 /* CLK13 is receive, CLK14 is transmit. These are board dependent.
187 #define PC_F2RXCLK ((uint)0x00001000)
188 #define PC_F2TXCLK ((uint)0x00002000)
189 #define CMX2_CLK_ROUTE ((uint)0x00250000)
190 #define CMX2_CLK_MASK ((uint)0x00ff0000)
192 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
193 * but there is little variation among the choices.
195 #define PB3_RXDV ((uint)0x00004000)
196 #define PB3_RXER ((uint)0x00008000)
197 #define PB3_TXER ((uint)0x00010000)
198 #define PB3_TXEN ((uint)0x00020000)
199 #define PB3_COL ((uint)0x00040000)
200 #define PB3_CRS ((uint)0x00080000)
201 #define PB3_TXDAT ((uint)0x0f000000)
202 #define PB3_RXDAT ((uint)0x00f00000)
203 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
204 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
205 #define PB3_PSORB1 (0)
206 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
207 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
209 /* CLK15 is receive, CLK16 is transmit. These are board dependent.
211 #define PC_F3RXCLK ((uint)0x00004000)
212 #define PC_F3TXCLK ((uint)0x00008000)
213 #define CMX3_CLK_ROUTE ((uint)0x00003700)
214 #define CMX3_CLK_MASK ((uint)0x0000ff00)
216 /* MII status/control serial interface.
218 #ifdef CONFIG_TQM8260
219 /* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
220 #define PC_MDIO ((uint)0x00000002)
221 #define PC_MDCK ((uint)0x00000001)
223 #define PC_MDIO ((uint)0x00000004)
224 #define PC_MDCK ((uint)0x00000020)
227 /* A table of information for supporting FCCs. This does two things.
228 * First, we know how many FCCs we have and they are always externally
229 * numbered from zero. Second, it holds control register and I/O
230 * information that could be different among board designs.
232 typedef struct fcc_info {
245 static fcc_info_t fcc_ports[] = {
246 #ifdef CONFIG_FCC1_ENET
247 { 0, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
248 (PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
249 # if defined(CONFIG_TQM8260)
252 0x00000004, 0x00000100 },
255 #ifdef CONFIG_FCC2_ENET
256 { 1, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
257 (PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
258 # if defined(CONFIG_TQM8260)
260 # elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260)
261 0x00400000, 0x00200000 },
263 0x00000002, 0x00000080 },
266 #ifdef CONFIG_FCC3_ENET
267 { 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
268 (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
269 # if defined(CONFIG_TQM8260)
272 0x00000001, 0x00000040 },
277 /* The FCC buffer descriptors track the ring buffers. The rx_bd_base and
278 * tx_bd_base always point to the base of the buffer descriptors. The
279 * cur_rx and cur_tx point to the currently available buffer.
280 * The dirty_tx tracks the current buffer that is being sent by the
281 * controller. The cur_tx and dirty_tx are equal under both completely
282 * empty and completely full conditions. The empty/ready indicator in
283 * the buffer descriptor determines the actual condition.
285 struct fcc_enet_private {
286 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
287 struct sk_buff* tx_skbuff[TX_RING_SIZE];
291 /* CPM dual port RAM relative addresses.
293 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
295 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
296 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
297 volatile fcc_t *fccp;
298 volatile fcc_enet_t *ep;
299 struct net_device_stats stats;
303 #ifdef CONFIG_USE_MDIO
308 struct tq_struct phy_task;
313 #endif /* CONFIG_USE_MDIO */
322 static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
323 volatile immap_t *immap);
324 static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
325 static void init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
326 volatile immap_t *immap);
327 static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
328 volatile immap_t *immap);
330 #ifdef CONFIG_USE_MDIO
331 static int mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *));
332 static uint mii_send_receive(fcc_info_t *fip, uint cmd);
334 static void fcc_stop(struct net_device *dev);
336 /* Make MII read/write commands for the FCC.
338 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
339 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
342 #endif /* CONFIG_USE_MDIO */
346 fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
348 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
352 /* Link is down or autonegotiation is in progress. */
356 /* Fill in a Tx ring entry */
359 #ifndef final_version
360 if (bdp->cbd_sc & BD_ENET_TX_READY) {
361 /* Ooops. All transmit buffers are full. Bail out.
362 * This should not happen, since cep->tx_full should be set.
364 printk("%s: tx queue full!.\n", dev->name);
369 /* Clear all of the status flags. */
370 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
372 /* If the frame is short, tell CPM to pad it. */
373 if (skb->len <= ETH_ZLEN)
374 bdp->cbd_sc |= BD_ENET_TX_PAD;
376 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
378 /* Set buffer length and buffer pointer. */
379 bdp->cbd_datlen = skb->len;
380 bdp->cbd_bufaddr = __pa(skb->data);
382 /* Save skb pointer. */
383 cep->tx_skbuff[cep->skb_cur] = skb;
385 cep->stats.tx_bytes += skb->len;
386 cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
388 spin_lock_irq(&cep->lock);
390 /* Send it on its way. Tell CPM its ready, interrupt when done,
391 * its the last BD of the frame, and to put the CRC on the end.
393 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
396 /* Errata says don't do this. */
397 cep->fccp->fcc_ftodr = 0x8000;
399 dev->trans_start = jiffies;
401 /* If this was the last BD in the ring, start at the beginning again. */
402 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
403 bdp = cep->tx_bd_base;
407 if (bdp->cbd_sc & BD_ENET_TX_READY) {
408 netif_stop_queue(dev);
412 cep->cur_tx = (cbd_t *)bdp;
414 spin_unlock_irq(&cep->lock);
421 fcc_enet_timeout(struct net_device *dev)
423 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
425 printk("%s: transmit timed out.\n", dev->name);
426 cep->stats.tx_errors++;
427 #ifndef final_version
431 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
432 cep->cur_tx, cep->tx_full ? " (full)" : "",
434 bdp = cep->tx_bd_base;
435 printk(" Tx @base %p :\n", bdp);
436 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
437 printk("%04x %04x %08x\n",
441 bdp = cep->rx_bd_base;
442 printk(" Rx @base %p :\n", bdp);
443 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
444 printk("%04x %04x %08x\n",
451 netif_wake_queue(dev);
454 /* The interrupt handler. */
456 fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
458 struct net_device *dev = dev_id;
459 volatile struct fcc_enet_private *cep;
464 cep = (struct fcc_enet_private *)dev->priv;
466 /* Get the interrupt events that caused us to be here.
468 int_events = cep->fccp->fcc_fcce;
469 cep->fccp->fcc_fcce = int_events;
472 /* Handle receive event in its own function.
474 if (int_events & FCC_ENET_RXF)
477 /* Check for a transmit error. The manual is a little unclear
478 * about this, so the debug code until I get it figured out. It
479 * appears that if TXE is set, then TXB is not set. However,
480 * if carrier sense is lost during frame transmission, the TXE
481 * bit is set, "and continues the buffer transmission normally."
482 * I don't know if "normally" implies TXB is set when the buffer
483 * descriptor is closed.....trial and error :-).
486 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
488 if (int_events & (FCC_ENET_TXE | FCC_ENET_TXB)) {
489 spin_lock(&cep->lock);
491 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
492 if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
495 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
496 cep->stats.tx_heartbeat_errors++;
497 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
498 cep->stats.tx_window_errors++;
499 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
500 cep->stats.tx_aborted_errors++;
501 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
502 cep->stats.tx_fifo_errors++;
503 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
504 cep->stats.tx_carrier_errors++;
507 /* No heartbeat or Lost carrier are not really bad errors.
508 * The others require a restart transmit command.
511 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
513 cep->stats.tx_errors++;
516 cep->stats.tx_packets++;
518 /* Deferred means some collisions occurred during transmit,
519 * but we eventually sent the packet OK.
521 if (bdp->cbd_sc & BD_ENET_TX_DEF)
522 cep->stats.collisions++;
524 /* Free the sk buffer associated with this last transmit. */
525 dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
526 cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;
528 /* Update pointer to next buffer descriptor to be transmitted. */
529 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
530 bdp = cep->tx_bd_base;
534 /* I don't know if we can be held off from processing these
535 * interrupts for more than one frame time. I really hope
536 * not. In such a case, we would now want to check the
537 * currently available BD (cur_tx) and determine if any
538 * buffers between the dirty_tx and cur_tx have also been
539 * sent. We would want to process anything in between that
540 * does not have BD_ENET_TX_READY set.
543 /* Since we have freed up a buffer, the ring is no longer
548 if (netif_queue_stopped(dev)) {
549 netif_wake_queue(dev);
553 cep->dirty_tx = (cbd_t *)bdp;
557 volatile cpm8260_t *cp;
559 /* Some transmit errors cause the transmitter to shut
560 * down. We now issue a restart transmit. Since the
561 * errors close the BD and update the pointers, the restart
562 * _should_ pick up without having to reset any of our
563 * pointers either. Also, To workaround 8260 device erratum
564 * CPM37, we must disable and then re-enable the transmitter
565 * following a Late Collision, Underrun, or Retry Limit error.
567 cep->fccp->fcc_gfmr &= ~FCC_GFMR_ENT;
568 udelay(10); /* wait a few microseconds just on principle */
569 cep->fccp->fcc_gfmr |= FCC_GFMR_ENT;
573 mk_cr_cmd(cep->fip->fc_cpmpage, cep->fip->fc_cpmblock,
574 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG;
575 while (cp->cp_cpcr & CPM_CR_FLG);
577 spin_unlock(&cep->lock);
580 /* Check for receive busy, i.e. packets coming but no place to
583 if (int_events & FCC_ENET_BSY) {
584 cep->stats.rx_dropped++;
589 /* During a receive, the cur_rx points to the current incoming buffer.
590 * When we update through the ring, if the next incoming buffer has
591 * not been given to the system, we just set the empty indicator,
592 * effectively tossing the packet.
595 fcc_enet_rx(struct net_device *dev)
597 struct fcc_enet_private *cep;
602 cep = (struct fcc_enet_private *)dev->priv;
604 /* First, grab all of the stats for the incoming packet.
605 * These get messed up if we get called due to a busy condition.
610 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
613 #ifndef final_version
614 /* Since we have allocated space to hold a complete frame, both
615 * the first and last indicators should be set.
617 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
618 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
619 printk("CPM ENET: rcv is not first+last\n");
622 /* Frame too long or too short. */
623 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
624 cep->stats.rx_length_errors++;
625 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
626 cep->stats.rx_frame_errors++;
627 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
628 cep->stats.rx_crc_errors++;
629 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
630 cep->stats.rx_crc_errors++;
631 if (bdp->cbd_sc & BD_ENET_RX_CL) /* Late Collision */
632 cep->stats.rx_frame_errors++;
635 (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | BD_ENET_RX_CR
636 | BD_ENET_RX_OV | BD_ENET_RX_CL)))
638 /* Process the incoming frame. */
639 cep->stats.rx_packets++;
641 /* Remove the FCS from the packet length. */
642 pkt_len = bdp->cbd_datlen - 4;
643 cep->stats.rx_bytes += pkt_len;
645 /* This does 16 byte alignment, much more than we need. */
646 skb = dev_alloc_skb(pkt_len);
649 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
650 cep->stats.rx_dropped++;
654 skb_put(skb,pkt_len); /* Make room */
655 eth_copy_and_sum(skb,
656 (unsigned char *)__va(bdp->cbd_bufaddr),
658 skb->protocol=eth_type_trans(skb,dev);
663 /* Clear the status flags for this buffer. */
664 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
666 /* Mark the buffer empty. */
667 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
669 /* Update BD pointer to next entry. */
670 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
671 bdp = cep->rx_bd_base;
676 cep->cur_rx = (cbd_t *)bdp;
682 fcc_enet_close(struct net_device *dev)
684 /* Don't know what to do yet. */
685 netif_stop_queue(dev);
690 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev)
692 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
697 #ifdef CONFIG_USE_MDIO
699 /* NOTE: Most of the following comes from the FEC driver for 860. The
700 * overall structure of MII code has been retained (as it's proved stable
701 * and well-tested), but actual transfer requests are processed "at once"
702 * instead of being queued (there's no interrupt-driven MII transfer
703 * mechanism, one has to toggle the data/clock bits manually).
706 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
708 struct fcc_enet_private *fep;
711 /* Add PHY address to register command. */
713 regval |= fep->phy_addr << 23;
717 tmp = mii_send_receive(fep->fip, regval);
724 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
731 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
732 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
735 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
737 volatile struct fcc_enet_private *fep = dev->priv;
738 uint s = fep->phy_status;
740 s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
742 if (mii_reg & 0x0004)
744 if (mii_reg & 0x0010)
746 if (mii_reg & 0x0020)
750 fep->link = (s & PHY_STAT_LINK) ? 1 : 0;
753 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
755 volatile struct fcc_enet_private *fep = dev->priv;
756 uint s = fep->phy_status;
758 s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
760 if (mii_reg & 0x1000)
762 if (mii_reg & 0x4000)
768 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
770 volatile struct fcc_enet_private *fep = dev->priv;
771 uint s = fep->phy_status;
773 s &= ~(PHY_CONF_SPMASK);
775 if (mii_reg & 0x0020)
777 if (mii_reg & 0x0040)
779 if (mii_reg & 0x0080)
780 s |= PHY_CONF_100HDX;
781 if (mii_reg & 0x00100)
782 s |= PHY_CONF_100FDX;
786 /* ------------------------------------------------------------------------- */
787 /* The Level one LXT970 is used by many boards */
789 #ifdef CONFIG_FCC_LXT970
791 #define MII_LXT970_MIRROR 16 /* Mirror register */
792 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
793 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
794 #define MII_LXT970_CONFIG 19 /* Configuration Register */
795 #define MII_LXT970_CSR 20 /* Chip Status Register */
797 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
799 volatile struct fcc_enet_private *fep = dev->priv;
800 uint s = fep->phy_status;
802 s &= ~(PHY_STAT_SPMASK);
804 if (mii_reg & 0x0800) {
805 if (mii_reg & 0x1000)
806 s |= PHY_STAT_100FDX;
808 s |= PHY_STAT_100HDX;
810 if (mii_reg & 0x1000)
819 static phy_info_t phy_info_lxt970 = {
823 (const phy_cmd_t []) { /* config */
825 // { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
827 /* Set default operation of 100-TX....for some reason
828 * some of these bits are set on power up, which is wrong.
830 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
832 { mk_mii_read(MII_REG_CR), mii_parse_cr },
833 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
836 (const phy_cmd_t []) { /* startup - enable interrupts */
837 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
838 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
841 (const phy_cmd_t []) { /* ack_int */
842 /* read SR and ISR to acknowledge */
844 { mk_mii_read(MII_REG_SR), mii_parse_sr },
845 { mk_mii_read(MII_LXT970_ISR), NULL },
847 /* find out the current status */
849 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
852 (const phy_cmd_t []) { /* shutdown - disable interrupts */
853 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
858 #endif /* CONFIG_FEC_LXT970 */
860 /* ------------------------------------------------------------------------- */
861 /* The Level one LXT971 is used on some of my custom boards */
863 #ifdef CONFIG_FCC_LXT971
865 /* register definitions for the 971 */
867 #define MII_LXT971_PCR 16 /* Port Control Register */
868 #define MII_LXT971_SR2 17 /* Status Register 2 */
869 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
870 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
871 #define MII_LXT971_LCR 20 /* LED Control Register */
872 #define MII_LXT971_TCR 30 /* Transmit Control Register */
875 * I had some nice ideas of running the MDIO faster...
876 * The 971 should support 8MHz and I tried it, but things acted really
877 * weird, so 2.5 MHz ought to be enough for anyone...
880 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
882 volatile struct fcc_enet_private *fep = dev->priv;
883 uint s = fep->phy_status;
885 s &= ~(PHY_STAT_SPMASK);
887 if (mii_reg & 0x4000) {
888 if (mii_reg & 0x0200)
889 s |= PHY_STAT_100FDX;
891 s |= PHY_STAT_100HDX;
893 if (mii_reg & 0x0200)
898 if (mii_reg & 0x0008)
904 static phy_info_t phy_info_lxt971 = {
908 (const phy_cmd_t []) { /* config */
909 // { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
910 { mk_mii_read(MII_REG_CR), mii_parse_cr },
911 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
914 (const phy_cmd_t []) { /* startup - enable interrupts */
915 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
916 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
918 /* Somehow does the 971 tell me that the link is down
919 * the first read after power-up.
920 * read here to get a valid value in ack_int */
922 { mk_mii_read(MII_REG_SR), mii_parse_sr },
925 (const phy_cmd_t []) { /* ack_int */
926 /* find out the current status */
928 { mk_mii_read(MII_REG_SR), mii_parse_sr },
929 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
931 /* we only need to read ISR to acknowledge */
933 { mk_mii_read(MII_LXT971_ISR), NULL },
936 (const phy_cmd_t []) { /* shutdown - disable interrupts */
937 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
942 #endif /* CONFIG_FEC_LXT970 */
945 /* ------------------------------------------------------------------------- */
946 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
948 #ifdef CONFIG_FCC_QS6612
950 /* register definitions */
952 #define MII_QS6612_MCR 17 /* Mode Control Register */
953 #define MII_QS6612_FTR 27 /* Factory Test Register */
954 #define MII_QS6612_MCO 28 /* Misc. Control Register */
955 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
956 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
957 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
959 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
961 volatile struct fcc_enet_private *fep = dev->priv;
962 uint s = fep->phy_status;
964 s &= ~(PHY_STAT_SPMASK);
966 switch((mii_reg >> 2) & 7) {
967 case 1: s |= PHY_STAT_10HDX; break;
968 case 2: s |= PHY_STAT_100HDX; break;
969 case 5: s |= PHY_STAT_10FDX; break;
970 case 6: s |= PHY_STAT_100FDX; break;
976 static phy_info_t phy_info_qs6612 = {
980 (const phy_cmd_t []) { /* config */
981 // { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
983 /* The PHY powers up isolated on the RPX,
984 * so send a command to allow operation.
987 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
989 /* parse cr and anar to get some info */
991 { mk_mii_read(MII_REG_CR), mii_parse_cr },
992 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
995 (const phy_cmd_t []) { /* startup - enable interrupts */
996 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
997 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1000 (const phy_cmd_t []) { /* ack_int */
1002 /* we need to read ISR, SR and ANER to acknowledge */
1004 { mk_mii_read(MII_QS6612_ISR), NULL },
1005 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1006 { mk_mii_read(MII_REG_ANER), NULL },
1008 /* read pcr to get info */
1010 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1013 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1014 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1020 #endif /* CONFIG_FEC_QS6612 */
1023 static phy_info_t *phy_info[] = {
1025 #ifdef CONFIG_FCC_LXT970
1027 #endif /* CONFIG_FEC_LXT970 */
1029 #ifdef CONFIG_FCC_LXT971
1031 #endif /* CONFIG_FEC_LXT971 */
1033 #ifdef CONFIG_FCC_QS6612
1035 #endif /* CONFIG_FEC_LXT971 */
1040 static void mii_display_status(struct net_device *dev)
1042 volatile struct fcc_enet_private *fep = dev->priv;
1043 uint s = fep->phy_status;
1045 if (!fep->link && !fep->old_link) {
1046 /* Link is still down - don't print anything */
1050 printk("%s: status: ", dev->name);
1053 printk("link down");
1057 switch(s & PHY_STAT_SPMASK) {
1058 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1059 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1060 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1061 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1063 printk(", Unknown speed/duplex");
1066 if (s & PHY_STAT_ANC)
1067 printk(", auto-negotiation complete");
1070 if (s & PHY_STAT_FAULT)
1071 printk(", remote fault");
1076 static void mii_display_config(struct net_device *dev)
1078 volatile struct fcc_enet_private *fep = dev->priv;
1079 uint s = fep->phy_status;
1081 printk("%s: config: auto-negotiation ", dev->name);
1083 if (s & PHY_CONF_ANE)
1088 if (s & PHY_CONF_100FDX)
1090 if (s & PHY_CONF_100HDX)
1092 if (s & PHY_CONF_10FDX)
1094 if (s & PHY_CONF_10HDX)
1096 if (!(s & PHY_CONF_SPMASK))
1097 printk(", No speed/duplex selected?");
1099 if (s & PHY_CONF_LOOP)
1100 printk(", loopback enabled");
1104 fep->sequence_done = 1;
1107 static void mii_relink(struct net_device *dev)
1109 struct fcc_enet_private *fep = dev->priv;
1112 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1113 mii_display_status(dev);
1114 fep->old_link = fep->link;
1119 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1121 fcc_restart(dev, duplex);
1127 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1129 struct fcc_enet_private *fep = dev->priv;
1131 fep->phy_task.routine = (void *)mii_relink;
1132 fep->phy_task.data = dev;
1133 schedule_task(&fep->phy_task);
1136 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1138 struct fcc_enet_private *fep = dev->priv;
1140 fep->phy_task.routine = (void *)mii_display_config;
1141 fep->phy_task.data = dev;
1142 schedule_task(&fep->phy_task);
1147 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1149 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1153 /* Read remainder of PHY ID.
1156 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1158 struct fcc_enet_private *fep;
1162 fep->phy_id |= (mii_reg & 0xffff);
1164 for(i = 0; phy_info[i]; i++)
1165 if(phy_info[i]->id == (fep->phy_id >> 4))
1169 panic("%s: PHY id 0x%08x is not supported!\n",
1170 dev->name, fep->phy_id);
1172 fep->phy = phy_info[i];
1174 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1175 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1178 /* Scan all of the MII PHY addresses looking for someone to respond
1179 * with a valid ID. This usually happens quickly.
1182 mii_discover_phy(uint mii_reg, struct net_device *dev)
1184 struct fcc_enet_private *fep;
1189 if ((phytype = (mii_reg & 0xfff)) != 0xfff) {
1191 /* Got first part of ID, now get remainder. */
1192 fep->phy_id = phytype << 16;
1193 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1196 if (fep->phy_addr < 32) {
1197 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1200 printk("fec: No PHY device found.\n");
1205 /* This interrupt occurs when the PHY detects a link change. */
1207 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1209 struct net_device *dev = dev_id;
1210 struct fcc_enet_private *fep = dev->priv;
1212 mii_do_cmd(dev, fep->phy->ack_int);
1213 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1217 #endif /* CONFIG_USE_MDIO */
1219 /* Set or clear the multicast filter for this adaptor.
1220 * Skeleton taken from sunlance driver.
1221 * The CPM Ethernet implementation allows Multicast as well as individual
1222 * MAC address filtering. Some of the drivers check to make sure it is
1223 * a group multicast address, and discard those that are not. I guess I
1224 * will do the same for now, but just remove the test if you want
1225 * individual filtering as well (do the upper net layers want or support
1226 * this kind of feature?).
1229 set_multicast_list(struct net_device *dev)
1231 struct fcc_enet_private *cep;
1232 struct dev_mc_list *dmi;
1233 u_char *mcptr, *tdptr;
1234 volatile fcc_enet_t *ep;
1237 cep = (struct fcc_enet_private *)dev->priv;
1240 /* Get pointer to FCC area in parameter RAM.
1242 ep = (fcc_enet_t *)dev->base_addr;
1244 if (dev->flags&IFF_PROMISC) {
1246 /* Log any net taps. */
1247 printk("%s: Promiscuous mode enabled.\n", dev->name);
1248 cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
1251 cep->fccp->fcc_fpsmr &= ~FCC_PSMR_PRO;
1253 if (dev->flags & IFF_ALLMULTI) {
1254 /* Catch all multicast addresses, so set the
1255 * filter to all 1's.
1257 ep->fen_gaddrh = 0xffffffff;
1258 ep->fen_gaddrl = 0xffffffff;
1261 /* Clear filter and add the addresses in the list.
1268 for (i=0; i<dev->mc_count; i++) {
1270 /* Only support group multicast for now.
1272 if (!(dmi->dmi_addr[0] & 1))
1275 /* The address in dmi_addr is LSB first,
1276 * and taddr is MSB first. We have to
1277 * copy bytes MSB first from dmi_addr.
1279 mcptr = (u_char *)dmi->dmi_addr + 5;
1280 tdptr = (u_char *)&ep->fen_taddrh;
1282 *tdptr++ = *mcptr--;
1284 /* Ask CPM to run CRC and set bit in
1287 cpmp->cp_cpcr = mk_cr_cmd(cep->fip->fc_cpmpage,
1288 cep->fip->fc_cpmblock, 0x0c,
1289 CPM_CR_SET_GADDR) | CPM_CR_FLG;
1291 while (cpmp->cp_cpcr & CPM_CR_FLG);
1298 /* Set the individual MAC address.
1300 int fcc_enet_set_mac_address(struct net_device *dev, void *p)
1302 struct sockaddr *addr= (struct sockaddr *) p;
1303 struct fcc_enet_private *cep;
1304 volatile fcc_enet_t *ep;
1308 cep = (struct fcc_enet_private *)(dev->priv);
1311 if (netif_running(dev))
1314 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1316 eap = (unsigned char *) &(ep->fen_paddrh);
1317 for (i=5; i>=0; i--)
1318 *eap++ = addr->sa_data[i];
1324 /* Initialize the CPM Ethernet on FCC.
1326 static int __init fec_enet_init(void)
1328 struct net_device *dev;
1329 struct fcc_enet_private *cep;
1332 volatile immap_t *immap;
1333 volatile iop8260_t *io;
1335 immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
1336 io = &immap->im_ioport;
1338 np = sizeof(fcc_ports) / sizeof(fcc_info_t);
1342 /* Create an Ethernet device instance.
1344 dev = alloc_etherdev(sizeof(*cep));
1349 spin_lock_init(&cep->lock);
1352 init_fcc_shutdown(fip, cep, immap);
1353 init_fcc_ioports(fip, io, immap);
1354 init_fcc_param(fip, dev, immap);
1356 dev->base_addr = (unsigned long)(cep->ep);
1358 /* The CPM Ethernet specific entries in the device
1361 dev->open = fcc_enet_open;
1362 dev->hard_start_xmit = fcc_enet_start_xmit;
1363 dev->tx_timeout = fcc_enet_timeout;
1364 dev->watchdog_timeo = TX_TIMEOUT;
1365 dev->stop = fcc_enet_close;
1366 dev->get_stats = fcc_enet_get_stats;
1367 dev->set_multicast_list = set_multicast_list;
1368 dev->set_mac_address = fcc_enet_set_mac_address;
1370 init_fcc_startup(fip, dev);
1372 err = register_netdev(dev);
1378 printk("%s: FCC ENET Version 0.3, ", dev->name);
1380 printk("%02x:", dev->dev_addr[i]);
1381 printk("%02x\n", dev->dev_addr[5]);
1383 #ifdef CONFIG_USE_MDIO
1384 /* Queue up command to detect the PHY and initialize the
1385 * remainder of the interface.
1388 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1389 #endif /* CONFIG_USE_MDIO */
1396 module_init(fec_enet_init);
1398 /* Make sure the device is shut down during initialization.
1401 init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
1402 volatile immap_t *immap)
1404 volatile fcc_enet_t *ep;
1405 volatile fcc_t *fccp;
1407 /* Get pointer to FCC area in parameter RAM.
1409 ep = (fcc_enet_t *)(&immap->im_dprambase[fip->fc_proff]);
1411 /* And another to the FCC register area.
1413 fccp = (volatile fcc_t *)(&immap->im_fcc[fip->fc_fccnum]);
1414 cep->fccp = fccp; /* Keep the pointers handy */
1417 /* Disable receive and transmit in case someone left it running.
1419 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1422 /* Initialize the I/O pins for the FCC Ethernet.
1425 init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
1426 volatile immap_t *immap)
1429 /* FCC1 pins are on port A/C. FCC2/3 are port B/C.
1431 if (fip->fc_proff == PROFF_FCC1) {
1432 /* Configure port A and C pins for FCC1 Ethernet.
1434 io->iop_pdira &= ~PA1_DIRA0;
1435 io->iop_pdira |= PA1_DIRA1;
1436 io->iop_psora &= ~PA1_PSORA0;
1437 io->iop_psora |= PA1_PSORA1;
1438 io->iop_ppara |= (PA1_DIRA0 | PA1_DIRA1);
1440 if (fip->fc_proff == PROFF_FCC2) {
1441 /* Configure port B and C pins for FCC Ethernet.
1443 io->iop_pdirb &= ~PB2_DIRB0;
1444 io->iop_pdirb |= PB2_DIRB1;
1445 io->iop_psorb &= ~PB2_PSORB0;
1446 io->iop_psorb |= PB2_PSORB1;
1447 io->iop_pparb |= (PB2_DIRB0 | PB2_DIRB1);
1449 if (fip->fc_proff == PROFF_FCC3) {
1450 /* Configure port B and C pins for FCC Ethernet.
1452 io->iop_pdirb &= ~PB3_DIRB0;
1453 io->iop_pdirb |= PB3_DIRB1;
1454 io->iop_psorb &= ~PB3_PSORB0;
1455 io->iop_psorb |= PB3_PSORB1;
1456 io->iop_pparb |= (PB3_DIRB0 | PB3_DIRB1);
1459 /* Port C has clocks......
1461 io->iop_psorc &= ~(fip->fc_trxclocks);
1462 io->iop_pdirc &= ~(fip->fc_trxclocks);
1463 io->iop_pparc |= fip->fc_trxclocks;
1465 #ifdef CONFIG_USE_MDIO
1466 /* ....and the MII serial clock/data.
1468 io->iop_pdatc |= (fip->fc_mdio | fip->fc_mdck);
1469 io->iop_podrc &= ~(fip->fc_mdio | fip->fc_mdck);
1470 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1471 io->iop_pparc &= ~(fip->fc_mdio | fip->fc_mdck);
1472 #endif /* CONFIG_USE_MDIO */
1474 /* Configure Serial Interface clock routing.
1475 * First, clear all FCC bits to zero,
1476 * then set the ones we want.
1478 immap->im_cpmux.cmx_fcr &= ~(fip->fc_clockmask);
1479 immap->im_cpmux.cmx_fcr |= fip->fc_clockroute;
1483 init_fcc_param(fcc_info_t *fip, struct net_device *dev,
1484 volatile immap_t *immap)
1487 unsigned long mem_addr;
1490 struct fcc_enet_private *cep;
1491 volatile fcc_enet_t *ep;
1492 volatile cbd_t *bdp;
1493 volatile cpm8260_t *cp;
1495 cep = (struct fcc_enet_private *)(dev->priv);
1501 /* Zero the whole thing.....I must have missed some individually.
1502 * It works when I do this.
1504 memset((char *)ep, 0, sizeof(fcc_enet_t));
1506 /* Allocate space for the buffer descriptors in the DP ram.
1507 * These are relative offsets in the DP ram address space.
1508 * Initialize base addresses for the buffer descriptors.
1511 /* I really want to do this, but for some reason it doesn't
1512 * work with the data cache enabled, so I allocate from the
1513 * main memory instead.
1515 i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1516 ep->fen_genfcc.fcc_rbase = (uint)&immap->im_dprambase[i];
1517 cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1519 i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1520 ep->fen_genfcc.fcc_tbase = (uint)&immap->im_dprambase[i];
1521 cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1523 cep->rx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1524 ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
1525 cep->tx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1526 ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
1529 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
1530 cep->cur_rx = cep->rx_bd_base;
1532 ep->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1533 ep->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1535 /* Set maximum bytes per receive buffer.
1536 * It must be a multiple of 32.
1538 ep->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
1540 /* Allocate space in the reserved FCC area of DPRAM for the
1541 * internal buffers. No one uses this space (yet), so we
1542 * can do this. Later, we will add resource management for
1545 mem_addr = CPM_FCC_SPECIAL_BASE + (fip->fc_fccnum * 128);
1546 ep->fen_genfcc.fcc_riptr = mem_addr;
1547 ep->fen_genfcc.fcc_tiptr = mem_addr+32;
1548 ep->fen_padptr = mem_addr+64;
1549 memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32);
1551 ep->fen_genfcc.fcc_rbptr = 0;
1552 ep->fen_genfcc.fcc_tbptr = 0;
1553 ep->fen_genfcc.fcc_rcrc = 0;
1554 ep->fen_genfcc.fcc_tcrc = 0;
1555 ep->fen_genfcc.fcc_res1 = 0;
1556 ep->fen_genfcc.fcc_res2 = 0;
1558 ep->fen_camptr = 0; /* CAM isn't used in this driver */
1560 /* Set CRC preset and mask.
1562 ep->fen_cmask = 0xdebb20e3;
1563 ep->fen_cpres = 0xffffffff;
1565 ep->fen_crcec = 0; /* CRC Error counter */
1566 ep->fen_alec = 0; /* alignment error counter */
1567 ep->fen_disfc = 0; /* discard frame counter */
1568 ep->fen_retlim = 15; /* Retry limit threshold */
1569 ep->fen_pper = 0; /* Normal persistence */
1571 /* Clear hash filter tables.
1578 /* Clear the Out-of-sequence TxBD.
1580 ep->fen_tfcstat = 0;
1584 ep->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
1585 ep->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
1587 /* Set Ethernet station address.
1589 * This is supplied in the board information structure, so we
1590 * copy that into the controller.
1591 * So, far we have only been given one Ethernet address. We make
1592 * it unique by setting a few bits in the upper byte of the
1593 * non-static part of the address.
1595 eap = (unsigned char *)&(ep->fen_paddrh);
1596 for (i=5; i>=0; i--) {
1598 dev->dev_addr[i] = bd->bi_enetaddr[i];
1599 dev->dev_addr[i] |= (1 << (7 - fip->fc_fccnum));
1600 *eap++ = dev->dev_addr[i];
1603 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
1611 ep->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
1612 ep->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
1614 /* Clear stat counters, in case we ever enable RMON.
1631 ep->fen_rfthr = 0; /* Suggested by manual */
1635 /* Now allocate the host memory pages and initialize the
1636 * buffer descriptors.
1638 bdp = cep->tx_bd_base;
1639 for (i=0; i<TX_RING_SIZE; i++) {
1641 /* Initialize the BD for every fragment in the page.
1644 bdp->cbd_datlen = 0;
1645 bdp->cbd_bufaddr = 0;
1649 /* Set the last buffer to wrap.
1652 bdp->cbd_sc |= BD_SC_WRAP;
1654 bdp = cep->rx_bd_base;
1655 for (i=0; i<FCC_ENET_RX_PAGES; i++) {
1659 mem_addr = __get_free_page(GFP_KERNEL);
1661 /* Initialize the BD for every fragment in the page.
1663 for (j=0; j<FCC_ENET_RX_FRPPG; j++) {
1664 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
1665 bdp->cbd_datlen = 0;
1666 bdp->cbd_bufaddr = __pa(mem_addr);
1667 mem_addr += FCC_ENET_RX_FRSIZE;
1672 /* Set the last buffer to wrap.
1675 bdp->cbd_sc |= BD_SC_WRAP;
1677 /* Let's re-initialize the channel now. We have to do it later
1678 * than the manual describes because we have just now finished
1679 * the BD initialization.
1681 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, 0x0c,
1682 CPM_CR_INIT_TRX) | CPM_CR_FLG;
1683 while (cp->cp_cpcr & CPM_CR_FLG);
1685 cep->skb_cur = cep->skb_dirty = 0;
1691 init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
1693 volatile fcc_t *fccp;
1694 struct fcc_enet_private *cep;
1696 cep = (struct fcc_enet_private *)(dev->priv);
1699 fccp->fcc_fcce = 0xffff; /* Clear any pending events */
1701 /* Enable interrupts for transmit error, complete frame
1702 * received, and any transmit buffer we have also set the
1705 fccp->fcc_fccm = (FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
1707 /* Install our interrupt handler.
1709 if (request_irq(fip->fc_interrupt, fcc_enet_interrupt, 0,
1711 printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);
1713 #ifdef CONFIG_USE_MDIO
1714 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0,
1716 printk("Can't get MII IRQ %d\n", fip->fc_interrupt);
1717 #endif /* CONFIG_USE_MDIO */
1719 /* Set GFMR to enable Ethernet operating mode.
1721 fccp->fcc_gfmr = (FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
1723 /* Set sync/delimiters.
1725 fccp->fcc_fdsr = 0xd555;
1727 /* Set protocol specific processing mode for Ethernet.
1728 * This has to be adjusted for Full Duplex operation after we can
1729 * determine how to detect that.
1731 fccp->fcc_fpsmr = FCC_PSMR_ENCRC;
1733 #ifdef CONFIG_ADS8260
1736 ads_csr_addr[1] |= BCSR1_FETH_RST; /* Remove reset */
1737 ads_csr_addr[1] &= ~BCSR1_FETHIEN; /* Enable */
1740 #if defined(CONFIG_USE_MDIO) || defined(CONFIG_TQM8260)
1741 /* start in full duplex mode, and negotiate speed
1743 fcc_restart (dev, 1);
1745 /* start in half duplex mode
1747 fcc_restart (dev, 0);
1751 #ifdef CONFIG_USE_MDIO
1752 /* MII command/status interface.
1753 * I'm not going to describe all of the details. You can find the
1754 * protocol definition in many other places, including the data sheet
1755 * of most PHY parts.
1756 * I wonder what "they" were thinking (maybe weren't) when they leave
1757 * the I2C in the CPM but I have to toggle these bits......
1760 #define FCC_PDATC_MDIO(bit) \
1762 io->iop_pdatc |= fip->fc_mdio; \
1764 io->iop_pdatc &= ~fip->fc_mdio;
1766 #define FCC_PDATC_MDC(bit) \
1768 io->iop_pdatc |= fip->fc_mdck; \
1770 io->iop_pdatc &= ~fip->fc_mdck;
1773 mii_send_receive(fcc_info_t *fip, uint cmd)
1776 int read_op, i, off;
1777 volatile immap_t *immap;
1778 volatile iop8260_t *io;
1780 immap = (immap_t *)IMAP_ADDR;
1781 io = &immap->im_ioport;
1783 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1785 read_op = ((cmd & 0xf0000000) == 0x60000000);
1789 for (i = 0; i < 32; i++)
1800 for (i = 0, off = 31; i < (read_op ? 14 : 32); i++, --off)
1803 FCC_PDATC_MDIO((cmd >> off) & 0x00000001);
1816 io->iop_pdirc &= ~fip->fc_mdio;
1823 for (i = 0, off = 15; i < 16; i++, off--)
1827 if (io->iop_pdatc & fip->fc_mdio)
1835 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1837 for (i = 0; i < 32; i++)
1850 fcc_stop(struct net_device *dev)
1852 volatile fcc_t *fccp;
1853 struct fcc_enet_private *fcp;
1855 fcp = (struct fcc_enet_private *)(dev->priv);
1858 /* Disable transmit/receive */
1859 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1861 #endif /* CONFIG_USE_MDIO */
1864 fcc_restart(struct net_device *dev, int duplex)
1866 volatile fcc_t *fccp;
1867 struct fcc_enet_private *fcp;
1869 fcp = (struct fcc_enet_private *)(dev->priv);
1873 fccp->fcc_fpsmr |= FCC_PSMR_FDE;
1875 fccp->fcc_fpsmr &= ~FCC_PSMR_FDE;
1877 /* Enable transmit/receive */
1878 fccp->fcc_gfmr |= FCC_GFMR_ENR | FCC_GFMR_ENT;
1882 fcc_enet_open(struct net_device *dev)
1884 struct fcc_enet_private *fep = dev->priv;
1886 #ifdef CONFIG_USE_MDIO
1887 fep->sequence_done = 0;
1891 mii_do_cmd(dev, fep->phy->ack_int);
1892 mii_do_cmd(dev, fep->phy->config);
1893 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1894 while(!fep->sequence_done)
1897 mii_do_cmd(dev, fep->phy->startup);
1898 netif_start_queue(dev);
1899 return 0; /* Success */
1901 return -ENODEV; /* No PHY we understand */
1904 netif_start_queue(dev);
1905 return 0; /* Always succeed */
1906 #endif /* CONFIG_USE_MDIO */