2 * General Purpose functions for the global management of the
3 * Communication Processor Module.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
6 * In addition to the individual control of the communication
7 * channels, there are a few functions that globally affect the
8 * communication processor.
10 * Buffer descriptors must be allocated from the dual ported memory
11 * space. The allocator for that is here. When the communication
12 * process is reset, we reclaim the memory available. There is
13 * currently no deallocator for this memory.
14 * The amount of space available is platform dependent. On the
15 * MBX, the EPPC software loads additional microcode into the
16 * communication processor, and uses some of the DP ram for this
17 * purpose. Current, the first 512 bytes and the last 256 bytes of
18 * memory are used. Right now I am conservative and only use the
19 * memory that can never be used for microcode. If there are
20 * applications that require more DP ram, we can expand the boundaries
21 * but then we have to be careful of any downloaded microcode.
23 #include <linux/errno.h>
24 #include <linux/sched.h>
25 #include <linux/kernel.h>
26 #include <linux/param.h>
27 #include <linux/string.h>
29 #include <linux/interrupt.h>
31 #include <asm/mpc8xx.h>
33 #include <asm/pgtable.h>
34 #include <asm/8xx_immap.h>
35 #include <asm/commproc.h>
38 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep);
40 static uint dp_alloc_base; /* Starting offset in DP ram */
41 static uint dp_alloc_top; /* Max offset + 1 */
42 static uint host_buffer; /* One page of host buffer */
43 static uint host_end; /* end + 1 */
44 cpm8xx_t *cpmp; /* Pointer to comm processor space */
46 /* CPM interrupt vector functions.
49 void (*handler)(void *, struct pt_regs * regs);
52 static struct cpm_action cpm_vecs[CPMVEC_NR];
53 static void cpm_interrupt(int irq, void * dev, struct pt_regs * regs);
54 static void cpm_error_interrupt(void *, struct pt_regs * regs);
55 static void alloc_host_memory(void);
61 volatile immap_t *imp;
62 volatile cpm8xx_t *commproc;
64 imp = (immap_t *)IMAP_ADDR;
65 commproc = (cpm8xx_t *)&imp->im_cpm;
67 #ifdef CONFIG_UCODE_PATCH
70 commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);
74 while (commproc->cp_cpcr & CPM_CR_FLG);
79 /* Set SDMA Bus Request priority 5.
80 * On 860T, this also enables FEC priority 6. I am not sure
81 * this is what we realy want for some applications, but the
82 * manual recommends it.
83 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
85 imp->im_siu_conf.sc_sdcr = 1;
87 /* Reclaim the DP memory for our use.
89 dp_alloc_base = CPM_DATAONLY_BASE;
90 dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE;
92 /* Tell everyone where the comm processor resides.
94 cpmp = (cpm8xx_t *)commproc;
97 /* We used to do this earlier, but have to postpone as long as possible
98 * to ensure the kernel VM is now running.
105 /* Set the host page for allocation.
107 host_buffer = (uint)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &physaddr);
108 host_end = host_buffer + PAGE_SIZE;
112 m8xx_cpm_reset(uint host_page_addr)
114 volatile immap_t *imp;
115 volatile cpm8xx_t *commproc;
118 imp = (immap_t *)IMAP_ADDR;
119 commproc = (cpm8xx_t *)&imp->im_cpm;
121 #ifdef CONFIG_UCODE_PATCH
124 commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);
128 while (commproc->cp_cpcr & CPM_CR_FLG);
133 /* Set SDMA Bus Request priority 5.
134 * On 860T, this also enables FEC priority 6. I am not sure
135 * this is what we realy want for some applications, but the
136 * manual recommends it.
137 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
139 imp->im_siu_conf.sc_sdcr = 1;
141 /* Reclaim the DP memory for our use.
143 dp_alloc_base = CPM_DATAONLY_BASE;
144 dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE;
146 /* Set the host page for allocation.
148 host_buffer = host_page_addr; /* Host virtual page address */
149 host_end = host_page_addr + PAGE_SIZE;
151 /* We need to get this page early, so I have to do it the
154 if (get_pteptr(&init_mm, host_page_addr, &pte)) {
155 pte_val(*pte) |= _PAGE_NO_CACHE;
156 flush_tlb_page(init_mm.mmap, host_buffer);
159 panic("Huh? No CPM host page?");
162 /* Tell everyone where the comm processor resides.
164 cpmp = (cpm8xx_t *)commproc;
168 /* This is called during init_IRQ. We used to do it above, but this
169 * was too early since init_IRQ was not yet called.
172 cpm_interrupt_init(void)
174 /* Initialize the CPM interrupt controller.
176 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr =
177 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
178 ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
179 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0;
181 /* Set our interrupt handler with the core CPU.
183 if (request_8xxirq(CPM_INTERRUPT, cpm_interrupt, 0, "cpm", NULL) != 0)
184 panic("Could not allocate CPM IRQ!");
186 /* Install our own error handler.
188 cpm_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
189 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN;
192 /* CPM interrupt controller interrupt.
195 cpm_interrupt(int irq, void * dev, struct pt_regs * regs)
199 /* Get the vector by setting the ACK bit and then reading
202 ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1;
203 vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr;
206 if (cpm_vecs[vec].handler != 0)
207 (*cpm_vecs[vec].handler)(cpm_vecs[vec].dev_id, regs);
209 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec);
211 /* After servicing the interrupt, we have to remove the status
214 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << vec);
218 /* The CPM can generate the error interrupt when there is a race condition
219 * between generating and masking interrupts. All we have to do is ACK it
220 * and return. This is a no-op function so we don't need any special
221 * tests in the interrupt handler.
224 cpm_error_interrupt(void *dev, struct pt_regs *regs)
228 /* Install a CPM interrupt handler.
231 cpm_install_handler(int vec, void (*handler)(void *, struct pt_regs *regs),
235 /* If null handler, assume we are trying to free the IRQ.
238 cpm_free_handler(vec);
242 if (cpm_vecs[vec].handler != 0)
243 printk("CPM interrupt %x replacing %x\n",
244 (uint)handler, (uint)cpm_vecs[vec].handler);
245 cpm_vecs[vec].handler = handler;
246 cpm_vecs[vec].dev_id = dev_id;
247 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << vec);
250 /* Free a CPM interrupt handler.
253 cpm_free_handler(int vec)
255 cpm_vecs[vec].handler = NULL;
256 cpm_vecs[vec].dev_id = NULL;
257 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec);
260 /* Allocate some memory from the dual ported ram. We may want to
261 * enforce alignment restrictions, but right now everyone is a good
265 m8xx_cpm_dpalloc(uint size)
269 if ((dp_alloc_base + size) >= dp_alloc_top)
270 return(CPM_DP_NOSPACE);
272 retloc = dp_alloc_base;
273 dp_alloc_base += size;
279 m8xx_cpm_dpalloc_index(void)
281 return dp_alloc_base;
284 /* We also own one page of host buffer space for the allocation of
285 * UART "fifos" and the like.
288 m8xx_cpm_hostalloc(uint size)
293 if (host_buffer == 0)
297 if ((host_buffer + size) >= host_end)
300 retloc = host_buffer;
306 /* Set a baud rate generator. This needs lots of work. There are
307 * four BRGs, any of which can be wired to any channel.
308 * The internal baud rate clock is the system clock divided by 16.
309 * This assumes the baudrate is 16x oversampled by the uart.
311 #define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq)
312 #define BRG_UART_CLK (BRG_INT_CLK/16)
313 #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
316 m8xx_cpm_setbrg(uint brg, uint rate)
320 /* This is good enough to get SMCs running.....
322 bp = (uint *)&cpmp->cp_brgc1;
324 /* The BRG has a 12-bit counter. For really slow baud rates (or
325 * really fast processors), we may have to further divide by 16.
327 if (((BRG_UART_CLK / rate) - 1) < 4096)
328 *bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;
330 *bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
331 CPM_BRG_EN | CPM_BRG_DIV16;