2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 #include <linux/config.h>
13 #include <asm/processor.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/cputable.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/offsets.h>
19 #include <asm/cache.h>
21 _GLOBAL(__setup_cpu_601)
23 _GLOBAL(__setup_cpu_603)
25 _GLOBAL(__setup_cpu_604)
27 bl setup_common_caches
31 _GLOBAL(__setup_cpu_750)
33 bl setup_common_caches
34 bl setup_750_7400_hid0
37 _GLOBAL(__setup_cpu_750cx)
39 bl setup_common_caches
40 bl setup_750_7400_hid0
44 _GLOBAL(__setup_cpu_750fx)
46 bl setup_common_caches
47 bl setup_750_7400_hid0
51 _GLOBAL(__setup_cpu_7400)
53 bl setup_7400_workarounds
54 bl setup_common_caches
55 bl setup_750_7400_hid0
58 _GLOBAL(__setup_cpu_7410)
60 bl setup_7410_workarounds
61 bl setup_common_caches
62 bl setup_750_7400_hid0
67 _GLOBAL(__setup_cpu_745x)
69 bl setup_common_caches
70 bl setup_745x_specifics
74 /* Enable caches for 603's, 604, 750 & 7400 */
78 ori r11,r11,HID0_ICE|HID0_DCE
80 bne 1f /* don't invalidate the D-cache */
81 ori r8,r8,HID0_DCI /* unless it wasn't enabled */
83 mtspr HID0,r8 /* enable and invalidate caches */
85 mtspr HID0,r11 /* enable caches */
90 /* 604, 604e, 604ev, ...
91 * Enable superscalar execution & branch history table
95 ori r11,r11,HID0_SIED|HID0_BHTE
98 mtspr HID0,r8 /* flush branch target address cache */
99 sync /* on 604e/604r */
105 /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
106 * erratas we work around here.
107 * Moto MPC710CE.pdf describes them, those are errata
109 * Note that we assume the firmware didn't choose to
110 * apply other workarounds (there are other ones documented
111 * in the .pdf). It appear that Apple firmware only works
112 * around #3 and with the same fix we use. We may want to
113 * check if the CPU is using 60x bus mode in which case
114 * the workaround for errata #4 is useless. Also, we may
115 * want to explicitely clear HID0_NOPDST as this is not
116 * needed once we have applied workaround #5 (though it's
117 * not set by Apple's firmware at least).
119 setup_7400_workarounds:
125 setup_7410_workarounds:
131 mfspr r11,SPRN_MSSSR0
132 /* Errata #3: Set L1OPQ_SIZE to 0x10 */
135 /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
137 /* Errata #5: Set DRLT_SIZE to 0x01 */
141 mtspr SPRN_MSSSR0,r11
147 * Enable Store Gathering (SGE), Address Brodcast (ABE),
148 * Branch History Table (BHTE), Branch Target ICache (BTIC)
149 * Dynamic Power Management (DPM), Speculative (SPD)
150 * Clear Instruction cache throttling (ICTC)
154 ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
156 oris r11,r11,HID0_DPM@h /* enable dynamic power mgmt */
157 END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
159 andc r11,r11,r3 /* clear SPD: enable speculative */
161 mtspr ICTC,r3 /* Instruction Cache Throttling off */
169 * Looks like we have to disable NAP feature for some PLL settings...
170 * (waiting for confirmation)
174 rlwinm r10,r10,4,28,31
178 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
179 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
181 lwz r6,CPU_SPEC_FEATURES(r5)
182 li r7,CPU_FTR_CAN_NAP
184 stw r6,CPU_SPEC_FEATURES(r5)
193 * Enable Store Gathering (SGE), Branch Folding (FOLD)
194 * Branch History Table (BHTE), Branch Target ICache (BTIC)
195 * Dynamic Power Management (DPM), Speculative (SPD)
196 * Ensure our data cache instructions really operate.
197 * Timebase has to be running or we wouldn't have made it here,
198 * just ensure we don't disable it.
199 * Clear Instruction cache throttling (ICTC)
200 * Enable L2 HW prefetch
202 setup_745x_specifics:
203 /* We check for the presence of an L3 cache setup by
204 * the firmware. If any, we disable NAP capability as
205 * it's known to be bogus on rev 2.1 and earlier
208 andis. r11,r11,L3CR_L3E@h
210 lwz r6,CPU_SPEC_FEATURES(r5)
211 andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
213 li r7,CPU_FTR_CAN_NAP
215 stw r6,CPU_SPEC_FEATURES(r5)
219 /* All of the bits we have to set.....
221 ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_LRSTK | HID0_BTIC
223 xori r11,r11,HID0_BTIC
224 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
226 oris r11,r11,HID0_DPM@h /* enable dynamic power mgmt */
227 END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
229 /* All of the bits we have to clear....
231 li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
232 andc r11,r11,r3 /* clear SPD: enable speculative */
235 mtspr ICTC,r3 /* Instruction Cache Throttling off */
241 /* Enable L2 HW prefetch
251 /* Definitions for the table use to save CPU states */
263 .balign L1_CACHE_LINE_SIZE
266 .balign L1_CACHE_LINE_SIZE,0
269 /* Called in normal context to backup CPU 0 state. This
270 * does not include cache settings. This function is also
271 * called for machine sleep. This does not include the MMU
272 * setup, BATs, etc... but rather the "special" registers
273 * like HID0, HID1, MSSCR0, etc...
275 _GLOBAL(__save_cpu_setup)
276 /* Some CR fields are volatile, we back it up all */
279 /* Get storage ptr */
280 lis r5,cpu_state_storage@h
281 ori r5,r5,cpu_state_storage@l
283 /* Save HID0 (common to all CONFIG_6xx cpus) */
287 /* Now deal with CPU type dependent registers */
290 cmplwi cr0,r3,0x8000 /* 7450 */
291 cmplwi cr1,r3,0x000c /* 7400 */
292 cmplwi cr2,r3,0x800c /* 7410 */
293 cmplwi cr3,r3,0x8001 /* 7455 */
294 cmplwi cr4,r3,0x8002 /* 7457 */
295 cmplwi cr5,r3,0x7000 /* 750FX */
296 /* cr1 is 7400 || 7410 */
297 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
299 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
300 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
301 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
303 /* Backup 74xx specific regs */
309 /* Backup 745x specific registers */
320 /* Backup 750FX specific registers */
323 /* If rev 2.x, backup HID2 */
334 /* Called with no MMU context (typically MSR:IR/DR off) to
335 * restore CPU state as backed up by the previous
336 * function. This does not include cache setting
338 _GLOBAL(__restore_cpu_setup)
339 /* Some CR fields are volatile, we back it up all */
342 /* Get storage ptr */
343 lis r5,(cpu_state_storage-KERNELBASE)@h
344 ori r5,r5,cpu_state_storage@l
354 /* Now deal with CPU type dependent registers */
357 cmplwi cr0,r3,0x8000 /* 7450 */
358 cmplwi cr1,r3,0x000c /* 7400 */
359 cmplwi cr2,r3,0x800c /* 7410 */
360 cmplwi cr3,r3,0x8001 /* 7455 */
361 cmplwi cr4,r3,0x8002 /* 7457 */
362 cmplwi cr5,r3,0x7000 /* 750FX */
363 /* cr1 is 7400 || 7410 */
364 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
366 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
367 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
368 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
370 /* Restore 74xx specific regs */
382 /* Clear 7410 L2CR2 */
386 /* Restore 745x specific registers */
408 /* Restore 750FX specific registers
409 * that is restore HID2 on rev 2.x and PLL config & switch
412 /* If rev 2.x, restore HID2 with low voltage bit cleared */
425 /* Wait for PLL to stabilize */
431 /* Setup final PLL */