2 * arch/ppc/kernel/cputable.c
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/config.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/threads.h>
16 #include <linux/init.h>
17 #include <asm/cputable.h>
19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
33 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
34 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
36 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
37 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
38 !defined(CONFIG_BOOKE))
40 /* This table only contains "desktop" CPUs, it need to be filled with embedded
43 #define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
46 /* We only set the altivec features if the kernel was compiled with altivec
50 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
51 #define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
53 #define CPU_FTR_ALTIVEC_COMP 0
54 #define PPC_FEATURE_ALTIVEC_COMP 0
57 /* We need to mark all pages as being coherent if we're SMP or we
58 * have a 74[45]x and an MPC107 host bridge.
60 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
61 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
63 #define CPU_FTR_COMMON 0
66 /* The powersave features NAP & DOZE seems to confuse BDI when
67 debugging. So if a BDI is used, disable theses
69 #ifndef CONFIG_BDI_SWITCH
70 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
71 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
73 #define CPU_FTR_MAYBE_CAN_DOZE 0
74 #define CPU_FTR_MAYBE_CAN_NAP 0
77 struct cpu_spec cpu_specs[] = {
80 0xffff0000, 0x00010000, "601",
82 CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
83 COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE,
88 0xffff0000, 0x00030000, "603",
90 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
91 CPU_FTR_MAYBE_CAN_NAP,
97 0xffff0000, 0x00060000, "603e",
99 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
100 CPU_FTR_MAYBE_CAN_NAP,
106 0xffff0000, 0x00070000, "603ev",
108 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
109 CPU_FTR_MAYBE_CAN_NAP,
115 0xffff0000, 0x00040000, "604",
117 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
124 0xfffff000, 0x00090000, "604e",
126 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
133 0xffff0000, 0x00090000, "604r",
135 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
142 0xffff0000, 0x000a0000, "604ev",
144 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
150 { /* 740/750 (0x4202, don't support TAU ?) */
151 0xffffffff, 0x00084202, "740/750",
153 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
154 CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
160 0xfffff000, 0x00083000, "745/755",
162 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
163 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
168 { /* 750CX (80100 and 8010x?) */
169 0xfffffff0, 0x00080100, "750CX",
171 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
172 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
177 { /* 750CX (82201 and 82202) */
178 0xfffffff0, 0x00082200, "750CX",
180 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
181 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
186 { /* 750CXe (82214) */
187 0xfffffff0, 0x00082210, "750CXe",
189 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
190 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
195 { /* 750FX rev 1.x */
196 0xffffff00, 0x70000100, "750FX",
198 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
199 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
200 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
205 { /* 750FX rev 2.0 must disable HID0[DPM] */
206 0xffffffff, 0x70000200, "750FX",
208 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
209 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
215 { /* 750FX (All revs except 2.0) */
216 0xffff0000, 0x70000000, "750FX",
218 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
219 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
220 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
226 0xffff0000, 0x70020000, "750GX",
227 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
228 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
229 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
234 { /* 740/750 (L2CR bit need fixup for 740) */
235 0xffff0000, 0x00080000, "740/750",
237 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
238 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
243 { /* 7400 rev 1.1 ? (no TAU) */
244 0xffffffff, 0x000c1101, "7400 (1.1)",
246 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
247 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
248 CPU_FTR_MAYBE_CAN_NAP,
249 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
254 0xffff0000, 0x000c0000, "7400",
256 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
257 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
258 CPU_FTR_MAYBE_CAN_NAP,
259 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
264 0xffff0000, 0x800c0000, "7410",
266 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
267 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
268 CPU_FTR_MAYBE_CAN_NAP,
269 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
273 { /* 7450 2.0 - no doze/nap */
274 0xffffffff, 0x80000200, "7450",
276 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
277 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
278 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT,
279 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
284 0xffffffff, 0x80000201, "7450",
286 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
287 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
288 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
289 CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
290 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
294 { /* 7450 2.3 and newer */
295 0xffff0000, 0x80000000, "7450",
297 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
298 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
299 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
300 CPU_FTR_NEED_COHERENT,
301 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
306 0xffffff00, 0x80010100, "7455",
308 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
309 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
310 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
311 CPU_FTR_NEED_COHERENT,
312 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
317 0xffffffff, 0x80010200, "7455",
319 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
320 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
321 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
322 CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
323 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
328 0xffff0000, 0x80010000, "7455",
330 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
331 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
332 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
333 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
334 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
338 { /* 7447/7457 Rev 1.0 */
339 0xffffffff, 0x80020100, "7447/7457",
341 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
342 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
343 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
344 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
345 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
349 { /* 7447/7457 Rev 1.1 */
350 0xffffffff, 0x80020101, "7447/7457",
352 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
353 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
354 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
355 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
356 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
360 { /* 7447/7457 Rev 1.2 and later */
361 0xffff0000, 0x80020000, "7447/7457",
363 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
364 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
365 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
366 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
367 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
372 0xffff0000, 0x80030000, "7447A",
374 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
375 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
376 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
377 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
378 COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
382 { /* 82xx (8240, 8245, 8260 are all 603e cores) */
383 0x7fff0000, 0x00810000, "82xx",
385 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
390 { /* All G2_LE (603e core, plus some) have the same pvr */
391 0x7fff0000, 0x00820000, "G2_LE",
392 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
393 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
398 { /* default match, we assume split I/D cache & TB (non-601)... */
399 0x00000000, 0x00000000, "(generic PPC)",
401 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
406 #endif /* CLASSIC_PPC */
407 #ifdef CONFIG_PPC64BRIDGE
409 0xffff0000, 0x00400000, "Power3 (630)",
411 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
412 COMMON_PPC | PPC_FEATURE_64,
417 0xffff0000, 0x00410000, "Power3 (630+)",
419 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
420 COMMON_PPC | PPC_FEATURE_64,
425 0xffff0000, 0x00360000, "I-star",
427 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
428 COMMON_PPC | PPC_FEATURE_64,
433 0xffff0000, 0x00370000, "S-star",
435 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
436 COMMON_PPC | PPC_FEATURE_64,
440 #endif /* CONFIG_PPC64BRIDGE */
443 0xffff0000, 0x00350000, "Power4",
445 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
446 COMMON_PPC | PPC_FEATURE_64,
451 0xffff0000, 0x00390000, "PPC970",
453 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
454 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
455 COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
460 0xffff0000, 0x003c0000, "PPC970FX",
462 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
463 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
464 COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
468 #endif /* CONFIG_POWER4 */
471 0xffff0000, 0x00500000, "8xx",
472 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
473 * if the 8xx code is there.... */
474 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
475 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
477 __setup_cpu_8xx /* Empty */
479 #endif /* CONFIG_8xx */
482 0xffffff00, 0x00200200, "403GC",
483 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
484 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
486 0, /*__setup_cpu_403 */
489 0xffffff00, 0x00201400, "403GCX",
490 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
491 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
493 0, /*__setup_cpu_403 */
496 0xffff0000, 0x00200000, "403G ??",
497 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
498 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
500 0, /*__setup_cpu_403 */
503 0xffff0000, 0x40110000, "405GP",
504 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
505 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
507 0, /*__setup_cpu_405 */
510 0xffff0000, 0x40130000, "STB03xxx",
511 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
512 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
514 0, /*__setup_cpu_405 */
517 0xffff0000, 0x41810000, "STB04xxx",
518 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
519 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
521 0, /*__setup_cpu_405 */
524 0xffff0000, 0x41610000, "NP405L",
525 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
526 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
528 0, /*__setup_cpu_405 */
531 0xffff0000, 0x40B10000, "NP4GS3",
532 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
533 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
535 0, /*__setup_cpu_405 */
538 0xffff0000, 0x41410000, "NP405H",
539 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
540 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
542 0, /*__setup_cpu_405 */
545 0xffff0000, 0x50910000, "405GPr",
546 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
547 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
549 0, /*__setup_cpu_405 */
552 0xffff0000, 0x51510000, "STBx25xx",
553 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
554 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
556 0, /*__setup_cpu_405 */
559 0xffff0000, 0x41F10000, "405LP",
560 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
561 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
563 0, /*__setup_cpu_405 */
565 { /* Xilinx Virtex-II Pro */
566 0xffff0000, 0x20010000, "Virtex-II Pro",
567 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
568 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
570 0, /*__setup_cpu_405 */
573 #endif /* CONFIG_40x */
576 0xf0000fff, 0x40000440, "440GP Rev. B",
577 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
578 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
580 0, /*__setup_cpu_440 */
583 0xf0000fff, 0x40000481, "440GP Rev. C",
584 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
585 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
587 0, /*__setup_cpu_440 */
590 0xf0000fff, 0x50000850, "440GX Rev. A",
591 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
592 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
594 0, /*__setup_cpu_440 */
597 0xf0000fff, 0x50000851, "440GX Rev. B",
598 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
599 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
601 0, /*__setup_cpu_440 */
604 0xf0000fff, 0x50000892, "440GX Rev. C",
605 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
606 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
608 0, /*__setup_cpu_440 */
610 #endif /* CONFIG_44x */
613 0xffff0000, 0x80200000, "e500",
614 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
615 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
616 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
618 0, /*__setup_cpu_e500 */
622 { /* default match */
623 0x00000000, 0x00000000, "(generic PPC)",
629 #endif /* !CLASSIC_PPC */