2 * arch/ppc/kernel/cputable.c
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/config.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/threads.h>
16 #include <linux/init.h>
17 #include <asm/cputable.h>
19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
33 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
35 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
36 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
37 !defined(CONFIG_BOOKE))
39 /* This table only contains "desktop" CPUs, it need to be filled with embedded
42 #define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
45 /* We only set the altivec features if the kernel was compiled with altivec
49 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
50 #define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
52 #define CPU_FTR_ALTIVEC_COMP 0
53 #define PPC_FEATURE_ALTIVEC_COMP 0
56 /* We only set the spe features if the kernel was compiled with
60 #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
62 #define PPC_FEATURE_SPE_COMP 0
65 /* We need to mark all pages as being coherent if we're SMP or we
66 * have a 74[45]x and an MPC107 host bridge.
68 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
69 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
71 #define CPU_FTR_COMMON 0
74 /* The powersave features NAP & DOZE seems to confuse BDI when
75 debugging. So if a BDI is used, disable theses
77 #ifndef CONFIG_BDI_SWITCH
78 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
79 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
81 #define CPU_FTR_MAYBE_CAN_DOZE 0
82 #define CPU_FTR_MAYBE_CAN_NAP 0
85 struct cpu_spec cpu_specs[] = {
88 .pvr_mask = 0xffff0000,
89 .pvr_value = 0x00010000,
91 .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
93 .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
94 PPC_FEATURE_UNIFIED_CACHE,
97 .cpu_setup = __setup_cpu_601
100 .pvr_mask = 0xffff0000,
101 .pvr_value = 0x00030000,
103 .cpu_features = CPU_FTR_COMMON |
104 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
105 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
106 .cpu_user_features = COMMON_PPC,
109 .cpu_setup = __setup_cpu_603
112 .pvr_mask = 0xffff0000,
113 .pvr_value = 0x00060000,
115 .cpu_features = CPU_FTR_COMMON |
116 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
117 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
118 .cpu_user_features = COMMON_PPC,
121 .cpu_setup = __setup_cpu_603
124 .pvr_mask = 0xffff0000,
125 .pvr_value = 0x00070000,
127 .cpu_features = CPU_FTR_COMMON |
128 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
129 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
130 .cpu_user_features = COMMON_PPC,
133 .cpu_setup = __setup_cpu_603
136 .pvr_mask = 0xffff0000,
137 .pvr_value = 0x00040000,
139 .cpu_features = CPU_FTR_COMMON |
140 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
141 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
142 .cpu_user_features = COMMON_PPC,
146 .cpu_setup = __setup_cpu_604
149 .pvr_mask = 0xfffff000,
150 .pvr_value = 0x00090000,
152 .cpu_features = CPU_FTR_COMMON |
153 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
154 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
155 .cpu_user_features = COMMON_PPC,
159 .cpu_setup = __setup_cpu_604
162 .pvr_mask = 0xffff0000,
163 .pvr_value = 0x00090000,
165 .cpu_features = CPU_FTR_COMMON |
166 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
167 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
168 .cpu_user_features = COMMON_PPC,
172 .cpu_setup = __setup_cpu_604
175 .pvr_mask = 0xffff0000,
176 .pvr_value = 0x000a0000,
178 .cpu_features = CPU_FTR_COMMON |
179 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
180 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
181 .cpu_user_features = COMMON_PPC,
185 .cpu_setup = __setup_cpu_604
187 { /* 740/750 (0x4202, don't support TAU ?) */
188 .pvr_mask = 0xffffffff,
189 .pvr_value = 0x00084202,
190 .cpu_name = "740/750",
191 .cpu_features = CPU_FTR_COMMON |
192 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
193 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
194 CPU_FTR_MAYBE_CAN_NAP,
195 .cpu_user_features = COMMON_PPC,
199 .cpu_setup = __setup_cpu_750
202 .pvr_mask = 0xfffff000,
203 .pvr_value = 0x00083000,
204 .cpu_name = "745/755",
205 .cpu_features = CPU_FTR_COMMON |
206 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
207 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
208 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
209 .cpu_user_features = COMMON_PPC,
213 .cpu_setup = __setup_cpu_750
215 { /* 750CX (80100 and 8010x?) */
216 .pvr_mask = 0xfffffff0,
217 .pvr_value = 0x00080100,
219 .cpu_features = CPU_FTR_COMMON |
220 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
221 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
222 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
223 .cpu_user_features = COMMON_PPC,
227 .cpu_setup = __setup_cpu_750cx
229 { /* 750CX (82201 and 82202) */
230 .pvr_mask = 0xfffffff0,
231 .pvr_value = 0x00082200,
233 .cpu_features = CPU_FTR_COMMON |
234 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
235 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
236 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
237 .cpu_user_features = COMMON_PPC,
241 .cpu_setup = __setup_cpu_750cx
243 { /* 750CXe (82214) */
244 .pvr_mask = 0xfffffff0,
245 .pvr_value = 0x00082210,
246 .cpu_name = "750CXe",
247 .cpu_features = CPU_FTR_COMMON |
248 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
249 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
250 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
251 .cpu_user_features = COMMON_PPC,
255 .cpu_setup = __setup_cpu_750cx
257 { /* 750FX rev 1.x */
258 .pvr_mask = 0xffffff00,
259 .pvr_value = 0x70000100,
261 .cpu_features = CPU_FTR_COMMON |
262 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
263 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
264 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
265 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
266 .cpu_user_features = COMMON_PPC,
270 .cpu_setup = __setup_cpu_750
272 { /* 750FX rev 2.0 must disable HID0[DPM] */
273 .pvr_mask = 0xffffffff,
274 .pvr_value = 0x70000200,
276 .cpu_features = CPU_FTR_COMMON |
277 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
278 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
279 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
281 .cpu_user_features = COMMON_PPC,
285 .cpu_setup = __setup_cpu_750
287 { /* 750FX (All revs except 2.0) */
288 .pvr_mask = 0xffff0000,
289 .pvr_value = 0x70000000,
291 .cpu_features = CPU_FTR_COMMON |
292 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
293 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
294 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
295 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
296 .cpu_user_features = COMMON_PPC,
300 .cpu_setup = __setup_cpu_750fx
303 .pvr_mask = 0xffff0000,
304 .pvr_value = 0x70020000,
306 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
307 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
308 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
310 CPU_FTR_HAS_HIGH_BATS,
311 .cpu_user_features = COMMON_PPC,
315 .cpu_setup = __setup_cpu_750fx
317 { /* 740/750 (L2CR bit need fixup for 740) */
318 .pvr_mask = 0xffff0000,
319 .pvr_value = 0x00080000,
320 .cpu_name = "740/750",
321 .cpu_features = CPU_FTR_COMMON |
322 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
323 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
324 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
325 .cpu_user_features = COMMON_PPC,
329 .cpu_setup = __setup_cpu_750
331 { /* 7400 rev 1.1 ? (no TAU) */
332 .pvr_mask = 0xffffffff,
333 .pvr_value = 0x000c1101,
334 .cpu_name = "7400 (1.1)",
335 .cpu_features = CPU_FTR_COMMON |
336 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
337 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
338 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
339 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
343 .cpu_setup = __setup_cpu_7400
346 .pvr_mask = 0xffff0000,
347 .pvr_value = 0x000c0000,
349 .cpu_features = CPU_FTR_COMMON |
350 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
351 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
352 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
353 CPU_FTR_MAYBE_CAN_NAP,
354 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
358 .cpu_setup = __setup_cpu_7400
361 .pvr_mask = 0xffff0000,
362 .pvr_value = 0x800c0000,
364 .cpu_features = CPU_FTR_COMMON |
365 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
366 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
367 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
368 CPU_FTR_MAYBE_CAN_NAP,
369 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
373 .cpu_setup = __setup_cpu_7410
375 { /* 7450 2.0 - no doze/nap */
376 .pvr_mask = 0xffffffff,
377 .pvr_value = 0x80000200,
379 .cpu_features = CPU_FTR_COMMON |
380 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
381 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
382 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
383 CPU_FTR_NEED_COHERENT,
384 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
388 .cpu_setup = __setup_cpu_745x
391 .pvr_mask = 0xffffffff,
392 .pvr_value = 0x80000201,
394 .cpu_features = CPU_FTR_COMMON |
395 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
396 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
397 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
398 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
399 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
400 CPU_FTR_NEED_COHERENT,
401 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
405 .cpu_setup = __setup_cpu_745x
407 { /* 7450 2.3 and newer */
408 .pvr_mask = 0xffff0000,
409 .pvr_value = 0x80000000,
411 .cpu_features = CPU_FTR_COMMON |
412 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
413 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
414 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
415 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
416 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
417 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
421 .cpu_setup = __setup_cpu_745x
424 .pvr_mask = 0xffffff00,
425 .pvr_value = 0x80010100,
427 .cpu_features = CPU_FTR_COMMON |
428 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
429 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
430 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
431 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
432 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
436 .cpu_setup = __setup_cpu_745x
439 .pvr_mask = 0xffffffff,
440 .pvr_value = 0x80010200,
442 .cpu_features = CPU_FTR_COMMON |
443 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
444 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
445 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
446 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
447 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
448 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
449 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
453 .cpu_setup = __setup_cpu_745x
456 .pvr_mask = 0xffff0000,
457 .pvr_value = 0x80010000,
459 .cpu_features = CPU_FTR_COMMON |
460 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
461 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
462 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
463 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
464 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
465 CPU_FTR_NEED_COHERENT,
466 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
470 .cpu_setup = __setup_cpu_745x
472 { /* 7447/7457 Rev 1.0 */
473 .pvr_mask = 0xffffffff,
474 .pvr_value = 0x80020100,
475 .cpu_name = "7447/7457",
476 .cpu_features = CPU_FTR_COMMON |
477 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
478 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
479 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
480 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
481 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
482 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
483 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
487 .cpu_setup = __setup_cpu_745x
489 { /* 7447/7457 Rev 1.1 */
490 .pvr_mask = 0xffffffff,
491 .pvr_value = 0x80020101,
492 .cpu_name = "7447/7457",
493 .cpu_features = CPU_FTR_COMMON |
494 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
495 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
496 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
497 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
498 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
499 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
500 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
504 .cpu_setup = __setup_cpu_745x
506 { /* 7447/7457 Rev 1.2 and later */
507 .pvr_mask = 0xffff0000,
508 .pvr_value = 0x80020000,
509 .cpu_name = "7447/7457",
510 .cpu_features = CPU_FTR_COMMON |
511 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
512 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
513 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
514 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
515 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
516 CPU_FTR_NEED_COHERENT,
517 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
521 .cpu_setup = __setup_cpu_745x
524 .pvr_mask = 0xffff0000,
525 .pvr_value = 0x80030000,
527 .cpu_features = CPU_FTR_COMMON |
528 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
529 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
530 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
531 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
532 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
533 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
537 .cpu_setup = __setup_cpu_745x
539 { /* 82xx (8240, 8245, 8260 are all 603e cores) */
540 .pvr_mask = 0x7fff0000,
541 .pvr_value = 0x00810000,
543 .cpu_features = CPU_FTR_COMMON |
544 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
546 .cpu_user_features = COMMON_PPC,
549 .cpu_setup = __setup_cpu_603
551 { /* All G2_LE (603e core, plus some) have the same pvr */
552 .pvr_mask = 0x7fff0000,
553 .pvr_value = 0x00820000,
555 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
556 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
557 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
558 .cpu_user_features = COMMON_PPC,
561 .cpu_setup = __setup_cpu_603
563 { /* default match, we assume split I/D cache & TB (non-601)... */
564 .pvr_mask = 0x00000000,
565 .pvr_value = 0x00000000,
566 .cpu_name = "(generic PPC)",
567 .cpu_features = CPU_FTR_COMMON |
568 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
570 .cpu_user_features = COMMON_PPC,
573 .cpu_setup = __setup_cpu_generic
575 #endif /* CLASSIC_PPC */
576 #ifdef CONFIG_PPC64BRIDGE
578 .pvr_mask = 0xffff0000,
579 .pvr_value = 0x00400000,
580 .cpu_name = "Power3 (630)",
581 .cpu_features = CPU_FTR_COMMON |
582 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
584 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
588 .cpu_setup = __setup_cpu_power3
591 .pvr_mask = 0xffff0000,
592 .pvr_value = 0x00410000,
593 .cpu_name = "Power3 (630+)",
594 .cpu_features = CPU_FTR_COMMON |
595 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
597 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
601 .cpu_setup = __setup_cpu_power3
604 .pvr_mask = 0xffff0000,
605 .pvr_value = 0x00360000,
606 .cpu_name = "I-star",
607 .cpu_features = CPU_FTR_COMMON |
608 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
610 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
614 .cpu_setup = __setup_cpu_power3
617 .pvr_mask = 0xffff0000,
618 .pvr_value = 0x00370000,
619 .cpu_name = "S-star",
620 .cpu_features = CPU_FTR_COMMON |
621 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
623 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
627 .cpu_setup = __setup_cpu_power3
629 #endif /* CONFIG_PPC64BRIDGE */
632 .pvr_mask = 0xffff0000,
633 .pvr_value = 0x00350000,
634 .cpu_name = "Power4",
635 .cpu_features = CPU_FTR_COMMON |
636 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
638 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
642 .cpu_setup = __setup_cpu_power4
645 .pvr_mask = 0xffff0000,
646 .pvr_value = 0x00390000,
647 .cpu_name = "PPC970",
648 .cpu_features = CPU_FTR_COMMON |
649 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
651 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
652 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
653 PPC_FEATURE_ALTIVEC_COMP,
657 .cpu_setup = __setup_cpu_ppc970
660 .pvr_mask = 0xffff0000,
661 .pvr_value = 0x003c0000,
662 .cpu_name = "PPC970FX",
663 .cpu_features = CPU_FTR_COMMON |
664 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
666 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
667 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
668 PPC_FEATURE_ALTIVEC_COMP,
672 .cpu_setup = __setup_cpu_ppc970
674 #endif /* CONFIG_POWER4 */
677 .pvr_mask = 0xffff0000,
678 .pvr_value = 0x00500000,
680 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
681 * if the 8xx code is there.... */
682 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
684 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
688 #endif /* CONFIG_8xx */
691 .pvr_mask = 0xffffff00,
692 .pvr_value = 0x00200200,
694 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
696 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
701 .pvr_mask = 0xffffff00,
702 .pvr_value = 0x00201400,
703 .cpu_name = "403GCX",
704 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
706 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
711 .pvr_mask = 0xffff0000,
712 .pvr_value = 0x00200000,
713 .cpu_name = "403G ??",
714 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
716 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
721 .pvr_mask = 0xffff0000,
722 .pvr_value = 0x40110000,
724 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
726 .cpu_user_features = PPC_FEATURE_32 |
727 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
732 .pvr_mask = 0xffff0000,
733 .pvr_value = 0x40130000,
734 .cpu_name = "STB03xxx",
735 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
737 .cpu_user_features = PPC_FEATURE_32 |
738 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
743 .pvr_mask = 0xffff0000,
744 .pvr_value = 0x41810000,
745 .cpu_name = "STB04xxx",
746 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
748 .cpu_user_features = PPC_FEATURE_32 |
749 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
754 .pvr_mask = 0xffff0000,
755 .pvr_value = 0x41610000,
756 .cpu_name = "NP405L",
757 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
759 .cpu_user_features = PPC_FEATURE_32 |
760 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
765 .pvr_mask = 0xffff0000,
766 .pvr_value = 0x40B10000,
767 .cpu_name = "NP4GS3",
768 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
770 .cpu_user_features = PPC_FEATURE_32 |
771 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
776 .pvr_mask = 0xffff0000,
777 .pvr_value = 0x41410000,
778 .cpu_name = "NP405H",
779 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
781 .cpu_user_features = PPC_FEATURE_32 |
782 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
787 .pvr_mask = 0xffff0000,
788 .pvr_value = 0x50910000,
789 .cpu_name = "405GPr",
790 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
792 .cpu_user_features = PPC_FEATURE_32 |
793 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
798 .pvr_mask = 0xffff0000,
799 .pvr_value = 0x51510000,
800 .cpu_name = "STBx25xx",
801 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
803 .cpu_user_features = PPC_FEATURE_32 |
804 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
809 .pvr_mask = 0xffff0000,
810 .pvr_value = 0x41F10000,
812 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
814 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
818 { /* Xilinx Virtex-II Pro */
819 .pvr_mask = 0xffff0000,
820 .pvr_value = 0x20010000,
821 .cpu_name = "Virtex-II Pro",
822 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
824 .cpu_user_features = PPC_FEATURE_32 |
825 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
830 #endif /* CONFIG_40x */
833 .pvr_mask = 0xf0000fff,
834 .pvr_value = 0x40000440,
835 .cpu_name = "440GP Rev. B",
836 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
838 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
843 .pvr_mask = 0xf0000fff,
844 .pvr_value = 0x40000481,
845 .cpu_name = "440GP Rev. C",
846 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
848 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
853 .pvr_mask = 0xf0000fff,
854 .pvr_value = 0x50000850,
855 .cpu_name = "440GX Rev. A",
856 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
858 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
863 .pvr_mask = 0xf0000fff,
864 .pvr_value = 0x50000851,
865 .cpu_name = "440GX Rev. B",
866 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
868 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
873 .pvr_mask = 0xf0000fff,
874 .pvr_value = 0x50000892,
875 .cpu_name = "440GX Rev. C",
876 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
878 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
882 #endif /* CONFIG_44x */
885 .pvr_mask = 0xffff0000,
886 .pvr_value = 0x80200000,
888 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
889 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
891 .cpu_user_features = PPC_FEATURE_32 |
892 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
893 PPC_FEATURE_HAS_EFP_SINGLE,
900 { /* default match */
901 .pvr_mask = 0x00000000,
902 .pvr_value = 0x00000000,
903 .cpu_name = "(generic PPC)",
904 .cpu_features = CPU_FTR_COMMON,
905 .cpu_user_features = PPC_FEATURE_32,
909 #endif /* !CLASSIC_PPC */